MPD78C18GQ-XXX-36

87AD SERIES µPD78C18 8-BIT SINGLE-CHIP MICROCONTROLLER © 1991 Document No. U10199EJ5V0UM00 (5th edition) (Previous No. IEU-1314) Date Published August 1995 P Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after poweron for devices having reset function. QTOP is a trademark of NEC Corporation. MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The customer must judge the need for license : µPD78C11, 78C11A, 78C12A, 78C14, 78C14A, 78CP14CW, 78CP14G-36, 78CP14GF-3BE, 78CP14L, 78C18, 78CP18CW, 78CP18GF-3BE, 78CP18GQ-36, 78C11(A), 78C11A(A), 78C12A(A), 78C14(A), 78CP14(A), 78C18(A), 78CP18(A) License not needed : µPD78C10, 78C10A, 78CG14, 78CP14DW, 78CP14KB, 78CP14R, 78C17, 78CP18DW, 78CP18KB, 78C10(A), 78C10A(A), 78C17(A) The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M7 94.11 INTRODUCTION Intended Readership: This manual is intended for engineers who require an understanding of 87AD series products functions prior to designing an application system or an application program. The relevant products are the following 87AD series CMOS version products. • µPD78C10A, 78C11A, 78C10A(A), 78C11A(A) • µPD78C12A, 78C12A(A) • µPD78C14, 78C14A, 78CG14, 78CP14, 78C14(A), 78CP14(A) • µPD78C17, 78C18, 78CP18, 78C17(A), 78C18(A), 78CP18(A) Remark µPD78C10, 78C11, 78C10(A), 78C11(A) have been maintenance products since October 1991. Purpose: The purposes of this manual is that users understand the hardware functions of 87AD series products shown in the organization below. Organization: This manual is mainly composed of the following contents. • General description • Pin functions • Internal block functions • Interrupt control functions • External device accesses and timing • PROM accesses • Instruction set • Operating precautions Using This Information: Use of this information requires general knowledge of electricity, logic circuits and microcontrollers. This manual describes the µPD78C18 as a representative product as long as there are no differences in the functions. Using this manual as the other 87AD series (CMOS) products manual, refer to the manual by changing "µPD78C18" to each product name. For the µPD78CG14, refer to APPENDIX A INTRODUCTION TO PIGGYBACK PRODUCT. For the "Special" quality grade product, refer to the manual by changing it to the "Standard" quality grade product. x For general understanding of the 87AD series (CMOS) product functions: ¬ Read in order of contents. x For searching for an instruction function by mnemonics: ¬ Use APPENDIX C INDEX OF INSTRUCTIONS (ALPHABETICAL ORDER). x For searching for mnemonics by the outline of functions: ¬ Search 14.6 Instruction Descriptions for the functions. Usage examples in this manual is produced for the "Standard" quality grade. Using this manual for the "Special" quality grade applications, make use of parts and circuits actually used after checking the quality grade. Operating Precaution Be sure to read CHAPTER 15 OPERATING PRECAUTIONS in which operating precautions of the 87AD series (CMOS) products are compiled. For the latest information of this products, contact our salesman or special agent. Legend: Data notation weight Notation of active low Address on the memory map Note Caution Remark Numeric notation : Upper digits to the left, lower digits to the right : ××× (A line over pin or signal names) : Lower address to the upper part, higher address to the lower part : Explanation of Note in text : Content to be read carefully : Complementary explanation of text : Binary .............. ××××B or ×××× Decimal ........... ×××× Hexadecimal ... ××××H Related Documents The following documents are provided for 87AD series CMOS version products. Numbers in the table are document numbers. Document Name Data Sheet Product Name User's Manual This manual • (I) Software fundamental IC-2678 IEM-1131 • (II) Floating-point format IC-2417 IC-2565 IC-2564 IC-2533 IC-2788 IC-2789 IC-3033 IC-2814 operation package IEM-1242 • (III) Hardware IEM-1240 Application Note µPD78C10 µPD78C11 µPD78C10A µPD78C11A µPD78C12A µPD78C14 µPD78C14A µPD78CG14 µPD78CP14 µPD78C17 µPD78C18 µPD78CP18 µPD78C10(A) µPD78C11(A) µPD78C10A(A) µPD78C11A(A) µPD78C12A(A) µPD78C14(A) µPD78CP14(A) µPD78C17(A) µPD78C18(A) µPD78CP18(A) IC-1872 IC-2846 IC-2813 IC-3068 IC-3127 IC-3233 The contents of the above documents are subject to change without prior notification. Please check whether requested documentation is the latest version. 87AD Series CMOS Version Development Expanded ROM/RAM capacity On-chip pull-up resistor (Mask option) Relative performance µ PD78C18 µ PD78CP18 (PROM product) µ PD78C17 (ROM-less product) µ PD78C14A PROM product µ PD78CP14 µ PD78C14 Expanded ROM capacity µ PD78C12A On-chip pull-up resistor (Mask option) On-chip pull-up Note resistor µ PD78C11Note (Mask option) µ PD78C10 (ROM-less product) µ PD78C11A µ PD78C10A (ROM-less product) µ PD7811H µ PD7810H (ROM-less product) CMOS process, on-chip pull-up resistors (Mask option) Time of product release Note µPD78C10 and 78C11 are maintenance products. TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION ........................................................................................... 1.1 1.2 Features ............................................................................................................................. Ordering Information and Quality Grade ..................................................................... 1.2.1 1.2.2 Ordering information ........................................................................................................... Quality grade ........................................................................................................................ Shrink DIP, QUIP (straight) (37), QUIP (36) ........................................................................ QFP (1B/3BE), WQFN ......................................................................................................... QFP (AB8) ............................................................................................................................ QFJ ....................................................................................................................................... 1 3 5 5 9 1.3 Pin Configurations (Top View) ....................................................................................... 1.3.1 1.3.2 1.3.3 1.3.4 10 10 13 15 16 1.4 1.5 1.6 1.7 Block Diagram................................................................................................................... Functional Comparison of 87AD Series CMOS Products ........................................... Differences between 87AD Series CMOS and NMOS Products ................................ Differences between "Standard" and "Special" Quality Grade Products ............... 18 19 21 22 23 23 23 23 23 25 26 27 27 27 28 28 28 28 28 28 29 29 29 29 29 29 29 CHAPTER 2 PIN FUNCTIONS ......................................................................................................... 2.1 Normal Operation Mode ................................................................................................. 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10 2.1.11 2.1.12 2.1.13 2.1.14 2.1.15 2.1.16 2.1.17 2.1.18 2.1.19 2.1.20 2.1.21 PA7 to PA0 (Port A) ............................................................................................................. PB7 to PB0 (Port B) ............................................................................................................. PC7 to PC0 (Port C) ............................................................................................................. PD7 to PD0 (Port D) ............................................................................................................ PF7 to PF0 (Port F) .............................................................................................................. WR (Write strobe) ............................................................................................................... RD (Read strobe) ................................................................................................................. ALE (Address latch enable) ................................................................................................. MODE0, MODE1 (Mode) .................................................................................................... NMI (Non maskable interrupt) ............................................................................................ INT1 (Interrupt request) ...................................................................................................... AN7 to AN0 (Analog input) ................................................................................................. VAREF (Reference voltage) .................................................................................................... AVDD (Analog VDD) ................................................................................................................ AVSS (Analog VSS) ................................................................................................................. STOP (Stop control input) ................................................................................................... X1, X2 (Crystal) .................................................................................................................... RESET (Reset) ..................................................................................................................... VDD ........................................................................................................................................ VSS ........................................................................................................................................ IC .......................................................................................................................................... A14 to A0 (Address) ............................................................................................................ O7 to O0 (Data) ................................................................................................................... CE (Chip enable) .................................................................................................................. 2.2 EPROM Mode .................................................................................................................... 2.2.1 2.2.2 2.2.3 30 30 30 30 –i– 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 OE (Output enable) ... ......................................................................................................... MODE1, MODE0 (Mode) .................................................................................................... RESET (Reset) ..................................................................................................................... VPP ........................................................................................................................................ VDD ........................................................................................................................................ VSS ........................................................................................................................................ 30 30 30 30 30 30 2.3 2.4 2.5 Pin Input/Output Circuits ................................................................................................ Pin Mask Options (µPD78C18/78C14A/78C12A/78C11A Only) ................................. Processing of Unused Pins ............................................................................................. 31 37 37 39 39 41 42 42 44 44 52 CHAPTER 3 INTERNAL BLOCK FUNCTIONS ............................................................................... 3.1 3.2 3.3 3.4 3.5 Registers ............................................................................................................................ Mode Registers ................................................................................................................. Arithmetic Logical Unit (ALU) ........................................................................................ Program Status Word (PSW) .......................................................................................... Memory .............................................................................................................................. 3.5.1 3.5.2 µPD78C18/78C17/78C14/78C14A/78C12A/78C11A/78C10A memory configuration ...... µPD78CP18/78CP14 memory configuration ...................................................................... 3.6 3.7 3.8 3.9 3.10 3.11 Timers ................................................................................................................................ Timer/Event Counter ....................................................................................................... Serial Interface .................................................................................................................. Analog/Digital Converter ................................................................................................ Interrupt Control .............................................................................................................. Zero-Cross Detector ......................................................................................................... 57 57 57 57 57 58 61 61 65 66 70 71 73 75 75 77 79 81 81 85 85 88 CHAPTER 4 PORT FUNCTIONS ..................................................................................................... 4.1 4.2 4.3 4.4 4.5 4.6 Port A (PA7 to PA0) ......................................................................................................... Port B (PB7 to PB0) .......................................................................................................... Port C (PC7 to PC0) .......................................................................................................... Port D (PD7 to PD0) ......................................................................................................... Port F (PF7 to PF0) ........................................................................................................... Operation of Arithmetic and Logical Operation Instruction Involving a Port and Immediate Data ................................................................................................................ CHAPTER 5 TIMER FUNCTIONS .................................................................................................... 5.1 5.2 5.3 Timer Configuration ......................................................................................................... Timer Mode Register (TMM) .......................................................................................... Timer Operations ............................................................................................................. CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS ................................................................... 6.1 6.2 Timer/Event Counter Configuration .............................................................................. Mode Registers ................................................................................................................. 6.2.1 6.2.2 Timer/event counter mode register (ETMM) ..................................................................... Timer/event counter output mode register (EOM) ............................................................ – ii – 6.3 Timer/Event Counter Operation .................................................................................... 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 Interval timer mode ............................................................................................................. Event counter mode ............................................................................................................ Frequency measurement mode .......................................................................................... Pulse width measurement mode ....................................................................................... Programmable rectangular-wave output mode .................................................................. Timer/event counter program examples ............................................................................ 90 90 92 93 94 95 97 CHAPTER 7 SERIAL INTERFACE FUNCTIONS ............................................................................. 7.1 7.2 Serial Interface Configuration ........................................................................................ Serial Mode Registers ..................................................................................................... 7.2.1 7.2.2 7.2.3 Serial mode high register (SMH) ........................................................................................ Serial mode low register (SML) .......................................................................................... Serial mode register initialization ........................................................................................ Asynchronous mode ............................................................................................................ Synchronous mode .............................................................................................................. I/O interface mode .............................................................................................................. Example of serial interface program .................................................................................. 107 107 109 109 112 114 7.3 Serial Interface Operation ............................................................................................... 7.3.1 7.3.2 7.3.3 7.3.4 114 114 121 123 127 CHAPTER 8 ANALOG/DIGITAL CONVERTER FUNCTIONS ....................................................... 8.1 8.2 8.3 Analog/Digital Converter Configuration....................................................................... A/D Channel Mode Register (ANM) .............................................................................. Analog/Digital Converter Operation ............................................................................. 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Scan mode ........................................................................................................................... Select mode ......................................................................................................................... A/D converter operation control method ........................................................................... Input voltage and conversion results ................................................................................. Example of analog/digital converter program .................................................................... 137 137 140 142 142 143 144 145 146 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS ....................................................................... 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Interrupt Control Circuit Configuration ........................................................................ External Interrupt Sampling ........................................................................................... Non-Maskable Interrupt Operation ............................................................................... Maskable Interrupt Operation ........................................................................................ Interrupt Operation by SOFTI Instruction .................................................................... Interrupt Wait Time ......................................................................................................... Multiple Interrupts ........................................................................................................... 153 154 158 160 163 167 168 169 171 171 171 172 174 175 CHAPTER 10 CONTROL FUNCTIONS ........................................................................................... 10.1 Standby Functions ........................................................................................................... 10.1.1 10.1.2 10.1.3 10.1.4 HALT mode .......................................................................................................................... HALT mode release ............................................................................................................. Software STOP mode ......................................................................................................... Software STOP mode release ............................................................................................ – iii – 10.1.5 10.1.6 10.1.7 Hardware STOP mode ........................................................................................................ Hardware STOP mode release ........................................................................................... Low supply voltage data retention mode........................................................................... 177 178 179 10.2 Reset Functions ................................................................................................................ 10.3 Clock Generation Circuit ................................................................................................. CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS ................................................... 11.1 µPD78C18/78C14/78C14A/78C12A/78C11A External Device Accesses .................... 11.1.1 11.1.2 11.1.3 11.2.1 Memory mapping register (MM) ........................................................................................ Example of memory expansion .......................................................................................... Example of peripheral device connection .......................................................................... MM register setting ............................................................................................................ 180 182 187 187 190 192 194 11.2 µPD78C17/78C10A External Device Access .................................................................. 11.3 Timings .............................................................................................................................. CHAPTER 12 PROM ACCESSES (µPD78CP18/78CP14 ONLY) ................................................... CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS (µPD78CP18/78CP14 ONLY) .......... 13.1 13.2 13.3 13.4 13.5 PROM Programming Operating Modes ........................................................................ PROM Writing Procedure ................................................................................................ PROM Reading Procedure ............................................................................................... Erasure Procedure (Ceramic Package Products Only) ................................................ One-Time PROM Products Screening ........................................................................... 198 199 201 203 207 208 209 210 211 211 213 213 215 216 216 217 218 218 219 CHAPTER 14 INSTRUCTION SET .................................................................................................. 14.1 Operand Notation and Description Method ................................................................ 14.2 Explanation of Operation Code Symbols ..................................................................... 14.3 Instruction Address Addressing..................................................................................... 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.4.6 14.4.7 14.4.8 14.4.9 Register addressing ............................................................................................................. Immediate addressing ......................................................................................................... Direct addressing ................................................................................................................. Relative addressing ............................................................................................................. Extended relative addressing .............................................................................................. Register addressing ............................................................................................................. Register indirect addressing ............................................................................................... Auto-increment addressing ................................................................................................. Auto-decrement addressing ................................................................................................ Double auto-increment addressing ..................................................................................... Base addressing .................................................................................................................. Base index addressing ........................................................................................................ Working register addressing ............................................................................................... Accumulator indirect addressing ........................................................................................ 14.4 Operand Address Addressing......................................................................................... 220 220 222 223 224 225 226 227 228 229 229 230 231 14.4.10 Immediate addressing ......................................................................................................... 14.4.11 Extended immediate addressing ........................................................................................ 14.4.12 Direct addressing ................................................................................................................. – iv – 14.5 14.6 Number of States Required for Skipping ................................................................... Instruction Descriptions ................................................................................................ 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.6.6 14.6.7 14.6.8 14.6.9 8-bit data transfer instructions ......................................................................................... 16-bit data transfer instructions ....................................................................................... 8-bit operation instructions (Register) ............................................................................. 8-bit operation instructions (Memory) ............................................................................. Immediate data operation instructions ............................................................................ Working register operation instructions .......................................................................... 16-bit operation instructions ............................................................................................ Multiplication/division instructions ................................................................................... Increment/decrement instructions ................................................................................... 232 233 233 242 252 263 270 285 294 300 301 304 306 313 316 319 321 323 14.6.10 Other operation instructions ............................................................................................ 14.6.11 Rotation/shift instructions ................................................................................................ 14.6.12 Jump instructions ............................................................................................................. 14.6.13 Call instructions ................................................................................................................ 14.6.14 Return instructions ........................................................................................................... 14.6.15 Skip instructions ............................................................................................................... 14.6.16 CPU control instructions ................................................................................................... 14.7 Stacked Instructions ...................................................................................................... 326 327 327 328 328 329 330 330 330 332 335 335 336 336 337 340 340 342 CHAPTER 15 OPERATING PRECAUTIONS ................................................................................... 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.12 RAE Bit Setting............................................................................................................... Port D/F Setting ............................................................................................................. Timer, Timer/Event Counter Compare Register Setting ......................................... Restrictions on Serial Interface and Asynchronous Modes .................................... Serial Interface Start Bit Input ..................................................................................... Serial Interface and Transmission Format Change .................................................. Input Voltage to Analog Input Pin .............................................................................. Limitations on Hardware STOP Mode ........................................................................ How to Use Standby Flag ............................................................................................. Bus Interface ................................................................................................................... Restrictions on IE-78C11-M Operation........................................................................ Electrostatic Withstand Limit of VPP Pin .................................................................... APPENDIX A INTROCUTION TO PIGGYBACK PRODUCT .......................................................... A.1 Pin Functions .................................................................................................................. A.1.1 A.1.2 Lower pins (µPD78C11A/78C12A/78C14 QUIP type compatible) ................................. Upper pins (27C256/27C256A compatible) ..................................................................... A.2 A.3 A.4 Memory Configuration .................................................................................................. Memory Mapping Register (MM) ................................................................................ Interface with EPROM ................................................................................................... 342 346 348 349 353 APPENDIX B DEVELOPMENT TOOLS........................................................................................... APPENDIX C INDEX OF INSTRUCTIONS (ALPHABETICAL ORDER) ........................................ –v– [MEMO] – vi – LIST OF FIGURES (1/3) Figure No. Title Page 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 Register Configuration ........................................................................................................... PSW Configuration ................................................................................................................ Memory Map (µPD78C18) ..................................................................................................... Memory Map (µPD78C17) ..................................................................................................... Memory Map (µPD78C14/78C14A) ....................................................................................... Memory Map (µPD78C12A) .................................................................................................. Memory Map (µPD78C11A) .................................................................................................. Memory Map (µPD78C10A) .................................................................................................. Memory Map (µPD78C18 Mode) .......................................................................................... Memory Map (µPD78C14 Mode) .......................................................................................... Memory Map (µPD78C12A Mode) ........................................................................................ Memory Map (µPD78C11A Mode) ........................................................................................ Zero-Cross Detector .............................................................................................................. Zero-Cross Detection Signal .................................................................................................. Zero-Cross Mode Register Format ........................................................................................ Port A ..................................................................................................................................... Mode A Register Format ....................................................................................................... Port A Specified as Output Port ............................................................................................. Port A Specified as Input Port ................................................................................................ Mode B Register Format ....................................................................................................... Mode Control C Register Format ........................................................................................... Mode C Register Format ....................................................................................................... Port C Specified as Control Signal Output ............................................................................. Port C Specified as Control Signal Input ................................................................................ Mode F Register Format ....................................................................................................... Timer Block Diagram ............................................................................................................. Timer Mode Register (TMM) Format ..................................................................................... Timer/Event Counter Block Diagram ..................................................................................... Timer/Event Counter Mode Register Format ........................................................................ Output Control Circuit Block Diagram (CO0 Output) ............................................................. Timer/Event Counter Output Mode Register Format ............................................................ Timer/Event Counter Setting Procedure ................................................................................ Timer/Event Counter Mode Register Setting (Interval Timer Mode) ..................................... Interval Timer Mode Operation .............................................................................................. Timer/Event Counter Mode Register Setting (Event Counter Mode) .................................... Event Counter Mode Operation ............................................................................................. Timer/Event Counter Mode Register Setting (Frequency Measurement Mode) ................... Frequency Measurement Mode Operation ........................................................................... Timer/Event Counter Mode Register Setting (Pulse Width Measurement Mode) ................ Pulse Width Measurement Mode Operation ........................................................................ Timer/Event Counter Output Mode Register Setting ............................................................ Timer/Event Counter Mode Register Setting (Programmable Rectangular-Wave Output Mode) ........................................................................................................................ Programmable Rectangular-Wave Output Mode Operation .................................................. Timer/Event Counter Mode Register Setting (Programmable Rectangular-Wave Output: ECNT Clear, CO0 Output Reset) ........................................................................................... Port C Setting (Programmable Rectangular-Wave Output) .................................................... Timer/Event Counter Mode Register Setting (Programmable Rectangular-Wave Output: ECNT Operation Setting) ....................................................................................................... Single Pulse Output ............................................................................................................... Port C Setting (Single Pulse Output) ..................................................................................... Interrupt Mask Register Setting (Single Pulse Output: INTEIN Mask Release) .................... Timer/Event Counter Mode Register Setting (Single Pulse Output: ECNT Operation Setting) .................................................................................................................. 39 42 46 47 48 49 50 51 53 54 55 56 58 58 59 61 61 62 62 65 66 67 68 68 71 76 78 81 87 88 89 90 91 91 92 92 93 93 94 95 95 96 96 98 98 99 100 101 101 102 – vii – LIST OF FIGURES (2/3) Figure No. Title Page 6-24 6-25 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Timer/Event Counter Mode Register Setting (Single Pulse Output: CO0 Output Timing Setting) ....................................................................................................................... Interrupt Mask Register (MKL) Setting (Single Pulse Output: INTE1 Mask Release) ........... Serial Interface Configuration ................................................................................................ Serial Mode High Register (SMH) Format ............................................................................. Serial Mode Low Register (SML) Format .............................................................................. Serial Mode Register Format in Asynchronous Mode ........................................................... Asynchronous Data Format ................................................................................................... Serial Mode Register Format in Synchronous Mode ............................................................. Synchronous Mode Timing .................................................................................................... Serial Mode Register Format in I/O Interface Mode .............................................................. I/O Interface Mode Timing ..................................................................................................... Example of Serial Data Transfer System Configuration ......................................................... Serial Mode Register Setting ................................................................................................. Timer Mode Register Setting ................................................................................................ Port C Setting (Serial Interface) ............................................................................................. Serial Mode High Register (SMH) Setting (Serial Interface: Transmission Enable) .............. Interrupt Mask Register (MKH) Setting (Serial Interface: INTSR Mask Release) ................. Serial Mode High Register (SMH) Setting (Serial Interface: Reception Enable) ................... A/D Converter Block Diagram ................................................................................................ A/D Channel Mode Register Format ..................................................................................... A/D Channel Mode Register in Scan Mode ........................................................................... Outline of A/D Converter Operation Timing in Scan Mode .................................................... A/D Channel Mode Register in Select Mode ......................................................................... Outline of A/D Converter Operation Timing in Select Mode ................................................. Relationship Between Analog Input Voltage and A/D Conversion Results ............................ Memory Map (Store Example of A/D Conversion Result) ..................................................... A/D Channel Mode Register Settings .................................................................................... Interrupt Control Circuit Block Diagram ................................................................................. Mask Register (MKL, MKH) Format ...................................................................................... Interrupt Sampling ................................................................................................................. Interrupt Operation Procedure ............................................................................................... Internal Configuration of NMI Pin .......................................................................................... Interrupt Servicing Sequence (Masking released for both INT1 and INT2) ............................ Interrupt Servicing Sequence (Masking released for either INT1 or INT2) ............................ 3-Level Multiple Interrupts ..................................................................................................... HALT Mode Release Timing (RESET Signal Input) ................................................................ HALT Mode Release Timing (In EI State) .............................................................................. HALT Mode Release Timing (In DI State) .............................................................................. Software STOP Mode Release Timing (RESET Signal Input) ................................................ SB Flag Operation .................................................................................................................. Software STOP Mode Release Timing (NMI Signal Input) .................................................... Hardware STOP Mode Release Timing (STOP Signal Input) ................................................. Hardware STOP Mode Release Timing (RESET Signal Input) ............................................... Hardware STOP Mode Release Timing (STOP Signal Rising to RESET Signal Input) ........... Relation between VDD and SB Flag ........................................................................................ Oscillator Connection Circuit ................................................................................................. Example of External Clock Input Circuit ................................................................................. Examples of Poor Resonator Connection Circuit ................................................................... 103 104 107 111 113 115 118 121 122 123 124 127 128 129 130 130 133 133 138 141 142 143 143 144 145 146 147 154 156 159 161 162 164 165 169 172 173 173 175 176 176 178 178 179 179 182 182 183 – viii – LIST OF FIGURES (3/3) Figure No. Title Page 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 12-1 12-2 13-1 13-2 15-1 15-2 15-3 15-4 15-5 15-6 A-1 A-2 A-3 A-4 A-5 External Expansion Modes Set by Memory Mapping Register ............................................. Memory Mapping Register Format (µPD78C18/78C14/78C14A/78C12A/78C11A) .............. Example of Memory Expansion (Reference Diagram) ........................................................... Memory Mapping Register Settings ..................................................................................... µPD71055 Connection Diagram (Reference Diagram) .......................................................... Memory Map (µPD78C18) ..................................................................................................... Memory Map (µPD78C14/78C14A) ....................................................................................... Memory map (µPD78C12A) .................................................................................................. Memory Map (µPD78C11A) .................................................................................................. MM Register Format (µPD78C17/78C10A) ........................................................................... µPD78C17 Address Space .................................................................................................... µPD78C10A Address Space .................................................................................................. OP Code Fetch Timing ........................................................................................................... External Device Read Timing ................................................................................................. External Device Write Timing ................................................................................................ Memory Mapping Register Format (µPD78CP18) ................................................................. Memory Mapping Register Format (µPD78CP14) ................................................................. PROM Write/Verify Timing .................................................................................................... PROM Read Timing ............................................................................................................... Analog Input Circuit Block Diagram ....................................................................................... When Both NMI and STOP Are Used .................................................................................... Control Timing of NMI and STOP .......................................................................................... When Both NMI and STOP Are Used .................................................................................... Control Timing of RESET and STOP ...................................................................................... µPD78C18 Read Operation ................................................................................................... Memory Map (µPD78C14 Mode) .......................................................................................... Memory Map (µPD78C12A Mode) ........................................................................................ Memory Map (µPD78C11A Mode) ........................................................................................ Memory Mapping Register Format (µPD78CG14) ................................................................ Connection to 27C256A ......................................................................................................... 189 191 192 193 195 196 196 197 197 199 199 200 202 202 202 204 205 209 210 331 332 333 334 334 335 343 344 345 347 348 – ix – [MEMO] –x– LIST OF TABLES Table No. Title Page 2-1 2-2 2-3 2-4 2-5 3-1 3-2 4-1 4-2 4-3 4-4 6-1 6-2 6-3 6-4 7-1 7-2 7-3 8-1 9-1 9-2 10-1 10-2 10-3 10-4 10-5 11-1 13-1 13-2 13-3 15-1 Operation of PC7 to PC0 ....................................................................................................... Operation of PF7 to PF0 (µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14) .... Operation of PF7 to PF0 (µPD78C17/78C10A) ...................................................................... MODE0 and MODE1 Functions (µPD78C17/78C10A) .......................................................... Pin Type No. .......................................................................................................................... Mode Register Functions ...................................................................................................... Flag Operations ...................................................................................................................... Operation of PD7 to PD0 (µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14) ... Operation of PF7 to PF0 (µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14) .... Operation of PF7 to PF0 (µPD78C17/78C10A) ...................................................................... Operation of Arithmetic/Logical Operation Instructions Involving a Port ............................... Timing for Latching in ECPT .................................................................................................. ECNT Inputs .......................................................................................................................... ECNT Clearing ........................................................................................................................ INTEIN Interrupt Request Flag Setting .................................................................................. Timer Setting ......................................................................................................................... Maximum Data Transfer Rate at Transmission ..................................................................... Maximum Data Transfer Rate at Reception .......................................................................... Conversion Speed Settings ................................................................................................... Priorities and Interrupt Addresses ......................................................................................... Maximum Interrupt Wait Time .............................................................................................. Output Pin Statuses ............................................................................................................... Output Pin Statuses ............................................................................................................... Hardware States after Reset ................................................................................................. Pin States after Reset ............................................................................................................ Recommended Ceramic Resonator ....................................................................................... PF7 to PF0 Address Bus Selection ........................................................................................ Pin Functions in PROM Programming ................................................................................... PROM Programming Modes ................................................................................................. Recommended Connection of Unused Pins (In PROM Programming Mode) ....................... Compare Register, Match Signal and Match Interrupt of Each Timer ................................... 24 26 27 28 31 41 43 70 72 72 73 82 83 84 84 118 119 120 140 153 168 171 174 180 181 185 187 207 208 208 328 – xi – CHAPTER 1 GENERAL DESCRIPTION CMOS version products in the 87AD series have the following functions integrated in a single chip: • • • • • • ROM (except µPD78C17, 78C10A) RAM 16-bit ALU A/D converter Multi-function timers/event counters General-purpose serial interface, etc. 87AD series CMOS products offer enhanced standby functions and a wide range of packages while maintaining compatibility with existing NMOS products. This allows further reductions in system low power consumption and size to be achieved. The features of the various products are shown below. Product Name On-Chip ROM None 4K × 8 bits 8K × 8 bits 16K × 8 bits On-Chip RAM 256 × 8 bits 256 × 8 bits 256 × 8 bits 256 × 8 bits External Expansion Memory Up to 64K bytes Remarks ROM-less product µPD78C10A µPD78C10A(A) µPD78C11A µPD78C11A(A) µPD78C12A µPD78C12A(A) µPD78C14 µPD78C14(A) µPD78C14A µPD78CP14 µPD78CP14(A) µPD78CG14 µPD78C17 µPD78C17(A) µPD78C18 µPD78C18(A) µPD78CP18 µPD78CP18(A) Up to 60K bytes On-chip pull-up resistor specifiable Up to 56K bytes On-chip pull-up resistor specifiable Up to 48K bytes — On-chip pull-up resistor specifiable PROM product 16K × 8 bits (external) None 32K × 8 bits 1K × 8 bits 1K × 8 bits Up to 63K bytes Piggy-back product ROM-less product Up to 31K bytes On-chip pull-up resistor specifiable PROM product 1 CHAPTER 1 GENERAL DESCRIPTION In the µPD78CP18/78CP14, the on-chip mask ROM of the µPD78C18/78C14 is replaced with one-time PROM or EPROM. One-time PROM products can be programmed once only, and are useful for short-run and multiple-device set production and early start-up. EPROM products can be programmed and reprogrammed, and are ideally suited to system evaluation. The relationship between "Standard" quality grade products and "Special" quality grade products. "Standard" Quality Grade Products "Special" Quality Grade Products µPD78C10A µPD78C11A µPD78C12A µPD78C14 µPD78CP14 µPD78C17 µPD78C18 µPD78CP18 Applications µPD78C10A(A) µPD78C11A(A) µPD78C12A(A) µPD78C14(A) µPD78CP14(A) µPD78C17(A) µPD78C18(A) µPD78CP18(A) • The "Standard" Products • Stationary machine and OA equipment .... PPC (Plain paper copier), printer, electronic typewriter, ECR (Electronic cash register), FAX, bar code reader, etc. • Automobile equipment ............................... Automobile air conditioner, cellular phone (communication), etc. • Home electric appliances ........................... Air conditioner, VCRs, etc. • Others ......................................................... Electronic musical instrument, POS (Point of sales terminal), inverter, electronic sewing machine, auto focus cameras, etc. • The "Special" Products • Automobile equipment ............................... Automobile electronic equipment, fuel control 2 CHAPTER 1 GENERAL DESCRIPTION 1.1 Features • 159 types of instructions • Multiplication/division instructions, 16-bit operation instructions possible • Minimum instruction execution time • 0.8 µs (at 15 MHz operation) • ROM capacity • 32768 × 8 bits (µPD78C18/78CP18Note 1) • 16384 × 8 bits (µPD78C14, 78C14A, 78CP14Note 1) • • 8192 × 8 bits (µPD78C12A) 4096 × 8 bits (µPD78C11A) (µPD78C17/78C10A) • ROM-less • RAM capacityNote 2 • • 1024 × 8 bits (µPD78C18/78CP18/78C17) 256 × 8 bits (µPD78C14/78C14A/78CP14/78C12A/78C11A/78C10A) • 8-bit resolution A/D converter • 8 channels • General-purpose serial interface • Asynchronous mode • Synchronous mode • I/O interface mode • 16-bit timer/event counter • 1 channel • 8-bit timer • 2 channels • Interrupt functions (3 external, 8 internal) • Non-maskable interrupt : • Maskable interrupts : 1 10 • 6 priority levels, 6 interrupt addresses Notes 1. 2. µPD78CP18/78CP14 have on-chip one-time PROM or EPROM. On-chip RAM can only be used when the RAE bit of the MM register is "1". 3 CHAPTER 1 GENERAL DESCRIPTION • I/O lines • Input/output ports : 40 (µPD78C18/78CP18/78C14/78C14A/78CP14/78C12A/78C11A) : 28 (µPD78C17/78C10A) • Edge-detected inputs : 4 inputs • Zero-cross detection function • Standby functions • HALT mode • Hardware/software STOP mode • Incorporation of pull-up resistors can be specified bit wise for port A and port C.Note • On-chip clock oscillator • Wide variety of packages Note µPD78C18/78C14A/78C12A/78C11A only. 4 CHAPTER 1 GENERAL DESCRIPTION 1.2 Ordering Information and Quality Grade 1.2.1 Ordering information (1) µPD78C10A/78C10A(A) Part number Package 64-pin plastic shrink DIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 68-pin plastic QFJ 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 68-pin plastic QFJ µPD78C10ACW µPD78C10AGF-3BE µPD78C10AGQ-36 µPD78C10AL µPD78C10AGF(A)-3BE µPD78C10AGQ(A)-36 µPD78C10AL(A) (2) µPD78C11A/78C11A(A) Part number Package 64-pin plastic shrink DIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 64-pin plastic QUIP (straight) 68-pin plastic QFJ 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 68-pin plastic QFJ µPD78C11ACW-××× µPD78C11AGF-×××-3BE µPD78C11AGQ-×××-36 µPD78C11AGQ-×××-37 µPD78C11AL-××× µPD78C11AGF(A)-×××-3BE µPD78C11AGQ(A)-×××-36 µPD78C11AL(A)-××× Remark ××× indicates ROM code number. 5 CHAPTER 1 GENERAL DESCRIPTION (3) µPD78C12A/78C12A(A) Part number Package 64-pin plastic shrink DIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 64-pin plastic QUIP (straight) 68-pin plastic QFJ 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 68-pin plastic QFJ µPD78C12ACW-××× µPD78C12AGF-×××-3BE µPD78C12AGQ-×××-36 µPD78C12AGQ-×××-37 µPD78C12AL-××× µPD78C12AGF(A)-×××-3BE µPD78C12AGQ(A)-×××-36 µPD78C12AL(A)-××× Remark ××× indicates ROM code number. 6 CHAPTER 1 GENERAL DESCRIPTION (4) µPD78C14/78C14(A)/78C14A/78CG14/78CP14/78CP14(A) Part number Package 64-pin plastic shrink DIP 64-pin plastic QUIP 64-pin plastic QUIP (straight) 64-pin plastic QFP (resin thickness: 2.05 mm) 64-pin plastic QFP (resin thickness: 2.7 mm) 68-pin plastic QFJ 64-pin plastic QUIP 64-pin plastic QFP (resin thickness: 2.7mm) 68-pin plastic QFJ 64-pin plastic QFP (inter-pin pitch: 0.8 mm) 64-pin ceramic piggyback QUIP 64-pin plastic shrink DIP 64-pin ceramic shrink DIP with window 64-pin plastic QUIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin ceramic WQFN 68-pin plastic QFJ 64-pin ceramic QUIP with window 64-pin plastic QUIP µPD78C14CW-××× µPD78C14G-×××-36 µPD78C14G-×××-37 µPD78C14G-×××-1B µPD78C14GF-×××-3BE µPD78C14L-××× µPD78C14G(A)-×××-36 µPD78C14GF(A)-×××-3BE µPD78C14L(A)-××× µPD78C14AG-×××-AB8 µPD78CG14E µPD78CP14CW µPD78CP14DW µPD78CP14G-36 µPD78CP14GF-3BE µPD78CP14KB µPD78CP14L µPD78CP14R µPD78CP14G(A)-36 Remark ××× indicates ROM code number. 7 CHAPTER 1 GENERAL DESCRIPTION (5) µPD78C17/78C17(A) Part number Package 64-pin plastic shrink DIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP µPD78C17CW µPD78C17GF-3BE µPD78C17GQ-36 µPD78C17GF(A)-3BE µPD78C17GQ(A)-36 (6) µPD78C18/78C18(A)/78CP18/78CP18(A) Part number Package 64-pin plastic shrink DIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 64-pin plastic shrink DIP 64-pin ceramic shrink DIP with window 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP 64-pin ceramic WQFN 64-pin plastic QFP (resin thickness: 2.7 mm) 64-pin plastic QUIP µPD78C18CW-××× µPD78C18GF-×××-3BE µPD78C18GQ-×××-36 µPD78C18GF(A)-×××-3BE µPD78C18GQ(A)-×××-36 µPD78CP18CW µPD78CP18DW µPD78CP18GF-3BE µPD78CP18GQ-36 µPD78CP18KB µPD78CP18GF(A)-3BE µPD78CP18GQ(A)-36 Remark ××× indicates ROM code number. 8 CHAPTER 1 GENERAL DESCRIPTION 1.2.2 Quality grade • Standard µPD78C10A µPD78C11A µPD78C12A µPD78C14 • Special µPD78C14A µPD78CG14 µPD78CP14 µPD78C17 µPD78C18 µPD78CP18 µPD78C10A(A) µPD78C11A(A) µPD78C12A(A) µPD78C14(A) µPD78CP14(A) µPD78C17(A) µPD78C18(A) µPD78CP18(A) Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 9 CHAPTER 1 GENERAL DESCRIPTION 1.3 Pin Configurations (Top View) 1.3.1 Shrink DIP, QUIP (straight) (37), QUIP (36) (1) Normal operation mode PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/TXD PC1/RXD PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 NMI INT1 MODE1 RESET MODE0 X2 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD STOP PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD VAREF AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS 10 CHAPTER 1 GENERAL DESCRIPTION PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PF7 to PF0 NMI INT1 MODE0, 1 : Port A : Port B : Port C : Port D : Port F : Non Maskable Interrupt : Interrupt Request : Mode0, 1 X1, X2 AN7 to AN0 RD WR ALE RESET VAREF STOP : Crystal : Analog Input : Read Strobe : Write Strobe : Address Latch Enable : Reset : Reference Voltage : Stop Control Input 11 CHAPTER 1 GENERAL DESCRIPTION (2) EPROM mode (µPD78CP18/78CP14 only) A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD VPP O7 O6 O5 O4 O3 O2 O1 O0 A14 A13 A12 A11 A10 A8 12 13 14 CE OE 15 16 17 18 19 20 21 22 23 24 A9 MODE1 RESET MODE0 25 26 27 28 29 30 31 32 Cautions : : : Connect directly to VSS. Pull down individually to VSS potential via a resistor. µPD78CP18 only. In case of µPD78CP14, pull down to VSS potential via a resistor. 12 CHAPTER 1 GENERAL DESCRIPTION 1.3.2 QFP (1B/3BE), WQFN (1) Normal operation mode STOP PD7 PD6 PD5 PD4 PD3 PA5 PA4 PA3 PA2 PA1 PA0 VDD PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/TXD PC1/RXD PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 NMI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PD2 PD1 PD0 PF7 A14 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD VAREF AN7 AN6 AN5 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS INT1 MODE1 MODE0 RESET AVSS X2 X1 AN0 AN1 AN2 AN3 AN4 13 CHAPTER 1 GENERAL DESCRIPTION (2) EPROM mode (µPD78CP18/78CP14 only) VDD VPP O7 O6 O5 O4 O3 A5 A4 A3 A2 A1 A0 A6 A7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 O2 O1 O0 A14 A13 A12 A11 A10 A8 CE OE 9 10 11 12 13 14 15 16 17 18 A9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MODE1 RESET MODE0 Cautions : : : Connect directly to VSS. Pull down individually to VSS potential via a resistor. µPD78CP18 only. In the case of µPD78CP14, pull down to VSS potential via a resistor. 14 CHAPTER 1 GENERAL DESCRIPTION 1.3.3 QFP (AB8) PC3/INT2 PC6/CO0 PC2/SCK PC1/RXD PC0/TXD PC4/TO PC5/CI PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7/CO1 NMI INT1 MODE1 RESET MODE0 X2 X1 VSS AVSS AN0 AN1 AN2 AN3 AN4 AN5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 3 4 5 6 7 8 9 10 11 12 13 14 15 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VDD STOP PD7 PD6 PD5 PD4 PD3 PD2 PD1 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VAREF AVDD AN6 AN7 RD WR ALE PD0 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 15 CHAPTER 1 GENERAL DESCRIPTION 1.3.4 QFJ (1) Normal operation mode IC PA6 PA5 PA4 PA3 PA2 PA1 PA0 VDD STOP PD7 PD6 PD5 PD4 PD3 PD2 IC PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/TXD PC1/RXD PC2/SCK PC3/INT2 IC PC4/TO PC5/IC PC6/CO0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD IC VAREF AN7 16 PC7/CO1 NMI INT1 MODE1 RESET MODE0 X2 X1 VSS AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 Remark IC: Internally connected CHAPTER 1 GENERAL DESCRIPTION (2) EPROM mode (µPD78CP14 only) Open A6 A5 A4 A3 A2 A1 A0 VDD VPP O7 O6 O5 O4 O3 O2 Open A7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 CE OE O1 O0 A13 A12 A11 A10 A8 Open Open A9 MODE1 RESET MODE0 Cautions Open : Leave open. : Connect directly to VSS. : Pull down individually to VSS potential via a resistor. 17 Port F Serial I/O Port D 8 Port C Timer PC4/TO PC5/CI PC6/CO0 PC7/CO1 AN7–0 8 VAREF AVDD AVSS A/D converter Timer/event counter 8 Port B 16 8 ALU (8/16) 16 16 Port A 18 X1 OSC X2 PC0/TXD PC1/RXD PC2/SCK 8 NMI INTI 4 1.4 Block Diagram INT control 8 16 Latch INC/DEC PC SP EA V A B C D E H L EA' V' A' B' C' D' E' H' L' Buffer 8/16 8 16 15 / 14 / 12 Main G. R Program memory (Depends on product) 16 8 8 8 8 PF7–0 AB15–8 8 8 8 PD7–0 AD7–0 ALT G. R Data Note memory (Depends on product) CHAPTER 1 8 PC7–0 PC3/INT2/TI 8 Internal data bus 16 Latch 6 PSW 8 8 8 INST. REG 8 INST. decoder 8 8 PB7–0 GENERAL DESCRIPTION 8 Latch 8 PA7–0 Read/write control Note Can only be used when the RAE bit of the MM register is 1; when 0, external memory is required. System control Standby control RD WR ALE MODE1 MODE0 RESET STOP VDD VSS 1.5 Functional Comparison of 87AD Series CMOS Products Product Name Item Instructions Minimum instruction execution time On-chip ROM On-chip RAM Interrupts External Internal Timer/counter A/D converter Serial interface I/O linesNote µPD78C10A µPD78C11A µPD78C12A 159 0.8 µs (at 15 MHz operation) µPD78C14 µPD78C14A ROM-less 4K × 8 bits 8K × 8 bits 256 × 8 bits 3 8 8-bit timer × 2, 16-bit timer/event counter × 1 8 bit × 8 channels UART (full duplex)/clocked 16K × 8 bits CHAPTER 1 32 • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) • 64-pin plastic QUIP • 68-pin plastic QFJ • 64-pin • 64-pin • 64-pin • 64-pin • 68-pin plastic plastic plastic plastic plastic shrink DIP (750 mil) QFP (14 × 20 mm) QUIP QUIP (straight) QFJ 44 • 64-pin plastic QFP (14 × 14 mm) Package GENERAL DESCRIPTION (to be continued) Note Incorporation of pull-up resistors can be specified by mask option for port A and port C of the µPD78C11A/78C12A. 19 20 Item Instructions Interrupts I/O linesNote Package Product Name µPD78CP14 µPD78CG14 µPD78C17 159 0.8 µs (at 15 MHz operation) µPD78C18 µPD78CP18 Minimum instruction execution time On-chip ROM 16K × 8 bits (PROM) 256 × 8 bits External Internal Timer/counter A/D converter Serial interface 44 • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) • 64-pin plastic QUIP • 68-pin plastic QFJ • 64-pin ceramic shrink DIP with window (750 mil) • 64-pin ceramic QUIP with window • 64-pin ceramic WQFN • 64-pin ceramic piggyback QUIP 16K × 8 bits (piggyback) ROM-less 32K × 8 bits 1K × 8 bits 32K × 8 bits (PROM) On-chip RAM 3 8 8-bit timer × 2, 16-bit timer/event counter × 1 8 bit × 8 channels UART (full duplex)/clocked 32 • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) • 64-pin plastic QUIP 44 • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) • 64-pin plastic QUIP • 64-pin ceramic shrink DIP with window (750 mil) • 64-pin ceramic WQFN CHAPTER 1 GENERAL DESCRIPTION Note Incorporation of pull-up resistors can be specified by mask option for port A and port C of the µPD78C14A/78C18. CHAPTER 1 GENERAL DESCRIPTION 1.6 Differences between 87AD Series CMOS and NMOS Products Process Item Product name CMOS NMOS µPD78C18/78C17/78C14/78C14A/78C12A/ 78C11A/78C10A 159 (STOP instruction added) 28 (ZCM register added) 3 modes: HALT mode, software STOP mode, hardware STOP mode. On-chip RAM data retained at low supply voltage (2.5 V) in software/hardware STOP mode. 12 Stopped Low level Self-bias control possible (by ZCM register specification) By analog delay µPD7811/7810 158 27 32-byte data of 256-byte on-chip RAM retained at low supply voltage (3.2 V). Instructions Special registers Standby function HLT instruction states HALT mode CPU operation ALE Self-bias control of zero-cross detector NMI/RESET noise elimination method A/D converter 11 M3, T2 cycle repetition High level Self-bias control not possible By clock sampling Operation stoppable (VAREF pin manipulation) RD/WR ALE PD/PF (ROM-less products) High impedance Operation not stoppable Operation during reset High level Output 0 output to pin specified by address bus. Remainder are high impedance. Power consumption PackageNote 2 Operating Standby 64-pin 64-pin 64-pin 64-pin 68-pin 65 mW Typ. (15 MHz)Note 1 5 µW Typ. plastic plastic plastic plastic plastic shrink DIP QUIP (straight) QUIP QFP (bent leads) QFJ 750 mW Typ. 4.8 mW Typ. 64-pin plastic shrink DIP 64-pin plastic QUIP (straight) 64-pin plastic QUIP Pin connection (except QFP & QFJ) VDD (pin 64) STOP (pin 63) VCC (pin 64) VDD (pin 63) Notes 1. 2. 80 mW (15 MHz) on the µPD78C18/78C17/78C14/78C14A. Correspondence between pin connection and pin number depends on the type of package. Caution There are also differences in electrical specifications, oscillator characteristics, and some internal operation timings: These should be noted when directly replacing a µPD7811/7810 with a µPD78C18/ 78C17/78C14/78C14A/78C12A/78C11A/78C10A. 21 22 Item Package 1.7 Differences between "Standard" and "Special" Quality Grade Products Product Name µPD78C10A, µPD78C11A, µPD78C12A µPD78C14, µPD78CP14 Standard µPD78C17, µPD78C18 µPD78C10A(A), µPD78C11A(A), µPD78C12A(A) µPD78C14(A), µPD78CP14(A) Special µPD78C17(A), µPD78C18(A), µPD78CP18(A) Quality grade Electrical specifications Input leak current AN7 to AN0; ± 10 µA (MAX.) • 64-pin • 64-pin • 64-pin • 64-pin • 68-pin plastic plastic plastic plastic plastic Input leak current AN7 to AN0; ± 1 µA (MAX.) • 64-pin plastic shrink DIP • 64-pin plastic QFP • 64-pin plastic QUIP • 64-pin plastic QFP • 64-pin plastic QUIP • 68-pin plastic QFJ • 64-pin plastic QFPNote 2 • 64-pin plastic QUIP • 68-pin plastic QFJNote 2 • 64-pin plastic QFP • 64-pin plastic QUIP shrink DIP QUIP QUIP (straight)Note 1 QFP QFJ CHAPTER 1 Notes 1. 2. Except µPD78C10/78C10A. Except µPD78CP14(A). GENERAL DESCRIPTION CHAPTER 2 PIN FUNCTIONS The µPD78C18/78C17/78C14/78C14A/78C12A/78C11A/78C10A operate with normal operation mode pin functions. µPD78CP18/78CP14 pin functions are of two kinds: Normal operation mode and EPROM mode. EPROM mode is entered by driving the MODE1 pin low and the MODE0 pin high. 2.1 Normal Operation Mode 2.1.1 PA7 to PA0 (Port A) ... 3-state input/output These are the 8-bit input/output pins of port A (8-bit input/output port with output latch), and can be specified bitwise as input/output by means of the Mode A register (MA). Upon RESET input, PA7 to PA0 are set as input port (high-impedance). PA7 to PA0 also become high-impedance in the hardware STOP mode. In the µPD78C18/78C14A/78C12A/78C11A, pull-up resistors can be incorporated bit-wise. 2.1.2 PB7 to PB0 (Port B) ... 3-state input/output These are the 8-bit input/output pins of port B (8-bit input/output port with output latch), and can be specified bitwise as input/output by means of the Mode B register (MB). Upon RESET input, PB7 to PB0 are set as an input port (high-impedance). PB7 to PB0 also become high-impedance in the hardware STOP mode. In the µPD78C18/78C14A/78C12A/78C11A, pull-up resistors can be incorporated bit-wise. 2.1.3 PC7 to PC0 (Port C) ... 3-state input/output These pins operate as the 8-bit input/output pins of port C (8-bit input/output port with output latch), but in addition to functioning as an input/output port, they also function as pins for various control signals. The PC7 to PC0 operating mode can be set bit-wise to port or control signal input/output mode by means of the Mode Control C register (MCC) (see Table 2-1). In the µPD78C18/78C14A/78C12A/78C11A, pull-up resistors can be incorporated bit-wise. 23 CHAPTER 2 PIN FUNCTIONS Table 2-1. Operation of PC7 to PC0 MCCn=0 Port Mode PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port MCCn=1 Control Signal Input/Output Mode TxD output RxD input SCK input/output INT2/TI input TO output CI input CO0 output CO1 output Remark n=0 to 7 (1) Port mode When PC7 to PC0 are specified as input/output port by means of the mode control C register, they can be set bit-wise as input or output port by means of the mode C register (MC). (2) Control signal input/output mode PC7 to PC0 can be set bit-wise as control pins by means of the mode control C register (MCC). The functions of the various control pins are shown below. (a) TxD (Transmit data) ... Output The serial data transmission pin, from which the contents of the serial register are output. (b) RxD (Receive data) ... Input The serial data reception pin: Data on RxD is loaded into the serial register. (c) SCK (Serial clock) ... Input/output The serial input/output data control clock: Functions as an output when the internal clock is used, and as an input when an external clock is used. (d) INT2/TI (Interrupt request/Timer input) ... Input The edge-triggered (falling edge) maskable interrupt input pin and timer external clock input pin. Can also be used as the AC signal zero-cross detection pin. Caution When pull-up resistors are incorporated in PC3 of the µPD78C18/78C14A/78C12A/78C11A, the zero-cross function can not be operated correctly. (e) TO (Timer output) ... Output Outputs a square wave with the timer count time or one cycle of the internal clock (φ3) as a half-cycle. (f) CI (Counter input) ... Input The timer/event counter external pulse input. (g) CO0, CO1 (Counter output) ... Output These pins output a rectangular wave which is programmable by the timer/event counter. Upon RESET input, PC7 to PC0 are set as input port (high-impedance). PC7 to PC0 also become high-impedance in the hardware STOP mode. 24 CHAPTER 2 PIN FUNCTIONS 2.1.4 PD7 to PD0 (Port D) ... 3-state input/output µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14 These are the 8-bit input/output pins of port D (8-bit input/output port with output latch), but in addition to functioning as an input/output port, they also function as time-division address output and data input/output (multiplexed address/data bus) pins for accessing externally expanded memory. Pins PD7 to PD0 can be specified as shown below by setting the memory mapping register. (1) Port mode As port D input/output pins, PD7 to PD0 can be specified as input or output as a byte (8-bit) unit. (2) Expansion mode When an external device (program memory, data memory, or a peripheral device) is added in addition to onchip memory, PD7 to PD0 are used as a multiplexed address/data bus (AD7 to AD0). When an instruction which references an external device is executed, the lower address information for the external device is output in the first state of the external device reference machine cycle of that instruction, and the pins become a bidirectional 8-bit data bus in the second and third states. At all other times, PD7 to PD0 are high-impedance. Cautions 1. When pins PD7 to PD0 are functioning as an address/data bus, the contents of the internal address bus are output as they are in synchronization with ALE in the first state of all machine cycles. 2. Emulation cannot be performed by an emulator for a program which varies the port D operating mode dynamically. Therefore, once the mode has been set, it should not be changed to a different mode. Upon RESET input, PD7 to PD0 are set as input port (high-impedance). PD7 to PD0 also become high-impedance in the hardware STOP mode. µPD78C17/78C10A These pins function only as time-division address output and data input/output (multiplexed address/data bus) pins for accessing externally installed memory. The pins output the lower 8 bits of the memory address in the first state, and become a bidirectional 8-bit data bus in the second and third states. When the RESET signal is low, or when in the hardware STOP mode or a standby mode (HALT or STOP), PD7 to PD0 are high-impedance. Caution Port D can only be used as an address/data bus. 25 CHAPTER 2 PIN FUNCTIONS 2.1.5 PF7 to PF0 (Port F) ... 3-state input/output µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14 These are the 8-bit input/output pins of port F (8-bit input/output port with output latch), but in addition to functioning as an input/output port, they also function as address outputs (AB15 to AB8) for accessing externally expanded memory. Pins PF7 to PF0 can be specified as shown below by setting the memory mapping register. (1) Port mode As port F input/output pins, PF7 to PF0 can be specified bit-wise as input or output by means of the mode F register. (2) Expansion mode When an external device is expanded in addition to on-chip memory, PF7 to PF0 are used as an address bus (AB15 to AB8) corresponding to the size of the external device, as shown in Table 2-2. When an instruction which references an external device is executed, the upper address information for the external device is output in the external device reference machine cycle of that instruction. Caution Pins PF7 to PF0 set as an address bus have output to them the contents of the internal address bus as they are in all machine cycles. Pins not specified as address output pins are in port mode. Caution Emulation cannot be performed by an emulator for a program which varies the port F operating mode dynamically. Therefore, once the mode has been set, it should not be changed to a different mode. Table 2-2. Operation of PF7 to PF0 (µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14) PF7 Port Port Port AB15 PF6 Port Port Port AB14 PF5 Port Port AB13 AB13 PF4 Port Port AB12 AB12 PF3 Port AB11 AB11 AB11 PF2 Port AB10 AB10 AB10 PF1 Port AB9 AB9 AB9 PF0 Port AB8 AB8 AB8 External Address Space Up to 256 bytes Up to 4K bytes Up to 16K bytes Up to 31K/48K/56K/60K bytesNote Note 31K(µPD78C18), 48K (µPD78C14/78C14A), 56K (µPD78C12A), 60K (µPD78C11A) The operation of the µPD78CP18 and 78CP14 differ depending on the setting of bits MM5 to MM7 of the memory mapping register. In the reset state (RESET input=low) or in the hardware STOP mode (STOP input=low), pins PF7 to PF0 become high-impedance. When the RESET input or STOP input subsequently returns to the high level, they are set as address bus or port according to the status of the MODE1 and MODE0 pins. 26 CHAPTER 2 PIN FUNCTIONS µPD78C17/78C10A These pins can be specified as an address bus (AB15 to AB8) corresponding to the size of the externally installed device by means of the MODE0 and MODE1 pin settings, and the remaining pins can be used as general-purpose input/output ports (see Table 2-3). Table 2-3. Operation of PF7 to PF0 (µPD78C17/78C10A) MODE1 0 0 1 1 MODE0 0 1 0 1 AB15 AB14 AB13 AB12 PF7 Port Port PF6 Port Port PF5 Port AB13 PF4 Port AB12 PF3 AB11 AB11 PF2 AB10 AB10 PF1 AB9 AB9 PF0 AB8 AB8 External Address Space 4K bytes 16K bytes Setting prohibited AB11 AB10 AB9 AB8 63K/64K bytesNote Note 63K (µPD78C17), 64K (µPD78C10A) In the reset state (RESET input=low) or in the hardware STOP mode (STOP input=low), pins PF7 to PF0 become high-impedance. When the RESET input or STOP input subsequently returns to the high level, they are set as address bus or port according to the status of the MODE1 and MODE0 pins. Caution Emulation cannot be performed by an emulator for a program which varies the port F operating mode dynamically. Therefore, once the mode has been set, it should not be changed to a different mode. 2.1.6 WR (Write strobe) ... 3-state output The strobe signal output for a write operation to external memory. This pin is driven high except in external memory data write machine cycles. When the RESET signal is low or when in the hardware STOP mode, WR become highimpedance. Remark In a data write to internal RAM, WR is driven high. 2.1.7 RD (Read strobe) ... 3-state output The strobe signal output for a read operation on external memory. This pin is driven high except in external memory data read machine cycles. When the RESET signal is low or when in the hardware STOP mode, RD become highimpedance. Remark In a data read from internal ROM or RAM, RD is driven high. 2.1.8 ALE (Address latch enable) ... 3-state output The strobe signal which externally latches the lower address information output to pins PD7 to PD0 for an access to external memory. When the RESET signal is low or when in the hardware STOP mode, ALE is high-impedance. Caution ALE output continues while the CPU is operating. Therefore, address latching by ALE is effective external access machine cycles. 27 CHAPTER 2 PIN FUNCTIONS 2.1.9 MODE0, MODE1 (Mode) ... Input/output µPD78C18/78C14/78C14A/78C12A/78C11A The MODE0 pin is set to "0" (low level) and the MODE1 pin is set to "1" (high level) via a pull-up resistor. The pull-up resistor R is 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] (tCYC unit is ns). When the MODE0 pin is set to "0" (low level) and the MODE1 pin is not "1" (high level), on-chip ROM is not accessed and these pins are functioned in the same way as those of the µPD78C17/78C10A. µPD78C17/78C10A The size of the externally installed memory can be selected as 4K bytes, 16K bytes, or 63K/64K bytes according to the settings of the MODE0 and MODE1 pins. Table 2-4. MODE0 and MODE1 Functions (µPD78C17/78C10A) MODE1 0 0 1 1Note 1 MODE0 0 1Note 1 0 1Note 1 External Address Space 4K bytes (addresses 0000H to 0FFFH) 16K bytes (addresses 0000H to 3FFFH) Setting prohibited 63K bytes (addresses 0000H to FBFFH)/ Note 2 64K bytes (addresses 0000H to FEFFH) Notes 1. Pull-up resistor required. The pull-up resistor R is 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] (tCYC unit is ns). 2. 63K (µPD78C17), 64K (µPD78C10A). When the MODE0 and MODE1 pins are pulled high up to "1", a control signal is output in synchronization with ALE. The MODE0 and MODE1 input signals are sampled periodically and the mode is set. Caution The µPD78CP18 and 78CP14 use the MODE0 pin for input and the MODE1 pin for input/output. 2.1.10 NMI (Non maskable interrupt) ... Input The edge-triggered (falling edge) non maskable interrupt input. 2.1.11 INT1 (Interrupt request) ... Input The edge-triggered (rising edge) maskable interrupt input. Can also be used as the AC input zero-cross detection pin. 2.1.12 AN7 to AN0 (Analog input) ... Input The 8 analog inputs to the A/D converter. AN7 to AN4 can also be used as input pins for falling edge detection; when a falling edge is detected, the test flag is set (1). 2.1.13 VAREF (Reference voltage) ... Input The A/D converter reference voltage input pin. Also used as the A/D converter operation control pin. 2.1.14 AVDD (Analog VDD) The A/D converter power supply supply pin. 28 CHAPTER 2 PIN FUNCTIONS 2.1.15 AVSS (Analog VSS) The A/D converter GND pin. 2.1.16 STOP (Stop control input) The hardware STOP mode control pin; oscillation is stopped when this pin is driven low. 2.1.17 X1, X2 (Crystal) Crystal connection pins for internal clock oscillation. When the clock is supplied from off chip, the clock should be input to X1, and the inverted X1 clock to X2. 2.1.18 RESET (Reset) ... Input The low-level active reset pin. 2.1.19 VDD The positive power supply pin. 2.1.20 VSS GND potential. 2.1.21 ICNote Internally connected pin. Leave open. Note QFJ package only. 29 CHAPTER 2 PIN FUNCTIONS 2.2 EPROM Mode The EPROM mode can only be specified for the µPD78CP18/78CP14. 2.2.1 A14 to A0 (Address) ... Input The 15-bit address input pins for an EPROM write/verify or read operation. The on-chip EPROM of the µPD78CP14 is 16K bytes in size, and is therefore addressed by the lower 14 bits (A13 to A0). PF6 should be fixed low. 2.2.2 O7 to O0 (Data) ... Input/output The 8-bit data input/output pins for an EPROM write/verify or read operation. 2.2.3 CE (Chip enable) ... Input The Chip Enable signal input pin. 2.2.4 OE (Output enable) ... Input The Output Enable signal input pin. 2.2.5 MODE1, MODE0 (Mode) ... Input The MODE1 pin should be set to "0" (low level) and the MODE0 pin to "1" (high level). 2.2.6 RESET (Reset) ... Input Should be set to "0" (low level). 2.2.7 VPP The high-voltage application pin for an EPROM write/verify operation. Inputs "1" (high level) in an EPROM read. 2.2.8 VDD The power supply application pin. 2.2.9 VSS The GND potential pin. 30 CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits The input/output circuits for the pins are shown in partially simplified format in Table 2-5 and Figures (1) to (15). Table 2-5. Pin Type No. Type No. Pin Name PA0 to PA7 PB0 to PB7 PC0, PC1 PC2/SCK PC3/INT2 PC4 to PC7 PD0 to PD7 PF0 to PF7 NMI INT1 RESET RD WR ALE STOP MODE0 MODE1 AN0 to AN3 AN4 to AN7 VAREF µPD78C17/78C14/78C10A 5 5 5 8 10 5 5 5 2 9 2 4 4 4 2 11 11 7 12 13 µPD78C18/78C14A/ 78C12A/78C11A 5-A 5-A 5-A 8-A 10-A 5-A 31 CHAPTER 2 PIN FUNCTIONS (1) Type 1 VDD P-ch IN N-ch (2) Type 2 IN (3) Type 4 VDD Output data P-ch OUT Output disable N-ch 32 CHAPTER 2 PIN FUNCTIONS (4) Type 4-A VDD Output data P-ch Mask option OUT Output disable N-ch (5) Type 5 Output data Type 4 Output disable IN/OUT Type 1 (6) Type 5-A Output data Type 4-A Output disable IN/OUT Type 1 (7) Type 7 AVDD IN AVDD P-ch N-ch + – Sampling C AVSS AVSS Reference voltage (From voltage tap of series resistance string) 33 CHAPTER 2 PIN FUNCTIONS (8) Type 8 Output data Output disable N-ch Type 5 IN/OUT N-ch Type 2 MCC (9) Type 8-A Output data Output disable N-ch Type 5-A IN/OUT N-ch Type 2 MCC (10) Type 9 Self-bias circuit enable IN Type 1 Data 34 CHAPTER 2 PIN FUNCTIONS (11) Type 10 Output data Output disable N-ch Self-bias circuit enable N-ch Type 5 IN/OUT Type 9 MCC (12) Type 10-A Output data Output disable N-ch Self bias circuit enable N-ch Type 5-A IN/OUT Type 9 MCC 35 CHAPTER 2 PIN FUNCTIONS (13) Type 11 IN/OUT Output data N-ch Type 1 (14) Type 12 IN Type 7 Type 2 Edge detector (15) Type 13 IN Type 1 STOP mode P-ch AVSS 36 CHAPTER 2 PIN FUNCTIONS 2.4 Pin Mask Options (µPD78C18/78C14A/78C12A/78C11A Only) The following mask options are available for pins, and these can be selected bit-wise to suit the purpose. Pin Name PA7 to PA0 PB7 to PB0 PC7 to PC0 Mask Option Pull-up resistor incorporated Pull-up resistor not incorporated Caution If a pull-up resistor is incorporated in PC3, the zero-cross function cannot be operated correctly. 2.5 Processing of Unused Pins Pin PA0 PB0 PC0 PD0 PF0 to to to to to PA7 PB7 PC7 PD7 PF7 Recommended Connection Connect to VSS or VDD via a resistor. RD WR ALE STOP INT1, NMI AVDD VAREF AVSS AN0 to AN7 Leave open. VDD Connect to VSS or VDD. Connect to VDD. Connect to VSS. Connect to AVSS or AVDD. 37 [MEMO] 38 CHAPTER 3 INTERNAL BLOCK FUNCTIONS 3.1 Registers The central registers are the sixteen 8-bit registers, four 16-bit registers and special registers shown in Figure 3-1. Figure 3-1. Register Configuration 15 PC SP 15 EA 7 V B D H 15 EA' 7 V' B' D' H' 07 A' C' E' L' 0 ALT 07 A C E L 0 0 Main 0 0 (1) Accumulator (A) Since an accumulator type architecture is used, data processing such as 8-bit arithmetic and logical operation instructions centers on this accumulator. This accumulator can be replaced with the ALT register paired with the vector register (V) by means of the EXA instruction. (2) Expansion accumulator (EA) Data processing such as 16-bit arithmetic and logical operation instructions centers on this accumulator. This accumulator can be replaced with the ALT register EA' by means of the EXA instruction. 39 CHAPTER 3 INTERNAL BLOCK FUNCTIOS (3) Working register vector register (V) When a working area is set in the memory space, the high-order 8 bits of the memory address are selected using the V register and the low-order 8 bits are addressed by the immediate data in the instruction. Thus, the memory area specified with the V register can be used as working registers with a 256 × 8-bit configuration. Because a working register can be specified with a 1-byte address field, program reduction is possible by using the working area for software flags, parameters and counters. The V register can be replaced with the ALT register paired with an accumulator by means of the EXA instruction. (4) General registers (B, C, D, E, H, L) There are two sets of general registers (main: B, C, D, E, H, L; ALT: B', C', D', E', H', L'). They function as auxiliary registers for the accumulator, and have a data pointer function as register pairs (BC, DE, HL; B'C', D'E', H'L'). Four register pairs, DE, D'E', HL and H'L' in particular, have a base register function. When the two sets are used, if an interrupt occurs in one set, the register contents are saved into the other register set without saving them into the memory so that interrupt servicing can be carried out. The other set of registers can also be used as a data pointer expansion registers. Single-step auto-increment/decrement modes and a two-step auto-increment addressing mode are available for the register pairs, DE, HL, D'E' and H'L', so that the processing time can be reduced. BC, DE and HL can be simultaneously replaced with the ALT register by means of the EXX instruction. The HL register can be independently replaced with the ALT register by means of the EXH instruction. (5) Program counter (PC) This is a 16-bit register which holds information on the next program address to be executed. This register is normally incremented automatically according to the number of bytes of the instruction to be fetched. When an instruction associated with a branch is executed, immediate data or register contents are loaded. RESET input clears this counter to 0000H. (6) Stack pointer (SP) This is a 16-bit register which holds the start address of the memory stack area (LIFO format). SP contents are decremented when a call or PUSH instruction is executed or an interrupt is generated, and incremented when a return or POP instruction is executed. 40 CHAPTER 3 INTERNAL BLOCK FUNCTIONS 3.2 Mode Registers Mode registers are provided (see Table 3-1) to control the ports, timers, timer/event counters, serial interface, A/D converter and interrupt control blocks. Table 3-1. Mode Register Functions Read/ Write W W W W W W R/W W R/W W R/W Interrupt mask register R/W Specifies interrupt request enable/disable. Mode Register Name MA MB MCC MC MM MF TMM ETMM EOM SML SMH MKL MKH ANM ZCM A/D channel mode register Zero-cross mode register Mode A register Mode B register Mode control C register Mode C register Memory mapping register Mode F register Timer mode register Timer/event counter mode register Timer/event counter output mode register Serial mode register Function Performs bit-wise input/output specification for port A. Performs bit-wise input/output specification for port B. Performs bit-wise port/control mode specification for port C. Performs bit-wise input/output specification for port C when in port mode. Performs port/expansion mode specification for port D and port F. Performs bit-wise input/output specification for port F when in port mode. Specifies timer operating mode. Specifies timer/event counter operating mode. Controls CO0 and CO1 output level. Specifies serial interface operating mode. R/W W Specifies A/D converter operating mode. Specifies zero-cross detector operation. 41 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 3.3 Arithmetic Logical Unit (ALU) The ALU executes data processing such as 8-bit arithmetic and logical operations, shift and rotation, data processing such as 16-bit arithmetic and logical operations and shift operations, 8-bit multiplication and 16-bit by 8bit division. 3.4 Program Status Word (PSW) This word consists of 6 types of flags which are set/reset according to instruction execution results. Three of these flags (Z, HC and CY) can be tested by an instruction. PSW contents are automatically saved to the stack when an interrupt (external, internal or SOFTI instruction) is generated, and restored by the RETI instruction. RESET input resets all bits to (0). Figure 3-2. PSW Configuration 7 0 6 Z 5 SK 4 HC 3 L1 2 L0 1 0 0 CY (1) Z (Zero) When the operation result is zero, this flag is set (1). In all other cases, it is reset (0). (2) SK (Skip) When the skip condition is satisfied, this flag is set (1). If the condition is not satisfied, it is reset (0). (3) HC (Half carry) If an operation generates a carry out of bit 3 or a borrow into bit 3, this flag is set (1). In all other cases, it is reset (0). (4) L1 When MVI A, byte instructions are stacked, this flag is set (1). In all other cases, it is reset (0). (5) L0 When MVI L, byte ; LXI H, word instructions are stacked, this flag is set (1). In all other cases, it is reset (0). (6) CY (Carry) When an operation generates a carry out of or a borrow into bit 7 or 15, this flag is set (1). In all other cases, it is reset (0). When one of 35 types of ALU instructions, a rotation instruction or a carry manipulation instruction is executed, various flags are affected as shown in Table 3-2. 42 CHAPTER 3 INTERNAL BLOCK FUNCTIONS Table 3-2. Flag Operations Operation reg, memory ADD ADC SUB SBB DADD DADC DSUB DSBB EADD ESUB ANA ORA XRA DAN DOR DXR ADDNC SUBNB GTA LTA DADDNC DSUBNB DGT DLT ONA OFFA DON DOFF NEA EQA DNE DEQ INR DCR DAA RLR RLL SLR SLL DRLR DRLL DSLR DSLL SLRC SLLC STC CLC MVI A, byte MVI L, byte LXI H, word BIT SK SKN SKIT SKNIT RETS All other instructions ADDW ADCW SUBW SBBW ADDX ADCX SUBX SBBX ADI ACI SUI SBI immediate skip D6 Z ¤ D5 SK 0 D4 HC ¤ D3 L1 0 D2 L0 0 D0 CY ¤ ANAW ORAW XRAW ANAX ORAX XRAX ANI ORI XRI ANIW ORIW ¤ 0 q 0 0 q ADDNCW SUBNBW GTAW LTAW ADDNCX SUBNBX GTAX LTAX ADINC SUINB GTI LTI ¤ GTIW LTIW ¤ ¤ 0 0 ¤ ONAW OFFAW ONAX OFFAX ONI OFFI ONIW OFFIW ¤ ¤ q 0 0 q NEAW EQAW NEAX EQAX NEI EQI NEIW EQIW ¤ ¤ ¤ 0 0 ¤ INRW DCRW ¤ ¤ q q q q q q q ¤ 0 0 ¤ 0 0 0 0 ¤ ¤ ¤ q q q q q q q 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 q ¤ ¤ ¤ 1 0 q q q q q 1 0 q q 0 0 0 0 q q ¤ ... Affected (set or reset) 1 ... Set 0 ... Reset q ... Not affected 43 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 3.5 Memory 3.5.1 µPD78C18/78C17/78C14/78C14A/78C12A/78C11A/78C10A memory configuration The µPD78C18/78C17/78C14/78C14A/78C12A/78C11A/78C10A can address a maximum of 64K bytes of memory. The memory maps are shown in Figures 3-3 to 3-8. The external memory area and the on-chip RAM area can be freely used as program memory and data memory. Since the access time for on-chip memory and external memory are the same, processing can be executed at high speeds. (1) Interrupt start addresses The interrupt start addresses are all fixed as follows: NMI .......................0004H INTT0/INTT1 ......... 0008H INT1/INT2 ............. 0010H INTE0/INTE1 ......... 0018H INTEIN/INTAD ...... 0020H INTSR/INTST ........ 0028H SOFTI .................... 0060H (2) Call address table The call address of a 1-byte call instruction (CALT) can be stored in the 64-byte area (for 32 call addresses) from address 0080H to address 00BFH. (3) Specific memory area The reset start address, interrupt start addresses and the call table are allocated to addresses 0000H to 00BFH, and this area takes account of these in use. Addresses 0800H to 0FFFH are directly addressable by a 2-byte call instruction (CALF). On-chip mask ROM allocation is shown below. • • • • • • µPD78C18 µPD78C17 µPD78C12A µPD78C11A µPD78C10A : Addresses 0000H to 7FFFH : No mask ROM incorporated : Addresses 0000H to 1FFFH : Addresses 0000H to 0FFFH : No mask ROM incorporated µPD78C14/78C14A : Addresses 0000H to 3FFFH With the µPD78C17/78C10A, a specific area can be set up externally. 44 CHAPTER 3 INTERNAL BLOCK FUNCTIONS (4) On-chip data memory area 1K byte RAM is incorporated in addresses FC00H to FFFFH in the µPD78C18, and 256-byte RAM in addresses FF00H to FFFFH in the µPD78C14A/78C12A/78C11A/78C10A. The RAM contents are retained in standby operation Caution When internal RAM is used, the RAE bit of the MM register must be set to 1. (5) External memory area The possible area for external memory expansion is shown below. This area can be expanded in steps by setting the memory mapping register. • • • • µPD78C18 µPD78C12A µPD78C11A : 31K bytes (addresses 8000H to FBFFH) : 56K bytes (addresses 2000H to FEFFH) : 60K bytes (addresses 1000H to FEFFH) µPD78C14, 78C14A : 48K bytes (addresses 4000H to FEFFH) External memory can be expanded in steps in a 63K-byte area (addresses 0000H to FBFFH) for the µPD78C17, and in a 64K-byte area (addresses 0000H to FEFFH) for the µPD78C10A. This setting is performed by the MODE0 and MODE1. The external memory is accessed using PD7 to PD0 (multiplexed address/data bus), PF7 to PF0 (address bus) and the RD, WR and ALE signals. Both programs and data can be stored in the external memory. (6) Working register area A 256-byte working register area can be set in any memory locations (specified by the V register). 45 CHAPTER 3 INTERNAL BLOCK FUNCTIOS Figure 3-3. Memory Map (µPD78C18) 0000H 0000H RESET On-chip ROM 32768 × 8-bit 0004H NMI 0008H 7FFFH 8000H INTT0/INTT1 0010H INT1/INT2 External memory 31744 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FBFFH FC00H On-chip RAM 1024 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area Note Can only be used when the RAE bit of the MM register is 1. 46 CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3-4. Memory Map (µPD78C17) 0000H 0000H RESET 0004H NMI 0008H INTT0/INTT1 0010H INT1/INT2 External memory 64512 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FBFFH FC00H On-chip RAM 1024 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH LOW ADRS HIGH ADRS t = 31 Note Can only be used when the RAE bit of the MM register is 1. 47 CHAPTER 3 INTERNAL BLOCK FUNCTIOS Figure 3-5. Memory Map (µPD78C14/78C14A) 0000H 0000H RESET On-chip ROM 16384 × 8-bit 0004H NMI 0008H 3FFFH 4000H INTT0/INTT1 0010H INT1/INT2 External memory 48896 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H On-chip RAM 256 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area Note Can only be used when the RAE bit of the MM register is 1. 48 CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3-6. Memory Map (µPD78C12A) 0000H 0000H RESET On-chip ROM 8192 × 8-bit 0004H NMI 0008H 1FFFH 2000H INTT0/INTT1 0010H INT1/INT2 External memory 57088 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H On-chip RAM 256 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area 1FFFH Note Can only be used when the RAE bit of the MM register is 1. 49 CHAPTER 3 INTERNAL BLOCK FUNCTIOS Figure 3-7. Memory Map (µPD78C11A) 0000H 0000H RESET On-chip ROM 4096 × 8-bit 0004H NMI 0008H 0FFFH 1000H INTT0/INTT1 0010H INT1/INT2 External memory 61184 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H On-chip RAM 256 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area Note Can only be used when the RAE bit of the MM register is 1. 50 CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3-8. Memory Map (µPD78C10A) 0000H 00BFH 00C0H 0000H RESET 0004H NMI 0008H INTT0/INTT1 External memory 65280 × 8-bit 0010H INT1/INT2 0018H INTE0/INTE1 0020H FEFFH FF00H On-chip RAM 256 × 8-bit FFFFH Note INTEIN/INTAD Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH LOW ADRS HIGH ADRS t = 31 Note Can only be used when the RAE bit of the MM register is 1. 51 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 3.5.2 µPD78CP18/78CP14 memory configuration The µPD78CP18 can operate in any of 4 modes and the µPD78CP14 in any of 3 modes according to the MM register mode specification. • • • • µPD78C18 modeNote µPD78C14 mode µPD78C12A mode µPD78C11A mode Note Only the µPD78CP18 can operate in this mode. In addition, the on-chip ROM address range can be specified to allow efficient mapping of external memory (excluding PROM). The vector area and call table area are the same in all modes. Setting the hardware/software STOP mode or HALT mode allows on-chip RAM data to be retained with a low consumption current. The memory map for each mode is shown in Figures 3-9 to 3-12. 52 CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3-9. Memory Map (µPD78C18 Mode) 0000H 0000H RESET On-chip EPROM 32768 × 8-bit 0004H NMI 0008H 7FFFH 8000H INTT0/INTT1 0010H INT1/INT2 External memory 31744 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FBFFH FC00H On-chip RAM 1024 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area 7FFFH Note Can only be used when the RAE bit of the MM register is 1. 53 CHAPTER 3 INTERNAL BLOCK FUNCTIOS Figure 3-10. Memory Map (µPD78C14 Mode) 0000H 0000H RESET On-chip EPROM 16384 × 8-bit 0004H NMI 0008H 3FFFH 4000H INTT0/INTT1 0010H INT1/INT2 External memory 48896 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H On-chip RAM 256 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area 3FFFH Note Can only be used when the RAE bit of the MM register is 1. 54 CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3-11. Memory Map (µPD78C12A Mode) 0000H 0000H RESET On-chip EPROM 8192 × 8-bit 0004H NMI 0008H 1FFFH 2000H INTT0/INTT1 0010H INT1/INT2 External memory 57088 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H On-chip RAM 256 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area 1FFFH Note Can only be used when the RAE bit of the MM register is 1. 55 CHAPTER 3 INTERNAL BLOCK FUNCTIOS Figure 3-12. Memory Map (µPD78C11A Mode) 0000H 0000H RESET On-chip EPROM 4096 × 8-bit 0004H NMI 0008H 0FFFH 1000H INTT0/INTT1 0010H INT1/INT2 External memory 61184 × 8-bit 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H On-chip RAM 256 × 8-bit FFFFH Note Standby area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 User's area 0FFFH Note Can only be used when the RAE bit of the MM register is 1. 56 CHAPTER 3 INTERNAL BLOCK FUNCTIONS 3.6 Timers The timer system comprises two 8-bit interval timers. The two interval timers can also be cascaded to operate as a 16-bit interval timer The elapse of the interval time can be identified by the generation of a timer interrupt. In addition, a square wave with the interval time as a half-cycle is obtained from the TO pin (see CHAPTER 5 TIMER FUNCTIONS for details). 3.7 Timer/Event Counter This is a 16-bit timer/event counter which performs the following operations according to the operating mode set by the program (see CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS for details). • Interval timer function • Event counter function • Frequency measurement • Pulse width measurement • Programmable square-wave output 3.8 Serial Interface This interface is used to perform serial data transfers in a multi-processor configuration or with various terminals, and operates in asynchronous mode, synchronous mode, and I/O interface mode (see CHAPTER 7 SERIAL INTERFACE FUNCTIONS for details). 3.9 Analog/Digital Converter This consists of an 8-bit A/D converter with 8 analog inputs which uses the high-precision successive approximation method, and 4 conversion result registers (CR0 to CR3) which hold the conversion results. With two analog input selection methods, scan mode and select mode, and 4 registers (CR0 to CR3) to hold the conversion results, software overhead is minimized (see CHAPTER 8 ANALOG/DIGITAL CONVERTER FUNCTIONS for details). 3.10 Interrupt Control There are 3 kinds of external interrupt request and 8 kinds of internal interrupt request, controlled according to the status and priority of the interrupt mask register. The 11 kinds of interrupt requests are divided into 6 groups, with 6 different priorities and 6 different interrupt addresses (see CHAPTER 9 INTERRUPT CONTROL FUNCTIONS for details). 57 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 3.11 Zero-Cross Detector The INT1 pin and INT2/TI (PC3 dual-function) pin can be made to execute zero-cross detection operations by setting the zero-cross mode register. The zero-cross detector has a self-bias type high-gain amplifier. It biases the input to the switching point and generates digital displacement in response to a small input displacement. Figure 3-13. Zero-Cross Detector µ PD78C18 External capacitor AC input signal (1 to 1.8 VPP) INT1 INT2/TI 1 µF To internal circuitry Self bias circuit enable The zero-cross detector detects a negative-to-positive or positive-to-negative transition of the AC signal input through an external capacitor and generates a digital pulse which changes from 0 to 1 or 1 to 0 at each transition point. Figure 3-14. Zero-Cross Detection Signal AC input signal Zero-cross detection signal A digital pulse generated in the zero-cross detector of the INT1 pin is set to the interrupt control circuit. The INTF1 interrupt request flag is set at the zero-cross point from negative to positive of the AC signal (rising edge), and if INT1 interrupt is enabled, interrupt servicing is started. A digital pulse generated in the INT2/TI pin zero-cross detector is sent to the interrupt control circuit and interrupt servicing can be started at the zero-cross point from positive to negative of the AC signal as with the INT1 pin, and can also be used as a timer input clock. 58 CHAPTER 3 INTERNAL BLOCK FUNCTIONS The zero-cross detection function can use the 50/60 Hz power signal as the basis for system timing. Further, a special characteristic of the zero-cross function is that it can be used for servicing of interrupts at the zero-voltage point. This makes it possible to control a device which uses voltage phase sensing such as a TRIAC or SCR, and allows the µPD78C18 to be used for applications such as shaft speed and angle measurement. When a capacitor is not connected to the INT1 and INT2 pins, they function as digital input pins. The format of the zero-cross mode register (ZCM), which controls self-bias for zero-cross detection of the INT1 and INT2/TI pins, is shown in Figure 3-15. Figure 3-15. Zero-Cross Mode Register Format 7 ZCM – 6 – 5 – 4 – 3 – 2 ZC2 1 ZC1 0 – INT1 pin 0 1 No self-bias generation Self-bias generation INT2/TI pin 0 1 No self-bias generation Self-bias generation When the ZC1 and ZC2 bits of the zero-cross mode register are set to to "0", a self-bias for zero-cross detection of each pin is not generated and each pin responds as a normal digital input. When the ZC1 and ZC2 bits are set to "1", a self-bias is generated and an AC input signal zero-cross can be detected by connecting a capacitor to each pin. Each pin with ZC1 and ZC2 bits set to "1" can be directly driven without the use of an external capacitor. In this case, each pin responds as a digital input. However, an input load current is necessary and an external circuit output driver must be considered. Thus, when no zero-cross detection is executed and each pin is used simply as an interrupt input or timer input, the ZC1 and ZC2 bits of the zero-cross mode register should be set to "0". RESET input sets both the ZC1 and ZC2 bit to "1" and a self-bias is generated. When the PC3 (INT2/TI) pins is in port mode, no self-bias is generated regardless of the ZCM register setting. Cautions 1. Unlike other CMOS circuits, a supply current is always present in the zero-cross detector because of its operation points. This also applies in the standby modes (HALT and software/ hardware STOP modes). Thus, when the zero-cross detector is operated (with self-bias generation: ZCx=1), slightly more current flows than without zero-cross detector operation, and its effect is greater in the software STOP mode. 2. When the PC3 pin is used for zero-cross detection in the µPD78C18/78C14A/78C12A/78C11A, no pull-up resistor should be incorporated. In the hardware STOP mode, self-bias generation is stopped automatically. 59 [MEMO] 60 CHAPTER 4 PORT FUNCTIONS 4.1 Port A (PA7 to PA0) This is an 8-bit input/output port which has input/output buffer and output latch functions (see Figure 4-1). Port A can be set as to input or output bit-wise using the mode A register (MA). When set to input, the pins become high-impedance. In the µPD78C18/78C14A/78C12A/78C11A, pull-up resistors can be incorporated bit-wise. Figure 4-1. Port A WRM MAn latch WRP Internal bus Output latch Output buffer PAn RD0 RD1 When the corresponding bit of the mode A register is set (1), a port A pin functions as an input port pin, and when reset (0), as an output port pin (see Figure 4-2). When RESET is input or the hardware STOP mode is set, all bits of the mode A register are set and port A functions as an input port (high-impedance). Figure 4-2. Mode A Register Format 7 6 5 4 3 MA3 2 MA2 1 0 MA MA7 MA6 MA5 MA4 MA1 MA0 0 1 PAn = Output port PAn = Input port (n = 0 – 7) 7 PA PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 0 PA0 61 CHAPTER 4 PORT FUNCTIONS (1) When specified as output port (MAn=0) The output latch is effective, enabling data exchange by a transfer instruction between the output latch and the accumulator. Direct bit setting/resetting of output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Once data is written to the output latch, the data is held until a port A manipulation instruction is executed or the data is reset. Figure 4-3. Port A Specified as Output Port WRP Internal bus Output latch RD0 PAn (2) When specified as input port (MAn=1) PA line contents can be loaded into an accumulator by a transfer instruction. They can also be directly tested bit-wise by an arithmetic or logical operation instruction without the use of an accumulator. In this case, too, writing to the output latch is possible and data transferred from the accumulator by a transfer instruction is stored in the entire output latch without regard to the input/output setting of the port. However, the output latch contents for bits specified as input port bits cannot be loaded into the accumulator, and since the output buffer is high-impedance, the contents are not output to an external pin (operating as an input pin). Thus data stored in the output latch can be output to the external pin and loaded into the accumulator when the bit is switched to output port mode. Since input data is not latched, stable input is necessary when executing a data transfer instruction or a bit test, etc. Figure 4-4. Port A Specified as Input Port WRP Output latch PAn Internal bus RD1 62 CHAPTER 4 PORT FUNCTIONS (3) Port A manipulation Actual execution of an instruction which manipulates port A is performed as an 8-bit unit. If a port A read instruction (MOV A, PA) is executed, the input line contents of the port specified for input and the output latch contents of the port specified for output are loaded into an accumulator. When a port A write instruction (MOV PA, A) is executed, data is written to the output latch of both ports specified for input and output, but the output latch contents of a port specified as input are not output to an external pin. Here, the data input/output manipulation is described when the high-order 4 bits (PA7 to PA4) of port A are used as an active-low output port, and the low-order 4 bits (PA3 to PA0) are used as an input port. Since the initial status of PA7 to PA0 after a reset is the input port status (high-impedance), the PA7 to PA4 output port pins used as active-low have to be raised to the high level with a pull-up resistor to make them inactive. Also, since the output latch contents are undefined after a reset, the active level (low) may be output at the point of specification as an output port. Therefore, all ones should be written to the PA7 to PA4 output latches before specification as an output port. VDD µ PD78C18 PA7 ~ Active-low output PA4 PA3 ~ PA0 63 CHAPTER 4 PORT FUNCTIONS PA Input/Output 76543210 RESET ; MA=0FFH IIIIIIII Note PA Output Latch 76543210 ×××××××× PA Pin 76543210 1111×××× By pull-up resistor MVI PA, 0F0H … 11110000 1111×××× By pull-up resistor MVI A, 0FH MOV MA, A;MA=0FH ……… OOOO I I I I Note 11110000 1111×××× MVI PA, 0EFH … 11101111 1110×××× MOV A, PA;A=11101010 Input data Output latch contents 11101111 11101010 Pin input data Note I: O: Input Output 64 CHAPTER 4 PORT FUNCTIONS 4.2 Port B (PB7 to PB0) Like port A, port B is an 8-bit input/output port with input/output buffer and output latch functions (see Figure 4-1). Port B can be set as an input or output port bit wise using the mode B register (MB). When set to input, the pins become high-impedance. When the corresponding bit of the mode B register is set (1), a port B pin functions as an input port pin, and when reset (0), as an output port pin (see Figure 4-5). When RESET is input or the hardware STOP mode is set all bits of the mode B register are set and port B functions as an input port (high-impedance). In the µPD78C18/78C14A/78C12A/78C11A, pull-up resistors can be incorporated bit-wise. Figure 4-5. Mode B Register Format 7 6 5 4 3 MB3 2 MB2 1 0 MB MB7 MB6 MB5 MB4 MB1 MB0 0 1 PBn = Output port PBn = Input port (n = 0 – 7) 7 PB PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 As with port A, direct bit setting/resetting of port B output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. 65 CHAPTER 4 PORT FUNCTIONS 4.3 Port C (PC7 to PC0) Port C (PC7 to PC0) is an 8-bit special input/output port which functions in either port mode or control signal input/ output mode according to the setting of the mode control C (MCC) register. When the corresponding bit of mode control C register is set (1), the port C is set to control mode, and if reset (0), set to port mode (see Figure 4-6). When RESET is input or the hardware STOP mode is set, all bits of the mode control C register are reset and all bits of port C are set to port mode. In the µPD78C18/78C14A/78C12A/78C11A, pull-up resistors can be incorporated bit-wise. Figure 4-6. Mode Control C Register Format 7 6 5 4 3 2 1 0 MCC MCC7 MCC6 MCC5 MCC4 MCC3 MCC2 MCC1 MCC0 0 1 PC0 = Port mode PC0 = TXD output 0 1 PC1 = Port mode PC1 = RXD input 0 1 PC2 = Port mode PC2 = SCK input/output 0 1 PC3 = Port mode PC3 = INT2/TI input 0 1 PC4 = Port mode PC4 = TO output 0 1 PC5 = Port mode PC5 = CI input 0 1 PC6 = Port mode PC6 = CO0 output 0 1 PC7 = Port mode PC7 = CO1 output 66 CHAPTER 4 PORT FUNCTIONS (1) Port mode Like port A, port C is an 8-bit input/output port with input/output buffer and output latch functions (see Figure 4-1). When port C is set to port mode by the mode control C register, it can be set bit-wise as an input or output port by means of the mode C register (MC). When set to input port, the pins become high-impedance. When the corresponding bit of the mode C register is set (1), a port C pin functions as an input port pin, and when reset (0), as an output port pin (see Figure 4-7). When RESET is input or the hardware STOP mode is set all bits of the mode C register are set and port C functions as an input port (high-impedance). Figure 4-7. Mode C Register Format 7 6 5 4 3 MC3 2 MC2 1 0 MC MC7 MC6 MC5 MC4 MC1 MC0 0 1 PCn = Output port PCn = Input port (n = 0 – 7) 7 PC PC7 6 PC6 5 PC5 4 PC4 3 PC3 2 PC2 1 PC1 0 PC0 As with port A, direct bit setting/resetting of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to /from an accumulator is also possible. (2) Control signal input/output mode Port C input/output pins (PC7 to PC0) can be used bit-wise as control signal inputs or outputs by setting (1) the relevant bit of the mode control C register, regardless of the mode C register setting. When the PCn pin is used for a control signal (MCCn=1), the control signal status is ascertained by execution of a port C read instruction or test instruction. (a) When PCn is control signal output When MCn=1, the status of the PCn pin control signal can be read into an accumulator or tested by executing a port C read instruction or test instruction. When MCn=0, the internal control signal status can be read into an accumulator or tested by executing a port C read instruction or test instruction (see Figure 4-8). 67 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Port C Specified as Control Signal Output Control signal MCn = 0 RDP Internal bus MCn = 1 PCn (Control signal output) (b) When PCn is control signal input When MCn=1, the status of the PCn pin control signal can be read into an accumulator by a port C read instruction or tested by a port C test instruction. Figure 4-9. Port C Specified as Control Signal Input Control signal PCn (Control signal output) RDP Internal bus MCn = 1 Cautions 1. When MCC3 is rewritten, INTF2 may be set. After rewriting, INTF2 should be reset by the SKIT instruction. 2. When TO (PC4), CO0 (PC6) and CO1 (PC7) are used as active-low signal outputs, the following manipulation is required. Since port C is entirely set as an input port (high-impedance) in its initial status after a reset, TO, CO0 and CO1 used as active-low pin have to be raised to the high level with a pull-up resistor to make them inactive. Also, before switching to the control signal output mode by means of the mode control C register, "1" must be written to the port C output latch to make the port C output level and output latch contents equal. Port C is then switched to the control signal output mode by means of the mode control C register. 68 CHAPTER 4 PORT FUNCTIONS VDD µ PD78C18 TO (PC4) CO0 (PC6) CO1 (PC7) Active-low output MVI MVI PC, 0FFH ; PORT C OUTPUT LATCH=1 A, 0FFH ; ; PORT C CONTROL MODE MOV MCC, A 69 CHAPTER 4 PORT FUNCTIONS 4.4 Port D (PD7 to PD0) µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14 Port D is an 8-bit special input/output port; in addition to functioning as a general-purpose input/output port (port mode), this port also functions as a multiplexed address/data bus. Port/expansion mode can be specified for port D as a byte unit by means of the memory mapping register (see Table 4-1). Table 4-1. Operation of PD7 to PD0 (µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14) MM2, MM1=0, 0 PD7 to PD0 Port mode MM2, MM1≠0, 0 Expansion mode Port D is set to port mode when the MM2 and MM1 bits of the memory mapping register are reset (0), and to expansion mode in all other cases (see 11.1.1 Memory mapping register (MM)). (1) Port mode Port D is an 8-bit input/output port which has input/output buffer and output latch functions in the same way as port A, except that input or output port setting is performed as a byte (8-bit) unit. Port D can be set as input or output as a byte unit by the MM0 bit of the memory mapping register: It functions as an input port when the MM0 bit is reset (0), and as an output port when the MM0 bit is set (1). Except for having input/output specified as a byte unit, port D operation is the same as for port A; Direct bit setting/resetting of output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator, and data transfer to/from an accumulator is also possible. (2) Expansion mode External memory expansion up to 256 bytes is possible using the port D input/output pins (PD7 to PD0) as a multiplexed address/data bus. Also, when a large external memory expansion is made, this is done by using PF7 to PF0 as the address bus (see CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS for details). µPD78C17/78C10A The port operates only as a multiplexed address/data bus (AD7 to AD0), and has no port function Cautions 1. When the port D input/output pins (PD7 to PD0) are functioning as an address/data bus (AD7 to AD0), the internal address bus status is output in synchronization with ALE in all machine cycles. 2. Emulation cannot be performed by an emulator for a program which varies the port D operating mode dynamically. Therefore, once the mode has been set, it should not be changed to a different mode. 70 CHAPTER 4 PORT FUNCTIONS 4.5 Port F (PF7 to PF0) µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14 Port F is an 8-bit special input/output port; in addition to functioning as a general-purpose input/output port (port mode), this port also functions as an address bus. Port/expansion mode can be specified in steps for PF7 to PF0 by means of the memory mapping register (see 11.1.1 Memory mapping register (MM)). (1) Port mode Like port A, port F is an 8-bit input/output port with input/output buffer and output latch functions (see Figure 4-1. Port A). Port F can be set bit-wise as an input or output port by means of the mode F register (MF). When set to input, the pins become high-impedance. When the corresponding bit of the mode F register is set (1), a port F pin functions as an input port pin, and when reset (0), as an output port pin. When RESET is input or the hardware STOP mode is set all bits of the mode F register are set. Figure 4-10. Mode F Register Format 7 MF MF7 6 MF6 5 MF5 4 MF4 3 MF3 2 MF2 1 MF1 0 MF0 0 1 PFn = Output port PFn = Input port (n = 0 – 7) 7 PF PF7 6 PF6 5 PF5 4 PF4 3 PF3 2 PF2 1 PF1 0 PF0 As with port A, direct bit setting/resetting and bit testing of port F output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. 71 CHAPTER 4 PORT FUNCTIONS (2) Expansion mode Port F input/output pins (PF7 to PF0) can be used as address outputs corresponding to the size of external expansion memory, as shown in Table 4-2. This setting is performed by means of the memory mapping register. Pins not used as address outputs are set to port mode. Table 4-2. Operation of PF7 to PF0 (µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14) PF7 Port Port Port AB15 PF6 Port Port Port AB14 PF5 Port Port AB13 AB13 PF4 Port Port AB12 AB12 PF3 Port AB11 AB11 AB11 PF2 Port AB10 AB10 AB10 PF1 Port AB9 AB9 AB9 PF0 Port AB8 AB8 AB8 External Address Space Up to 256 bytes Up to 4K bytes Up to 16K bytes Up to 31K/48K/56K/60K bytesNote Note 31K (µPD78C18), 48K (µPD78C14/78C14A), 56K (µPD78C12A), 60K (µPD78C11A). The operation of the µPD78CP18 and 78CP14 differ depending on the setting of bits MM5 to MM7 of the memory mapping register. µPD78C17/78C10A These pins function as address outputs corresponding to the size of externally installed memory according to the MODE0 and MODE1 pin settings. Pins which are not used as address outputs can be used as general-purpose input/output port pins which have the same port functions as port A, with input/output setting performed by the mode F register. Table 4-3. Operation of PF7 to PF0 (µPD78C17/78C10A) MODE1 0 0 1 1 MODE0 0 1 0 1 PF7 Port Port PF6 Port Port PF5 Port PF4 Port PF3 PF2 PF1 AB9 AB9 PF0 AB8 AB8 External Address Space 4K bytes 16K bytes 63K/64K bytesNote AB11 AB10 AB13 AB12 AB11 AB10 Setting prohibited AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 Note 63K (µPD78C17), 64K (µPD78C10A) Cautions 1. Pins not used as address bus pins output the internal address bus status in all machine cycles. When the address changes, undefined data is output. 2. Emulation cannot be performed by an emulator for a program which varies the port F operating mode dynamically. Therefore, once the mode has been set, it should not be changed to a different mode. When the 63K/64K-byte mode is used with the µPD78C17/78C10A, instructions which output data to port D or port F should not be executed; if such an instruction is executed, the WR signal will be output. 72 CHAPTER 4 PORT FUNCTIONS 4.6 Operation of Arithmetic and Logical Operation Instruction Involving a Port and Immediate Data With the following instructions which perform arithmetic and logical operations involving a port and immediate data, the operation differs depending on the input/output setting of the port. Table 4-4. Operation of Arithmetic/Logical Operation Instructions Involving a Port Mnemonic ACI, ADI, ADINC SBI, SUI, SUINB ANI, ORI, XRI GTI, LTI EQI, NEI OFFI, ONI Logical operation Comparison Match detection Test Operand sr2, byte Instruction Arithmetic operation Instruction operations are as follows: (1) The port status is input. Output mode pin: Input mode pin: Output latch status is input. Pin external status is input. (2) The arithmetic/logical operation is performed on the input data and immediate data. (3) The entire 8-bit operation result data is transferred to the port output latch. For input mode pins, the result of the operation with the pin external status is transferred to the output latch. Caution (3) applies only to the arithmetic operations and logical operations in Table 4-4. Port output latch initialization should be performed by a transfer instruction (MOV, MVI). 73 [MEMO] 74 CHAPTER 5 TIMER FUNCTIONS 5.1 Timer Configuration The timer system in the µPD78C18 consists of two 8-bit interval timers (TIMER0 and TIMER1) and a timer F/F. Timer operation and square-wave output is controlled by the timer mode register (TMM). Each interval timer (TIMER0 and TIMER1) consists of an 8-bit upcounter, an 8-bit comparator, and 8-bit timer REG0/ 1 (TM0 and TM1). (1) Upcounter This counts up using the input clock specified by the timer mode register (TMM). (2) Timer REG0, 1 (TM0, TM1) These are 8-bit registers used to set the interval time. (3) Comparator The comparator compares the upcounter contents with the timer REG0/1 contents, and if they match, clears the upcounter and generates an internal interrupt (INTT0/INTT1). (4) Timer F/F This F/F is inverted by a TIMER0/TIMER1 match signal or the internal clock (φ3). The output of this timer F/ F can be output to the TO pin (dual function as PC4). The timer F/F output can be used irrespective of the PC4 pin mode status as the basic timer of the timer/event counter according to the specification of the timer/ event counter mode register or as the serial clock (SCK) according to the serial mode register specification. The timer is also used for generation of the oscillator stabilization time when standby mode (STOP) is released (see 10.1 Standby Functions for details). 75 CHAPTER 5 TIMER FUNCTIONS Figure 5-1. Timer Block Diagram φ3 Timer F/F PC4/TO TIMER0 PC3/TI clear φ 12 φ 384 φ 12 TIMER1 To timer/event counter To serial interface clear Upcounter Upcounter φ 384 Comparator Comparator Timer mode register Timer REG0 (TM0) INTT0 Timer REG1 (TM1) INTT1 Internal bus Remark φ3 = fXX × 1/3 φ12 = fXX × 1/12 φ384 = fXX × 1/384 fXX : Oscillator frequency (MHz) 76 CHAPTER 5 TIMER FUNCTIONS 5.2 Timer Mode Register (TMM) This is an 8-bit register which specifies the operating mode of the two interval timers (TIMER0 and TIMER1) and the timer F/F. Its configuration is shown in Figure 5-2. (1) TF0 & TF1 (bits 0 & 1) These bits perform timer F/F reset specification and input clock specification. The internal clock (φ3) is obtained by dividing the oscillator frequency by 3. (2) CK00 & CK01 (bits 2 & 3) These bits specify the TIMER0 input clock. Internal clocks φ12 and φ384 are obtained by dividing the oscillator frequency by 12 and 384 respectively. (3) TS0 (bit 4) TS0 controls the operation of the TIMER0 upcounter. When TS0 is "1", the upcounter is cleared to 00H and the count-up is stopped; when changed from "1" to "0", the upcounter starts counting up from 00H. However, if, after this bit is set to "0" and the count has begun, "0" is written to the bit again, the upcounter is not cleared and the count continues. (4) CK10 & CK11 (bits 5 & 6) These bits specify the TIMER1 input clock. (5) TS1 (bit 7) TS1 controls the operation of the TIMER1 upcounter and operates in the same way as the TS0 bit. RESET input sets the timer mode register to FFH, clears and stops the upcounter of both TIMER0 and TIMER1, and resets the timer F/F. 77 CHAPTER 5 TIMER FUNCTIONS Figure 5-2. Timer Mode Register (TMM) Format 7 TMM TS1 6 5 4 TS0 3 2 1 TF1 0 TF0 Timer F/F input & operating mode specification 0 0 1 1 0 1 0 1 TIMER0 comparator match signal TIMER1 comparator match signal Internal clock (φ 3 ) Timer F/F reset CK11 CK10 CK01 CK00 TIMER0 input clock specification 0 0 1 1 0 1 0 1 Internal clock (φ 12) Internal clock (φ 384 ) External pulse (TI pin falling edge) input Disable TIMER0 operation specification 0 1 Count-up Reset TIMER1 input clock specification 0 0 1 1 0 1 0 1 Internal clock (φ 12) Internal clock (φ 384) External pulse (TI pin falling edge) input TIMER0 comparator match signal TIMER1 operation specification 0 1 Count-up Reset 78 CHAPTER 5 TIMER FUNCTIONS 5.3 Timer Operations Interval timer operation is performed for the two timers using the following input clocks according to the specification of the timer mode register (TMM). (1) Internal clock (φ12) When the internal clock (φ12) is specified as the upcounter input clock, the timer operates as an interval timer with an interval from 1 µs to 256 µs (at 12 MHz operation) with a 1 resolution of 1 µs. (2) Internal clock (φ384) When the internal clock (φ384) is specified as the upcounter input clock, an interval time from 32 µs to 8.192 ms can be selected (at 12 MHz operation) with a resolution of 32 µs. (3) External pulse (TI) When an external pulse (TI input) is specified as the upcounter input clock, the timer operates as an interval timer of any desired resolution. Also, when the upcounter counts external pulses up to the value set in timer REG0/1 (TM0/TM1), it can also be used as an event counter which generates internal timer interrupts (INTT0/ INTT1). However, it is not possible to read the count data (the upcounter contents) during the count. To prevent errors due to noise signals in the TI pin, sampling is performed by a sampling pulse with a 1-state (250 ns: 12 MHz) cycle. Thus an input signal of less than 1 state is eliminated, and a high level or low level duration of 2 states or more is necessary for a signal to be acknowledged as a TI pin input signal. The upcounter count operation is performed by falling edge input on the TI pin. (4) TIMER0 output (can only be specified for TIMER1) This can only be specified for TIMER1. The timer operates as a 16-bit interval timer which counts TIMER0 match signals as the TIMER1 upcounter input. An interval from 1 µs to 65.536 ms or from 32 µs to 2.1 s can be selected (at 12 MHz operation). Since both TIMER0 and TIMER1 perform the same operation, TIMER0 operation is described here. Interval timer operation is started by setting the count value in timer REG0 and writing the necessary data to the timer mode register. The upcounter counts up every input clock cycle, while the comparator constantly compares the contents of the counting upcounter and the contents of timer REG0, and generates an internal interrupt (INTT0) if they match. When a match occurs, the upcounter is cleared and the count-up starts again from 00H. Thus TIMER0 functions as an interval timer which generates repeated interrupt requests using the value set in timer REG0 as the interval. When timer REG0 is set, an interrupt is generated on the 256th count. Cautions 1. When data is written to timer REG0, output of the comparator match signal is disabled, and therefore INTT0 is not generated. 2. After RESET input, the contents of TM0 are undefined. Ensure that TM0 initialization is performed by the program before the timer is started. When the TIMER0 match signal is selected as the timer F/F input and the upcounter contents and the timer REG0 contents match, the timer F/F contents are inverted and a square wave can be output from the TO pin. The pulse width of the square wave output to the TO pin is determined by the count value set in timer REG0. If 0 is set, the timer F/F contents are inverted and INTT0 is generated by the comparator match signal generated every 256 counts. The INTT0 timer interrupt is disabled by setting MKT0 (bit 1 of the interrupt mask register MKL). 79 [MEMO] 80 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS The µPD78C18 is equipped with a multi-function 16-bit timer/event counter which performs the following operations: • Interval timer function (see 6.3.1 Interval timer mode) • External event counter function (see 6.3.2 Event counter mode) • Frequency measurement (see 6.3.3 Frequency measurement mode) • Pulse width measurement (see 6.3.4 Pulse width measurement mode) • Programmable square-wave output (see 6.3.5 Programmable rectangular-wave output mode) 6.1 Timer/Event Counter Configuration The configuration of the timer/event counter is shown in Figure 6-1. Figure 6-1. Timer/Event Counter Block Diagram Internal bus Timer event counter capture REG (ECPT) φ 12 PC5/CI TO Input control Timer/event counter upcounter (ECNT) Clear control OV Output control PC6/CO0 PC7/CO1 Comparator Comparator CP1 Mode registers (ETMM, EOM) EIN Interrupt control Timer/event counter REG1 (ETM1) Timer/event counter REG0 (ETM0) CP0 INTE0 INTE1 INTE IN Internal bus Edge detection Remark φ12=fXX × 1 12 fXX: Oscillator frequency 81 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS (1) Timer/event counter upcounter (ECNT) ECNT is a 16-bit upcounter which counts input pulses, and is cleared by the clear control circuit. The OV flag is set if overflow occurs. The OV flag can be tested by the SKIT instruction (see 9.1 (6) Test flag register). (2) Timer/event counter capture register (ECPT) The ECPT register is a 16-bit buffer register which holds the ECNT contents. The timing for latching of the ECNT contents by the ECPT register is as follows according to the input to the ECNT. The ECPT register latches the ECNT contents on the fall of the CI input when the input to ECNT is (5) (i) Internal clock (φ12), or (ii) Internal clock while CI input is high, and on the fall of TO when the input to ECNT is (iii) CI input or (iv) CI input while TO output is high. Table 6-1. Timing for Latching in ECPT ETMM ET1 0 0 1 1 Notes 1. 2. ET0 0 1 0 1 Internal clock (φ12) φ12 while CI is high ECNT Input ECNT Latch Timing CI input falling edge TO falling edgeNote 2 CI inputNote 1 CI input while TO is highNote 1 Falling edge input The TO signal cannot be used when timer F/F input is used as internal clock φ3 (see Figure 5-1. Timer Block Diagram). (3) Timer/event counter REG0/1 (ETM0/ETM1) These are two 16-bit registers used to set the count value. Cautions 1. When 0 is set, a match signal (CP0/CP1) is generated from the comparator every count of 65536 (10000H). 2. When data is written to ETM0/ETM1, output of the comparator match outputs (CP0/CP1) are disabled, and therefore INTE0/INTE1 are not generated. (4) Comparator The comparator compares the contents of ECNT and ETM0/ETM1, and if a match is detected, outputs a coincidence signal (CP0/CP1) 82 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS (5) Input control circuit This circuit controls input to ECNT. The input to ECNT is determined as follows according to the specification of the timer/event counter mode register (ETMM). (i) (ii) Internal clock (φ12) Internal clock while CI input is high (iii) CI input (iv) CI input while TO output is high To prevent errors due to noise signals in the CI pin, sampling is performed by a sampling pulse with φ3 cycle (250 ns at 12 MHz operation). Thus an input signal of less than 1 state (250 ns at 12 MHz operation) is eliminated, and a high level or low level duration of 2 states (500 ns at 12 MHz operation) or more is necessary for a signal to be acknowledged as a CI pin input signal. Caution In CI pin edge detection, noise elimination is performed by the internal sampling clock (φ3) Table 6-2. ECNT Inputs ETMM ET1 0 0 1 1 ET0 0 1 0 1 Internal clock (φ12) φ12 while CI input is high ECNT Input CI inputNote CI input while TO is highNote Note Falling edge input (6) Clear control circuit This circuit clears ECNT as follows according to the specification of the timer/event counter mode register (ETMM). (i) (ii) Remains cleared Not cleared (iii) Match of ECNT and ETM1 (iv) CI input falling edge or TO falling edge In case (iv), the operation is as shown in Table 6-3 according to the ECNT input. 83 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS Table 6-3. ECNT Clearing ETMM ECNT Input EM1 0 0 1 EM0 0 1 0 ET1 × × 0 0 1 1 1 1 × ET0 × × 0 1 0 1 × Internal clock (φ12) No relation Stop after clearing Free running (not cleared) CI input falling edge ECNT Clearing φ12 while CI input is high CI input CI input while TO is high No relation Match of ECNT and ETM1 TO falling edgeNote Note The TO signal cannot be used when timer F/F input is used as internal clock φ3 (see Figure 5-1. Timer Block Diagram). When (iv) is specified in the clear mode, the clear operation is performed after the capture operation. (7) Interrupt control circuit This circuit controls timer/event counter interrupts. Interrupt sources are shown below; an interrupt request flag is set (1) by each source. (i) (ii) (iii) ECNT/ETM0 match signal ECNT/ETM1 match signal → INTE0 → INTE1 CI input falling edge or TO falling edge → INTEIN In case (iii), the setting is as shown in Table 6-4 according to the ECNT input as in case (ii) of item (6) Clear control circuit. Table 6-4. INTEIN Interrupt Request Flag Setting ETMM ET1 0 0 1 1 Notes ET0 0 1 0 1 Internal clock (φ12) φ12 while CI input is high ECNT Input Interrupt Request Flag Setting CI input falling edge TO falling edgeNote 2 CI inputNote 1 CI input while TO is highNote 1 1. Falling edge input 2. The TO signal cannot be used when timer F/F input is used as internal clock φ3 (see Figure 5-1. Timer Block Diagram). 84 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS (8) Output control circuit This circuit controls the two channel pulse outputs (CO0 & CO1), and operates as a timer/event counter enabling the pulse width and cycle to be varied. Pulse output is varied by the following signals. (i) (ii) (iii) Match of ECNT and ETM0 Match of ECNT and ETM1 CI input fallng edge (9) Mode registers These are two 8-bit registers which specify the operation of the timer/event counter and output control circuit (see 6.2 Mode Registers for details). 6.2 Mode Registers The timer/event counter has two mode registers: The timer/event counter mode register (ETMM) which specifies the operating mode, and the timer/event counter output mode register (EOM) which specifies the operation of the output control circuit. 6.2.1 Timer/event counter mode register (ETMM) This is an 8-bit register which controls the timer/event counter; its configuration is shown in Figure 6-2. (1) ET0 & ET1 (bits 0 & 1) These bits specify the timer/event counter upcounter (ECNT) input clock, latch timing, and INTEIN interrupt flag setting conditions. They may also be used for clear mode specification (when EM1=1 and EM0=0). The internal clock (φ12) is obtained by dividing the oscillator frequency by 12. (2) EM0, & EM1 (bits 2 & 3) These bits control the ECNT clear mode. When the value of the EM0 bit and EM1 bit is "00", ECNT is cleared to 0000H and counting up is not performed. When the EM0 and EM1 bits are set to any value other than "00", ECNT counts up using the input clock; ECNT is cleared by the conditions shown in Figure 6-2, after which the count starts again from 0000H. When EM0=0 and EM1=1, the conditions for clearing ECNT are as follows, according to the input clock specification. • • When ET1=0 and ET0=0, or ET1=0 and ET0=1, ECNT is cleared by the falling edge of the CI input (see 6.3.4 Pulse width measurement mode). When ET1=1 and ET0=0, or ET1=1 and ET0=1, ECNT is cleared by the falling edge of the TO input (see 6.3.3 Frequency measurement mode). (3) CO00 & CO01 (bits 4 & 5) These bits specify the timing for transfer to the output latch of the level of the LV0 level F/F shown in Figure 6-3. When CO00=0 and CO01=1, the LV0 level is transferred to the output latch in the event of either a match between ECNT and ETM0 or a fall of the CI input. When CO00=1 and CO01=1, the level is transferred in the event of a match between ECNT and ETM0 or a match between ECNT and ETM1. When the LD0 bit of the timer/event counter output mode register (EOM) is set (1), the LV0 level is inverted after transfer to the output latch. 85 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS (4) CO10 & CO11 (bits 6 & 7) In a similar way to the CO00 and CO01 bits, these bits specify the timing for transfer to the output latch of the level of the LV1 level F/F. When CO10=0 and CO11=1, or CO10=1 and CO11=1, the LV1 level is transferred to the output latch as with the CO00 and CO01 bits. When the LD1 bit of the timer/event counter output mode register (EOM) is set (1), the LV1 level is inverted after transfer to the output latch. The timer/event counter mode register is reset to 00H by RESET input and in the hardware STOP mode. 86 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS Figure 6-2. Timer/Event Counter Mode Register Format 7 6 5 4 3 2 EM0 1 ET1 0 ET0 ECNT input clock 0 0 1 1 0 1 0 1 Internal clock ( φ 12) ETMM CO11 CO10 CO01 CO00 EM1 φ 12 while CI input is high CI input CI input while TO is high ECNT clear mode 0 0 0 1 Stop after clearing Free running Cleared every full count Cleared on fall of CI input Cleared on fall of TO 1 1 (ET1=0) (ET1=1) 1 0 Cleared by match between ECNT and ETM1 CO0 output timing 0 0 1 0 1 0 Match between ECNT and ETM0 Setting prohibited Match between ECNT and ETM0, or fall of CI input Match between ECNT and ETM0, or match between ECNT and ETM1 1 1 CO1 output timing 0 0 1 0 1 0 Match between ECNT and ETM1 Setting prohibited Match between ECNT and ETM1, or fall of CI input Match between ECNT and ETM0, or match between ECNT and ETM1 1 1 87 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS 6.2.2 Timer/event counter output mode register (EOM) This is an 8-bit register which controls the operation of the timer/event counter output control circuit. First, the configuration of the functions of the output control cycle will be described. The block diagram of the CO0 output of the output control circuit is shown in Figure 6-3. The CO0 output is a master/slave type output, and the first-stage level F/F (LV0) holds the level to be output next. The next-stage output latch is used to output the LV0 level off chip. For the timing for inversion of the LV0 level and output off chip from LV0, the output timing specified by the timer/ event counter mode register is used. The configuration of the CO1 output is the same as that of the CO0 output. Figure 6-3. Output Control Circuit Block Diagram (CO0 Output) Level F/F Output latch LRE0 LRE1 LD0 CP0 CP1 CI LO0 R S LV0 INV Q D CK O PC6/CO0 The timer/event counter output mode register performs initialization and operation control for the output control circuit above; its configuration is shown in Figure 6-4. (1) LO0 & LO1 (bits 0 & 4) When LO0 or LO1 bit is set (1), the level of the level F/F (LV0 or LV1) is output to the output pin. These bits are automatically reset (0) when the level is output. (2) LD0 & LD1 (bits 1 & 5) These bits determine whether or not the LV0/LV1 level is inverted using the timing specified by the timer/ event counter mode register. When the LD0/LD1 bit is set (1), the LV0/LV1 level is inverted using the specified output timing. When the LD0/LD1 bit is reset (0), inversion is disabled. (3) LRE0, LRE1, LRE2, LRE3 (bits 2, 3, 6, 7) These bits perform level F/F setting/resetting: When the LRE0 or LRE2 bit is set (1), LV0 or LV1 is reset respectively; and when LRE1/LRE3 is set (1), LV0/LV1 is set. These bits automatically return to "0" when the level F/F is set/reset. 88 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS The timer/event counter output mode register is reset to 00H by RESET input and in the hardware STOP mode. Figure 6-4. Timer/Event Counter Output Mode Register Format 7 EOM 6 5 LD1 4 LO1 3 2 1 LD0 0 LO0 LV0 data output 0 1 No operation LV0 contents output (output trigger) LRE3 LRE2 LRE1 LRE0 LV0 level inversion 0 1 Disable Enable LV0 set/reset 0 0 1 1 0 1 0 1 No operation LV0 reset LV0 set Setting prohibited LV1 data output 0 1 No operation LV1 contents output LV1 level inversion 0 1 Disable Enable LV1 set/reset 0 0 1 1 0 1 0 1 No operation LV1 reset LV1 set Setting prohibited 89 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS 6.3 Timer/Event Counter Operation Timer/event counter operation is started by setting the count value and operating mode following the procedure shown in Figure 6-5. Once these settings have been made, operation continues in that mode until the mode register is set again. Figure 6-5. Timer/Event Counter Setting Procedure RESET input Clear timer/event counter upcounter (ECNT) Set count value in timer/event counter REG0/1 (ETM0/1) Timer/event counter output mode register (EOM) setting ; In case of programmable rectangular-wave output Timer/event counter mode register (ETMM) setting Port C mode setting (MCC) Start of count Interrupt Pin output 6.3.1 Interval timer mode In this mode, the timer functions as an interval timer which generates interrupts repeatedly with the specified count time as the interval. This interval timer allows a count to be specified from 1 µs to 65.535 ms with a resolution of 1 µs (at 12 MHz operation). After the timer/event counter upcounter (ECNT) is cleared, the count value is set in timer/event counter REG0/ 1 (ETM0/ETM1). Then when the data shown in Figure 6-6 is set in the timer/event counter mode register (ETMM), the timer/event counter operates as an interval timer using the internal clock (φ12) as the input clock. 90 CHAPTER 6 TIMER/EVENT COUNTER FUNCTIONS Figure 6-6. Timer/Event Counter Mode Register Setting (Interval Timer Mode) 7 ETMM 0 6 0 5 0 4 0 3 1 2 1 1 0 0 0 Internal clock ( φ 12) count ECNT cleared by match of ECNT and ETM1 contents ECNT counts up every 1 µs, and the respective comparator compares the ECNT count with the ETM0/ETM1 contents, and if a match is detected generates an internal interrupt (INTE0/INTE1) by means of a match signal (CP0/ CP1). Only in the event of a match between ECNT and ETM1, the ECNT contents are cleared and the count starts again from 0000H. Thus the timer functions as an interval timer which repeatedly generates interrupts using the count time determined by the count value set in ETM1 as the interval (see Figure 6-7). Caution Since ETMM setting and the start of the internal clock are asynchronous, it should be noted that some degree of error may arise in the first interval. Internal interrupts can be disabled by setting (1) the MKE0/MKE1 bits of the interrupt mask register (MKL). Figure 6-7. Interval Timer Mode Operation Internal clock (φ 12) CP0 0 m n0 m n0 CP1 INTE0 INTE1 Interrupt acknowledgment Start (ETMM setting) Interrupt ECNT acknowledgment clearance Interrupt ECNT acknowledgment clearance Remark ETM0=m ETM1=n (m 9 MHz 147 CHAPTER 8 ANALOG/DIGITAL CONVERTER FUNCTIONS The A/D channel mode register is cleared to 00H when a reset is performed, and A/D conversion is performed on pins AN0 to AN3 in the scan mode. The conversion values are stored in register CR0 to CR3, and it is possible that the interrupt request flag (INTFAD) may be set (1). Therefore, the interrupt request flag is reset (0) by a skip operation before setting the MKAD bit of the interrupt mask register (MKH) to "0" and releasing masking. The MKAD bit of the interrupt mask register (MKH) is reset(0), releasing masking of INTAD internal interrupts. The A/D converter initialization routine is shown below. ;*****A/D CONVERTER INITIALIZATION******* ADIN : LXI LXI LXI EXX MVI SKIT NOP ANI MKH, 0FEH ; INTAD enable ANM, 00H FAD H, 4000H B, 0301H D, 0101H ; Set data pointer ; Set counter ; Set counter ; Exchange register set ; ; Reset INTFAD In the INTAD interrupt service routine, the A/D conversion values in CR0 to CR3 are stored in the prescribed memory locations. The operation flow is shown below. 148 CHAPTER 8 ANALOG/DIGITAL CONVERTER FUNCTIONS ADSE Store contents of CR0 to CR3 in memory INTAD Y INTAD X 4? Breg N Set memory address HL ← HL + 1 Y 4020H end? N Creg 4004H end? N Y Dreg 4024H end? N Set memory address HL ← 4020H Y Ereg Set memory address HL ← 4004H Set counter C←0 Set memory address HL ← 4024H Set counters C←0 D←0 Set memory address HL ← 4000H Set counters C←1 D←1 E←1 Set counter B←3 Set A/D channel mode register invert ANI2 bit RETI The contents of CR0 to CR3 which hold the A/D conversion values for pins AN0 to AN3 or pins AN4 to AN7 are stored in the prescribed memory locations. A check is made to see if an INTAD internal interrupt has been generated 4 times: If fewer than 4, the HL register pair is incremented by 1 and control returns from the routine. If there have been 4 interrupts, the program jumps to . The B register is the counter used to check whether 4 interrupts have been generated. As the A/D conversion values are stored in memory blocks starting at address 4000H (4000H to 4003H, 4008H to 400BH, 4010H to 4013H, and 4018H to 401BH), the start address (4020H) of the next block is stored in the HL register pair, and 03H in the B register. The ANI2 bit of the A/D channel mode register is inverted to change the input pin on which A/D conversion is to be performed, and a return is made from the routine. When A/D conversion values are stored in the memory blocks starting at 4020H (4020H to 4023H, 4028H to 402BH, 4030H to 4033H, and 4038H to 403BH), the program jumps to . The C register is the counter used to check whether or not A/D conversion values have been stored in the memory blocks starting at 4020H. 149 CHAPTER 8 ANALOG/DIGITAL CONVERTER FUNCTIONS As the A/D conversion values are stored in memory blocks stating at address 4020H, the start address (4004H) of the next block is stored in the HL register pair, 03H in the B register, and 00H in the C register. The ANI2 bit of the A/D channel mode register is inverted to change the input pin on which A/D conversion is to be performed, and a return is made from the routine. When A/D conversion values are stored in the memory blocks starting at 4004H (4004H to 4007H, 400CH to 400FH, 4014H to 4017H, and 401CH to 401FH), the program jumps to . The D register is the counter used to check whether or not A/D conversion values have been stored in the memory blocks starting at 4004H. As the A/D conversion values are stored in memory blocks starting at address 4004H, the start address (4024H) of the next block is stored in the HL register pair, 03H in the B register, and 00H in the C register and D register. The ANI2 bit of the A/D channel mode register is inverted to change the input pin on which A/D conversion is to be performed, and a return is made from the routine. When A/D conversion values are stored in the memory blocks starting at 4024H (4024H to 4027H, 402CH to 402FH, 4034H to 4037H, and 403CH to 403FH), the program jumps to . The E register is the counter used to check whether or not A/D conversion values have been stored in the memory blocks starting at 4024H. The A/D conversion values are stored in memory blocks starting at address 4024H, and A/D conversion values are stored in the entire area from 4000H to 403FH. Therefore, initialization is performed in order to store A/D conversion values in the memory blocks starting at address 4000H once again. The interrupt service routine is shown below. A JMP ADSE instruction must be stored in the INTAD interrupt address. (0020H). 150 CHAPTER 8 ANALOG/DIGITAL CONVERTER FUNCTIONS ;*****A/D CONVERTER SERVICE****** ADSE : EXA EXX MOV STAX MOV STAX MOV STAX MOV STAX DCR JR DCR JR MOV DCR JR MOV DCR JR LXI LXI MVI JR ARIN : INX JR ARST0 : LXI JR ARST1 : LXI MOV JR ARST2 : LXI MOV MVI RET0 : MVI RET1 : MVI XRI RET2 : EXA EXX EI RETI A, CR0 H A, CR1 H+8H A, CR2 H+10H A, CR3 H+18H B ARIN C ARST0 A, D A ARST1 A, E A ARST2 H, 4000H D, 0101H C, 01H RET1 H RET2 H, 4020H RET1 H, 4004H D, A RET0 H, 4024H E, A D, 00H C, 00H B, 03H ANM, 08H ; Invert ANI2 bit ; Recover accumulator ; Recover register ; Enable interrupt ; Return ; Set data pointer ; Set data pointer ; Set data pointer ; Increment HL ; Set data pointer ; Set counter ; Set counter ; Store A/D conversion data to memory ; Decrement counter, skip if borrow ; Store A/D conversion data to memory ; Store A/D conversion data to memory ; Store A/D conversion data to memory ; Save accumulator ; Save register 151 [MEMO] 152 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS There are 3 kinds of external interrupt request (NMI, INT1, INT2) and 8 kinds of internal interrupt requests (INTT0, INTT1, INTE0, INTE1, INTEIN, INTAD, INTSR, INTST), plus a software interrupt instruction (SOFTI). The 11 kinds of interrupt requests excluding the SOFTI instruction are divided into 6 groups, each of which is assigned a different priority. The interrupt addresses for the 6 interrupt request groups and the SOFTI instruction are fixed, and are shown in Table 9-1. Table 9-1. Priorities and Interrupt Addresses Internal/ External 1 2 External Internal NMI INTT0 INTT1 3 External INT1 INT2 4 Internal INTE0 INTE1 5 INTEIN INTAD 6 INTSR INTST Falling edge (non-maskable interrupt) Match signal from TIMER0 Match signal from TIMER1 Rising edge Falling edge Match signal from timer/event counter Match signal from timer/event counter CI pin or TO fall signal A/D converter interrupt Serial reception interrupt Serial transmission interrupt SOFTI instruction 96 0060 40 0028 32 0020 24 0018 16 0010 Interrupt Address Decimal 4 8 Hexadecimal 0004 0008 Priority Interrupt Request 153 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9.1 Interrupt Control Circuit Configuration The interrupt control circuit consists of a request register, a mask register, a priority control, a test control, an interrupt enable F/F (IE F/F) and a test flag register. Figure 9-1. Interrupt Control Circuit Block Diagram NMI INTT0 INTT1 INT1 INT2 INTE0 INTE1 INTEIN INTAD INTSR INTST Request register INTFNMI Test control T.F Skip control INTFNMI Mask register IE F/F EI Priority control INTFNMI DI S R Q SOFTI Interrupt generation OV ER SB AN7–4 Test flag register T.F SOFTI INT. ADR (1) Request register This register consists of 11 interrupt request flags which are set by the different interrupt requests. A flag is reset when an interrupt request is acknowledged or a skip instruction (SKIT or SKNIT) is executed. RESET input resets all flags. The interrupt request flags are not affected by the interrupt mask register. • INTFNMI Set (1) by a falling edge input to the NMI pin. Unlike other interrupt request flags, this flag cannot be tested by a skip instruction. However, the status of the NMI pin can be tested (see (6) Test flag register). • • • • • • • INTFT0 Set (1) by TIMER0 match signal. INTFT1 Set (1) by TIMER1 match signal. INTF1 Set (1) by a rising edge input to the INT1 pin. INTF2 Set (1) by a falling edge input to the INT2 pin. INTFE0 Set (1) when timer/event counter ECNT and ETM0 register contents match. INTFE1 Set (1) when timer/event counter ECNT and ETM1 register contents match. INTFEIN Set (1) by a falling edge of the timer/event countr input (CI input) or timer output (TO). 154 Internal bus CHAPTER 9 INTERRUPT CONTROL FUNCTIONS • • • INTFAD Set (1) when A/D converter conversion values are transferred to the four registers CR0 to CR3. INTFSR Set (1) when the serial interface receive buffer becomes full. INTFST Set (1) when the serial interface transmit buffer becomes empty. (2) Mask register This is a 10-bit mask register which handles all interrupt requests except non-maskable interrupts (NMI). It can be set (1) or reset (0) bit-wise by an instruction. An interrupt request is masked (disabled) or enabled when the corresponding bit of the mask register is "1" or "0", respectively. When RESET is input and in the hardware STOP mode all bits of the mask register are set (1), masking all interrupt requests except non-maskable interrupts. 155 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS Figure 9-2. Mask Register (MKL, MKH) Format 7 MKL 6 5 4 3 2 1 0 – MKEIN MKE1 MKE0 MK2 MK1 MKT1 MKT0 0 1 INTT0 masking released INTT0 masked 0 1 INTT1 masking released INTT1 masked 0 1 INT1 masking released INT1 masked 0 1 INT2 masking released INT2 masked 0 1 INTE0 masking released INTE0 masked 0 1 INTE1 masking released INTE1 masked 0 1 INTEIN masking released INTEIN masked 7 MKH – 6 – 5 – 4 – 3 – 2 1 0 MKST MKSR MKAD 0 1 INTAD masking released INTAD masked 0 1 INTSR masking released INTSR masked 0 1 INTST masking released INTST masked 156 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS (3) Priority control circuit This circuit controls the 6 priority levels described earlier. If two or more interrupt request flags are set simultaneously, the interrupt with the highest priority according to Table 9-1 is acknowledged, and the remainder are held pending. (4) Test control circuit This circuit comes into operation when a skip instruction (SKIT or SKNIT) is executed to test interrupt request flags (except INTFNMI) for each interrupt source, NMI pin states and test flags which do not generate an interrupt request. (5) Interrupt enable F/F (IE F/F) This is a flip-flop which is set by the EI instruction and reset by the DI instruction. This flip-flop is reset when an interrupt is acknowledged, and by RESET input, hardware and in STOP mode. Interrupts are enabled when this flip-flop is set, and disabled when it is reset. Non-maskable interrupts can be acknowledged at any time irrespective of the status of this flip-flop. (6) Test flag register This register consists of 8 test flags which do not generate interrupt requests. • NMI Enables the NMI pin status to be tested. This flag is set to "1" when the NMI pin input level is "1", and "0" when the level is "0". • • • • OV Set (1) when the timer/event counter ECNT overflows. ER Set (1) in the event of a parity error, framing error or overrun error in serial reception. SB Set (1) if VDD pin increases from a level lower than specified to a level higher than specified. AN7 to AN4 Set (1) by a falling edge input to pins AN7 to AN4. Falling edge detection is performed by the same method as in the case of the INT2 pin. The above test flags can be tested by a skip instruction (SKIT or SKNIT). Test flags other than NMI are cleared when tested. The NMI test flag is not changed by execution of an instruction and the pin status can be tested as it is. 157 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9.2 External Interrupt Sampling Pins NMI, INT1, INT2, and AN7 to AN4 have a noise elimination function to prevent errors due to noise signals. (1) NMI input This is the falling-edge-active non-maskable interrupt input. When the NMI signal is detected to be low for at least a given time by the analog delay circuit, it is recognized as a normal signal and the INTFNMI interrupt request flag is set. At the end of the instruction INTFNMI is checked and if set, the program jumps to the interrupt address for non-maskable interrupts regardless of the EI/DI state. When an interrupt request is acknowledged, INTFNMI is automatically reset. (2) INT1 input This is the rising-edge-active maskable interrupt input. When the INT1 signal changes from low to high, and the high level is detected in 3 or more successive φ12 cycle sampling pulses (12 states: 2.4 µs at 15 MHz), the input is recognized as a normal signal and the INTF1 interrupt request flag is set. When masking is released in the EI state, a check is made that the INTF1 is set at the end of the instruction, and if there is no other interrupt request of higher priority, the INT1 interrupt is acknowledged and the program jumps to the interrupt address. Interrupt request flag resetting is described in 9.4 Maskable Interrupt Operation. A new INT1 interrupt is detected when the INT1 signal is high for at least 12 states after first returning to the low level. (3) INT2 input This is the falling-edge-active maskable interrupt input. Except for having the opposite active state, its functions are the same as those of the INT1 input. (4) AN7 to AN4 inputs A falling edge is detected by the same method as for the INT2 input, and the test flag is set (AN7 to AN4 of the test flag register). These flags can be tested by an instruction (SKIT or SKNIT), and are automatically reset when tested. In setting a testable flag again, the criterion for detection is a low-level input signal for a duration of at least 12 states after first returning to the high level. 158 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS Figure 9-3. Interrupt Sampling φ12 Sampling pulses INT2, AN7 – AN4 Valid Noise Valid INT1 INTF1, 2 AN7-AN4 As can be seen from the above diagram, INT1, INT2 and AN7 to AN4 are determined to be correct interrupt signals when the active level is detected in 3 or more φ12 (0.8 µs at 15 MHz operation) cycle sampling pulses. Therefore, noise signals of 8 states (1.6 µs at 15 MHz operation) or shorter duration are eliminated, and the interrupt request flag is properly set by a high-level or low-level input of at least 12 states (2.4 µs at 15 MHz operation). 159 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9.3 Non-Maskable Interrupt Operation When the INTFNMI interrupt request flag is set by a falling edge input to the NMI pin, a non-maskable interrupt is acknowledged by means of the following procedure irrespective of the EI/DI state (see Figure 9-4). (i) A check is made to see if INTFNMI is set at the end of each instruction. If INTFNMI is set, a non-maskable interrupt is acknowledged at INTFNMI is reset. (ii) When the non-maskable interrupt is acknowledged, the IE F/F is reset and all interrupts except for nonmaskable interrupts and the SOFTI instruction are placed in the disabled state (DI state). (iii) PSW, PC high byte and PC low byte are saved into the stack memory in that order. (iv) The program jumps to the interrupt address (0004H). These interrupt operations are automatically carried out in 16 states. Caution Operations when a non-maskable interrupt is generated directly after a maskable interrupt (1) (2) (3) (4) The PC value at the time of the interrupt is saved to the stack. The vector address of the maskable interrupt is stored in the PC, and the corresponding interrupt request flag is reset. Non-maskable interrupt servicing is executed before execution of the maskable interrupt routine. The non-maskable interrupt routine is executed. In this case, the return destination from the non-maskable interrupt routine is the maskable interrupt routine. 160 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS Figure 9-4. Interrupt Operation Procedure End of instruction Y NM I? N DI state? N All masked? N Y Y Reset INTFNMI Check nonmasked INTFx 2 or more Other interrupt Number of flags set 1 0 Check priority Next instruction Pending Highest-priority interrupt Same level interrupts both nonmaskable? Y N Reset INTFx Reset IE F/F Save PSW & PC to stack memory PC ← interrupt address 161 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS When execution of the interrupt service routine ends, processing is performed to return to the address at which the interrupt was acknowledged. First, registers, flags, etc., other than the PSW which have been save are restored, and if necessary the IE F/F is set by the EI instruction. Next, the RETI instruction is used to restore the previously saved return address and PSW in the order: Lower PC byte, upper PC byte, PSW. Since interrupt servicing is performed for non-maskable interrupts irrespective of the status of the IE F/F, they are useful for program processing in the event of an emergency such as a power failure. The configuration of the NMI pin is shown in Figure 9-5. Although INTFNMI cannot be tested by a skip instruction, the NMI pin status can be tested by a skip instruction (SKIT NMI or SKNIT NMI). Thus, in the non-maskable interrupt service routine, relatively wide noise can be removed by testing the NMI pin status several times using a skip instruction. The NMI pin status is not changed when tested by a skip instruction. Caution The IE F/F is reset unconditionally when a non-maskable interrupt is generated, and the contents of the IE F/F prior to the non-maskable interrupt are not saved. Therefore, when returning to the main routine the original status of the IE F/F should be determined by means of the stack address when the non-maskable interrupt was generated. Figure 9-5. Internal Configuration of NMI Pin NMI Falling edge detection NMI D Q S Q R Non-maskable interrupt request Non-maskable interrupt acknowledgment Test control µ PD78C18 162 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9.4 Maskable Interrupt Operation Interrupt requests except non-maskable interrupts and the SOFTI instruction are maskable interrupts which can be enabled/disabled (IE F/F set/reset) by the EI/DI instructions and can be masked individually by means of the mask register. When an external maskable interrupt is recognized as a normal interrupt signal by an active level input for more than the specified time, an interrupt request flag is set. If an internal interrupt request is generated, an interrupt request flag is immediately set. Once the interrupt request flag is set, both the external and internal interrupts are serviced using the following procedure (see Figure 9-3 Interrupt Sampling). (i) In the EI state (IE F/F=1), a check is made to see if the interrupt request flag has been set at the end checked at end of each instruction. If the flag has been set, the interrupt cycle starts. However, interrupt requests masked by the mask register are not checked. (ii) If two or more interrupt request flags have been set simultaneously, their priorities are checked. The interrupt with the highest priority is acknowledged and the others are held pending. (iii) When an interrupt request is acknowledged, the interrupt request flag is automatically reset. If two types of interrupt requests with the same priority have both been unmasked by the mask register, the interrupt request flag is not reset. This is because the two types are identified by software at a later stage. (iv) When an interrupt request is acknowledged, the IE F/F is reset, and all interrupts except non-maskable interrupts and the SOFTI instruction are placed in the disabled state (DI state). (v) The PSW, upper PC byte and lower PC byte are saved to the stack memory in that order. (vi) The program jumps to the interrupt address. These interrupt operations are automatically carried out in 16 states. The pending interrupt requests are acknowledged if there are no other interrupt requests of higher priority when interrupts are enabled by execution of the EI instruction. With maskable interrupts there are two types of interrupt requests with the same priority and same interrupt address. Unmasking both types, unmasking one type, or masking both kinds can be selected by setting the mask register. 163 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS (1) When both types are unmasked The corresponding bits of the mask register for two types of interrupt requests are both set to "0". In this case, the interrupt request is the logical sum of the two interrupt request flags. If an interrupt request is acknowledged in accordance with the interrupt operation as a result of setting one or both interrupt request flags having the same priority and the program jumps to the interrupt address, the interrupt request flag is not reset. Therefore, the interrupt request is identified by executing a skip instruction which tests the interrupt request flag at the beginning of the interrupt service routine, and the interrupt request flag is reset. The priority of interrupt requests with the same priority can be freely decided by the user by determining which of the two is first subject to execution of the skip instruction. The interrupt servicing sequence when both INT1 and INT2 are unmasked is shown in Figure 9-6. Figure 9-6. Interrupt Servicing Sequence (Masking released for both INT1 and INT2) (0010H) Save registers EI N INTF1=1 ? Y INT1 interrupt service program INT1 or INT2 INTF2=1 ? Y N INT2 interrupt service program Restore registers EI RETI Remark In this example masking is released for both INT1 and INT2 interrupt requests which have the same priority. 164 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS (2) When one type is unmasked For two types of interrupt requests having the same priority, the corresponding bit of the mask register for the interrupt request to be unmasked is set to "0" and the other bit is set to "1". In this case, if an interrupt request is generated by setting the unmasked interrupt request flag and that interrupt request is acknowledged in accordance with the interrupt operation, the interrupt request flag is automatically reset. When the masked interrupt request flag is set, that interrupt request is held pending. When the pending interrupt request is unmasked, it is acknowledged if there are no other interrupt requests of higher priority in the interrupt enable state. Whether or not the interrupt request flag for the acknowledged interrupt is automatically reset depends on the setting of the mask register of the same priority. If the other interrupt request is masked when masking is released the interrupt request flag is automatically reset, but if the other interrupt request remains unmasked when masking is released, the interrupt request flag is not reset even though the interrupt request is acknowledged (see 9.4 (1) When both types are unmasked). Figure 9-7. Interrupt Servicing Sequence (Masking released for either INT1 or INT2) EI Save registers INT Interrupt service program Restore registers EI RETI Remark In this example masking is released by the mask register for one of the interrupt requests which have the same priority. 165 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS (3) When both types are masked The corresponding bits of the mask register for two types of interrupt request are both set to "1". In this case, the interrupt requests are held pending are not acknowledged when the interrupt request flag is set. When the pending interrupt requests are unmasked, they are acknowledged if there are no other interrupt requests of higher priority in the interrupt enabled state. When execution of the interrupt service routine ends, processing is performed to return to the address at which the interrupt was acknowledged. First, registers, flags, etc., other than the PSW which have been saved are restored, and the IE F/F is set by the EI instruction. Next, an RETI instruction is executed to restore the previously saved return address and PSW in the order: lower PC byte, upper PC byte, PSW. 166 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9.5 Interrupt Operation by SOFTI Instruction When the SOFTI instruction is executed, the program jumps unconditionally to the interrupt address (0060H). The SOFTI instruction interrupt is not affected by the IE F/F, and the IE F/F is not affected when this instruction is executed. The servicing procedure for an interrupt generated by the SOFTI instruction is as follows: (i) The PSW, upper PC byte and lower PC byte are saved to the stack memory in that order. (ii) The program jumps to the interrupt address (0060H). When execution of the interrupt service routine ends, processing is performed to return to the address at which the interrupt was acknowledged. First, registers, flags, etc., other than the PSW which have been saved are restored. Next, a RETI instruction is executed to restore the previously saved return address and PSW in the order: lower PC byte, upper PC byte, PSW. Caution If the skip condition is satisfied by the instruction (arithmetic or logical operation, increment/ decrement, shift, skip or RETS instruction) immediately before the SOFTI instruction, the SOFTI instruction is executed and not skipped. When SOFTI instruction is executed, the SK flag of the PSW is saved as set (1) to the stack area. Thus, when the return is made from the SOFTI service routine, the PSW SK flag remains set and the instruction following the SOFTI instruction is skipped. Note that the 87AD series SOFTI instruction differs from that of the µCOM-87 in that the address contents saved to the stack memory are the start address of the next instruction. 167 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9.6 Interrupt Wait Time The time required from acknowledgement by the CPU of an asynchronously generated external interrupt until execution of the first instruction of the relevant interrupt service routine begins (the interrupt wait time) is the sum of time components I, II and III shown in Table 9-2. This interrupt wait time varies depending on the kind of instruction being executed when the interrupt occurs and the instruction timing at which the interrupt occurs. Table 9-2 shows maximum interrupt wait times. The 14 states of component I (10 µs max. in the case of NMI) indicate the time required until the interrupt request signal becomes active and is recognized as a normal signal, and INTFx is set (1). Therefore, this time is only required in the case of NMI, INT1 and INT2 interrupts. The 59 states of component II indicate the instruction execution time for the longest instruction. This time depends on the performance of the INTFx check at the end of each instruction (METE). Thus the required time for component II varies depending on the instruction being executed at that time, from a minimum of 4 states to a maximum of 59 states. The 16 states of component III represent the time required to save the contents of the PSW and PC to the stack memory. Table 9-2. Maximum Interrupt Wait Time Wait Time Components I II III Time required for noise elimination Time required for instruction execution (divide instruction) Time required for automatic save processing Total time INT1, INT2 14 states 59 states 16 states 89 states NMI 10 µs MAX. 59 states 16 states 75 states + 10 µs Others 0 states 59 states 16 states 75 states (22.25 µs/12 MHz) (28.75 µs/12 MHz) (18.75 µs/12 MHz) 168 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9.7 Multiple Interrupts When the EI instruction is executed all external and internal interrupt requests are enabled even when an interrupt service routine is being executed. Therefore, when the EI instruction is executed during execution of an interrupt service routine, acknowledgement is enabled even for that interrupt request itself or interrupt requests of lower priority. In this case too, if multiple interrupt requests are generated simultaneously, the highest-priority request is acknowledged and the lower-priority requests are held pending. The pending interrupt requests are acknowledged when the EI state is subsequently entered, if no other interrupt requests of higher priority have been generated. Since there are practically no restrictions on the stack area used when an interrupt is generated as long as the memory size is sufficient, multiple interrupt levels can also be used without restriction (see Figure 9-8). Figure 9-8. 3-Level Multiple Interrupts (0010H) (0008H) EI EI INTT0 EI EI ORI MKH, 02H INTE0 INTSR Not acknowledged (0018H) INT1 ANI MKH, 0FDH (0028H) RETI RETI EI RETI EI RETI Remark If masking is released by the mask register for two interrupt sources of the same priority, which of the two interrupt requests is concerned must be determined before executing the EI instruction at the start of the interrupt service routine. 169 [MEMO] 170 CHAPTER 10 CONTROL FUNCTIONS 10.1 Standby Functions Three standby modes are available for the µPD78C18 to save power consumption in the program standby state: The HALT mode, software STOP mode, and hardware STOP mode. 10.1.1 HALT mode When the HLT instruction is executed, the HALT mode is set unless the interrupt request flag of the unmasked interrupt is set. In the HALT mode the CPU clock stops and program execution also stops. However, the contents of all registers and on-chip RAM just before the stoppage are retained. In the HALT mode, the timer, timer/event counter, serial interface, A/D converter and interrupt control circuit are operational. Table 10-1 shows the status of the µPD78C18 output pins in the HALT mode. Table 10-1. Output Pin Statuses Output Pin PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PF7 to PF0 Single ChipNote 1 Data retained Data retained Data retained Data retained Data retained External Expansion Data retained Data retained Data retained High-impedance Next address retainedNote 2 Data retainedNote 3 WR, RD ALE Notes 1. 2. 3. High-level High-level High-level High-level µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14 Address output pin Port data output pin Cautions 1. Because an interrupt request flag is used to release the HALT mode, HLT instruction execution does not set the HALT mode if even a single interrupt request flag for an unmasked interrupt is set. Thus, when setting the HALT mode when there is a possibility that an interrupt request flag may have been set (when there is a pending interrupt), one of the following procedures should be followed: First process the pending interrupt; or, reset the interrupt request flag by executing a skip instruction; or, mask all interrupts except those used to release the HALT mode. 2. This function is valid when pins PC7 to PC0 are in the control signal input/output mode. Therefore, TO output and serial transmission/reception is enabled in the HALT mode. 171 CHAPTER 10 CONTROL FUNCTIONS 10.1.2 HALT mode release (1) Release by RESET signal When the RESET signal changes from the high to low level in the HALT mode, the HALT mode is released and the reset state is set. When the RESET signal returns to the high level, the CPU starts program execution at address 0. When the RESET signal is input, the RAM contents are retained but the contents of other registers are indeterminate. Figure 10-1. HALT Mode Release Timing (RESET Signal Input) Execution of address 0 instruction CPU HLT CSC RESET (2) Release by interrupt request flag The HALT mode is released if at least one interrupt request flag is set by the generation of a non-maskable interrupt (NMI) or one of ten unmasked maskable interrupts (INTT0, INTT1, INT1, INT2, INTE0, INTE1, INTEIN, INTAD, INTST and INTSR). When the HALT mode is released by a non-maskable interrupt, the instruction following the HLT instruction is not executed and the program jumps to the interrupt address (0004H) irrespective of the interrupt enabled/ disabled (EI/DI) state. When the HALT mode is released by a maskable interrupt, operation after release differs depending on whether the EI or DI state is set. 172 CHAPTER 10 CONTROL FUNCTIONS (i) EI state The instruction following the HLT instruction is not executed and the program jumps to the corresponding interrupt address. Figure 10-2. HALT Mode Release Timing (In EI State) CPU operation Interrupt execution Interrupt routine HLT OSC INTFx (ii) DI state Execution restarts with the instruction following the HLT instruction (without jumping to the interrupt address). Since the interrupt request flag used for release remains set, it should be reset by a skip instruction when required. Figure 10-3. HALT Mode Release Timing (In DI State) Execution of next instruction HLT CPU operation OSC INTFx 173 CHAPTER 10 CONTROL FUNCTIONS 10.1.3 Software STOP mode When the STOP instruction is executed, the software STOP mode is set unless the interrupt request flag for an unmasked external interrupt is set. In the software STOP mode, all clocks stop. When this mode is set, program execution stops and the contents of all registers, on-chip RAM and flags except FT0 and FT1 just before stoppage are retained (the timer upcounter is cleared to 00H). Only the NMI and RESET signals used to release the software STOP mode are valid, and all other functions stop. The statuses of the µPD78C18 output pins in the software STOP mode are the same as for the HALT mode, as shown in Table 10-2. Table 10-2. Output Pin Statuses Output Pin PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PF7 to PF0 Single ChipNote 1 Data retained Data retained Data retained Data retained Data retained External Expansion Data retained Data retained Data retained High-impedance Next address retainedNote 2 Data retainedNote 3 WR, RD ALE Notes 1. 2. 3. High-level High-level High-level High-level µPD78C18/78C14/78C14A/78C12A/78C11A/78CP18/78CP14 Address output pin Port data output pin Cautions 1. Internal interrupts should be masked before executing the STOP instruction to prevent errors due to an internal interrupt with the oscillation stabilization time upon release of the software STOP mode. 2. The TIMER1 coincidence signal is used as the signal to start CPU operation to secure an oscillation stabilization period after the software STOP mode has been released by setting the non-maskable interrupt request flag. Thus, it is necessary to set a count value in timer REG which takes account of the oscillation stabilization time, and to set the timer mode register to the timer operating state, before executing the STOP instruction. 3. Crystal oscillation or ceramic oscillation should be used when using the software STOP mode. The software STOP mode must not be used when an external clock is input. 174 CHAPTER 10 CONTROL FUNCTIONS 10.1.4 Software STOP mode release (1) Release by RESET signal When the RESET signal changes from the high to low level in the software STOP mode, the software STOP mode is released and clock oscillation starts as soon as the reset state is set. When the RESET signal is driven high after oscillation has stabilized, the CPU starts program execution at address 0. When the RESET signal changes from the high to low level, clock oscillation starts but it takes time for oscillation to stabilize. The RESET signal low-level width must therefore be longer than the oscillation stabilization time. When the RESET signal is input, the RAM contents are retained but the contents of other registers are indeterminate. Figure 10-4. Software STOP Mode Release Timing (RESET Signal Input) Execution of address 0 instruction STOP CPU operation OSC RESET If the software STOP mode is released by the RESET signal, program execution starts at address 0 as in the case of a normal power-on reset. The SB (Standby) flag can be used to identify the program execution mode. The SB flag is set (1) when the VDD pin rises from the specified low level or below to the specified high level or above, and is reset (0) by executing a skip instruction. Thus, testing the SB flag using a skip instruction in the program executed after RESET input makes it possible to differentiate between a power-on start and a start due to release of the software STOP mode (see Figure 10-5). A set (1) SB flag indicates a poweron start, and a reset (0) SB flag indicates a start due to release of the software STOP mode. 175 CHAPTER 10 CONTROL FUNCTIONS Figure 10-5. SB Flag Operation VDD RESET SB flag CPU operation Note 1 Note 2 Note 3 Note 1 Note 2 Software STOP mode Notes 1. Execution of address 0 instruction 2. Execution of SKIT SB or SKNIT SB instruction 3. Execution of STOP instruction (2) Release by NMI pin input When the non-maskable interrupt request flag is set (i.e. when the NMI pin input changes from high to low) in the software STOP mode, the software STOP mode is released and simultaneously clock oscillation starts. When clock oscillation starts, the timer upcounter starts counting up from 00H in accordance with the setting before execution of the STOP instruction. CPU operation is started by a match signal (wait time taking account of the oscillation stabilization time) from the TIMER1 upcounter. In this case, the upcounter match signal does not set the interrupt request flag. The timer mode register of the timer after generation of the match signal is set to FFH and timer operation is stopped. After the elapse of the oscillation stabilization time, the program jumps to the interrupt address (0004H) irrespective of the interrupt enabled/disabled (EI/DI) state and without executing the instruction following the STOP instruction. Figure 10-6. Software STOP Mode Release Timing (NMI Signal Input) Interrupt execution STOP Interrupt routine CPU operation OSC NMI INTFNMI Wait (programmable) TIMER1 match signal 176 CHAPTER 10 CONTROL FUNCTIONS 10.1.5 Hardware STOP mode When the STOP signal changes from the high to low level, the hardware STOP mode is set. In this mode all clocks stop. When the hardware STOP mode is set, program execution stops and the on-chip RAM contents just before stoppage are retained, and the STOP signal used to release the hardware STOP mode is valid. All other functions stop and the reset state is set. In the hardware STOP mode, the µPD78C18 output pins become high-impedance. However, the port output latch values are retained. Cautions 1. Crystal oscillation or ceramic oscillation should be used when using the hardware STOP mode. The hardware STOP mode must not be used when an external clock is input. 2. The STOP mode is entered at a machine cycle boundary. Thus memory contents are not corrupted, but the STOP mode may be entered midway through execution of an instruction. Therefore, with instructions which perform a 16-bit data transfer the STOP mode may be entered after only 8 bits have been transferred, with the transfer of the remaining 8 bits incomplete (16-bit data transfer instructions and call instructions). 3. If the STOP signal is input (high low level) during reset input (RESET = low level), a transition is made from the reset state to the STOP mode. 4. The STOP pin must be driven high after powering-on. The reset will not function correctly if the STOP pin is left low. The STOP pin can be driven low after oscillator operation has stabilized. 177 CHAPTER 10 CONTROL FUNCTIONS 10.1.6 Hardware STOP mode release When the STOP signal changes from the low to high level in the hardware STOP mode, the hardware STOP mode is released and simultaneously clock oscillation starts. After the elapse of the wait time (approximately 65 ms at 12 MHz) which takes account of the oscillation stabilization time, the CPU starts program execution at address 0 (see Figure 10-7). Figure 10-7. Hardware STOP Mode Release Timing (STOP Signal Input) STOP Instruction execution Wait (approx. 65 ms/12 MHz) Execution of address 0 instruction CPU operation OSC The hardware STOP mode is not released by a high-to-low transition of the RESET signal. When the STOP signal changes from low to high while the RESET signal is low, the hardware STOP mode is released and clock oscillation starts. If the RESET signal returns from the low to high level, the CPU starts program execution at address 0 without waiting for the elapse of the oscillation stabilization time (see Figure 10-8). If the RESET signal changes from the high to low level just after the hardware STOP mode has been released (after the STOP signal has changed from the low to high level), program execution starts when the RESET signal chnages from the low to high level (see Figure 10-9). The oscillation stabilization time should therefore be taken into account when returning the RESET signal to the high level. After RESET signal input RAM contents are retained, but the contents of other registers are undefined. Figure 10-8. Hardware STOP Mode Release Timing (RESET Signal Input) STOP Instruction execution CPU operation Wait RESET Execution of address 0 instruction OSC 178 CHAPTER 10 CONTROL FUNCTIONS Figure 10-9. Hardware STOP Mode Release Timing (STOP Signal Rising to RESET Signal Input) STOP Instruction execution CPU operation Execution of address 0 instruction RESET OSC In the case of a hardware STOP mode release, as with a release of the software STOP mode by means of the RESET signal, it is possible to differentiate between a power-on start and a start due to release of the hardware STOP mode by testing the SB flag using a skip instruction. 10.1.7 Low supply voltage data retention mode The low supply voltage data retention mode can be set by decreasing the VDD supply voltage after setting the software/hardware STOP mode. RAM contents can be retained with lower power dissipation than in the software/ hardware STOP mode. When returning from the software/hardware STOP mode by means of a reset, the SB flag is used to determine whether the reset is a power-on reset. The SB flag is set (1) only when the supply voltage (VDD) changes from a given voltage or below to a given voltage or above. This flag can be tested by the SKIT SB or SKNIT SB instruction, and is automatically reset (0) when either of these instructions is executed. Figure 10-10. Relation between VDD and SB Flag VDD SB flag STOP mode entered Instruction execution SKIT SB SKNIT SB Caution The software/hardware STOP mode should not be released while in the low supply voltage data retention mode. VDD must be raised to the normal operating voltage before the release is performed. 179 CHAPTER 10 CONTROL FUNCTIONS 10.2 Reset Functions When a low level signal is input to the RESET pin, a system reset is effected and initialization is performed as shown below. Table 10-3. Hardware States after Reset (1/2) Hardware Internal data memory Power-on reset Reset input during normal operation During non-write CPU operation Extended accumulator (EA, EA') Accumulators (A, A') General-purpose register (B, C, D, E, H, L, B', C', D', E', H', L') Working register/vector register (V, V') Program counter (PC) Stack pointer (SP) Ports Mode registers (MA, MB, MC, MF) Mode control register (MMC) MM registers (MM0, 1, 2) Port output latches Interrupts Interrupt enable F/F Request flags Mask register Test flags (except SB flag) Standby flag (SB) Power-on reset In standby mode Reset input during normal operation FFH 0 1 Previous contents retained Contents before RESET input retained Timer Timer mode register (TMM) Timer F/F Timer registers (TM0, TM1) Timer/event counter Timer/event counter mode register (ETMM) Timer/event counter output mode register (EOM) Timer/event counter registers (ETM0, ETM1) Timer/event counter capture register (ECPT) Timer/event counter (ECNT) Serial interface Serial mode high register (SMH) Serial mode low register (SML) 00H 48H Undefined FFH 0 Undefined 00H Undefined 0 0000H Undefined FFH 00H Undefined During CPU write operation Write address data Data in other addresses State after Reset Previous contents retained Undefined Previous contents retained 180 CHAPTER 10 CONTROL FUNCTIONS Table 10-3. Hardware States after Reset (2/2) Hardware A/D channel mode register (ANM) MM register RAE bit (MM3) Zero-cross mode register (ZC) 00H Undefined 1 State after Reset Table 10-4. Pin States after Reset Pin WR RD ALE All ports (PA, PB, PC, PD, PF) State after Reset High-impedance When the RESET input changes from low to high, program execution starts at address 0000H; the contents of the various registers should be initialized or re-initialized as required in the program. Caution With an external clock input, if VDD is within the operating voltage range all the pins are highimpedance after RESET signal input. Then a system reset is effected after X1 input. However, this does not apply when the clock is not input at all to X1 after powering-on. X1 input X1 RESET input RESET System reset Ports become high-impedance. 181 CHAPTER 10 CONTROL FUNCTIONS 10.3 Clock Generation Circuit The µPD78C18 incorporates a clock generation circuit, allowing the necessary clock to be generated simply by connecting a crystal or a ceramic resonator and capacitors. It is also possible to input an externally generated clock. Figure 10-11 shows a circuit with a resonator connected, and Figure 10-12 shows an example of a circuit when an external clock is input. Figure 10-11. Oscillator Connection Circuit Figure 10-12. Example of External Clock Input Circuit µ PD78C18 X1 X2 X1 µ PD78C18 X2 C1 C2 HCMOS inverter Caution When using the system clock oscillator, the shaded area in Figure 10-11 should be wired in order to avoid effects of wiring capacitor etc., as shown below. • Minimize the length of wiring. • Do not cross other signal lines, or position wiring close to a variable high current. • The connecting point of the oscillator capacitor should always be the same potential as VSS. Do not connect it to the gland pattern where there is a high current. • Do not pick up the signal from the oscillator. 182 CHAPTER 10 CONTROL FUNCTIONS Figure 10-13. Examples of Poor Resonator Connection Circuit (a) Long Connection Circuit Wiring (b) Crossed Signal Lines µ PD78C18 X1 X2 VSS X1 µ PD78C18 X2 PAn VSS (c) Signal Line Close to Varying High Current (d) Current Flows an Oscillator Ground Line (Potentials at A, B, and C fluctuate) VDD µ PD78C18 µ PD78C18 X1 X2 VSS PAn X1 High current X2 VSS A B C (e) Signal is Picked Up µ PD78C18 X1 X2 VSS 183 CHAPTER 10 CONTROL FUNCTIONS The wiring should also be kept as short as possible when an external clock is input, to prevent the effects of extraneous electromagnetic wave radiation or external noise. When the hardware/software STOP mode is entered, the X1 and X2 pin levels are fixed. Therefore, the hardware/ software STOP mode should not be used when an external clock is used. When the hardware/software STOP mode is used, a crystal or ceramic resonator should be used. When the device is powered on, and when returning from the hardware/software STOP mode, sufficient time must be allowed for the oscillation to stabilize. The time required for oscillation stabilization is several ms when a crystal is used, and several hundred µs when a ceramic resonator is used. An adequate oscillation stabilization period should be secured by the following means: RESET input when powering-on (reset period). RESET input (reset period) or automatically used timer when returning from the hardware STOP mode. RESET input or preset timer when returning from the software STOP mode. Using a crystal resonator, C1 = C2 = 10 pF should be kept. The values of C1 and C2 as recommended resonator when a ceramic resonator is used are shown in Table 10-5. 184 CHAPTER 10 CONTROL FUNCTIONS Table 10-5. Recommended Ceramic Resonator (1/2) Recommended C1 [pF] C2 [pF] 15 30 Built in Built in 30 Built in Built in Built in Built in Built in 22 30 Built in Built in 30 Built in Built in 30 Built in Built in Built in Built in Built in 22 30 Built in Built in 30 Built in Built in 30 Built in Built in Product Name Manufacturer Murata Mfg. Co., Ltd. Part Name CSA15.00MX001 CSA12.0MT CST12.0MT CST12.0MTW CSA7.37MT CST7.37MT CST7.37MTW µPD78C10A, 78C11A, 78C12A 15 30 Build in Built in 30 Built in Built in Built in Built in Built in 22 30 Built in Built in 30 Built in Built in 30 Built in Built in Built in Built in Built in 22 30 Built in Built in 30 Built in Built in 30 Built in Built in TDK FCR15.0MC FCR10.0MC FCR8.0MC µPD78C14 Murata Mfg. Co., Ltd. CSA15.0MX3 CSA12.0MT CST12.0MT CST12.0MTW CSA10.0MT CST10.0MT CST10.0MTW CSA6.00MG CST6.00MG TDK FCR15.0MC FCR12.0MC FCR10.0MC FCR8.0MC µPD78C14A Murata Mfg. Co., Ltd. CSA15.0MX3 CSA12.0MT CST12.0MT CST12.0MTW CSA10.0MT CST10.0MT CST10.0MTW CSA6.00MG CST6.00MG TDK FCR12.0MC 185 CHAPTER 10 CONTROL FUNCTIONS Table 10-5. Recommended Ceramic Resonator (2/2) Recommended Product Name Manufacturer Murata Mfg. Co., Ltd. Part Name C1 [pF] C2 [pF] 22 30 Built in 30 Built in 30 Built in 30 Built in 22 Built in 30 Built in 30 Built in Built in Built in Built in CSA15.0MX3 CSA12.0MT CST12.0MT 22 30 Built in 30 Built in 30 Built in 30 Built in 22 Built in 30 Built in 30 Built in Built in Built in Built in µPD78CG14 µPD78CP14 Murata Mfg. Co., Ltd. CSA12.0MT CST12.0MTW CSA10.0MT CST10.0MTW CSA8.00MT CST8.00MTW µPD78C17, 78C18 Murata Mfg. Co., Ltd. CSA15.00MX001 CST15.00MXW001 CSA10.0MT CST10.0MTW CSA8.00MT CST8.00MTW TDK FCR15.0MC FCR10.0MC FCR8.0MC Remark Use of crystal and ceramic resonator Generally speaking, the oscillation frequency of a crystal is extremely stable, and it is therefore ideal for high-precision time management (for example, in clocks and watches, measuring instruments, etc.). The oscillation frequency stability of a ceramic resonator is not as high as that of a crystal, but it offers three advantages: a fast oscillation start-up time, small size, and low cost. It is therefore suitable for general applications in which high-precision time management is not required. In addition, products with built-in capacitors, etc., are available, offering the advantage of fewer parts and reduced mounting area. 186 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11.1 µPD78C18/78C14/78C14A/78C12A/78C11A External Device Accesses For the µPD78C18/78C14/78C14A/78C12A/78C11A, the areas shown below can be used for external device expansion (data memory, program memory or peripheral devices). • • • • µPD78C18 µPD78C12A µPD78C11A : Addresses 8000H to FBFFH (31K bytes) : Addresses 2000H to FEFFH (56K bytes) : Addresses 1000H to FEFFH (60K bytes) µPD78C14, 78C14A : Addresses 4000H to FEFFH (48K bytes) The memory mapping register (MM) is used for external device expansion. Pins PD7 to PD0 are used as a multiplexed address/data bus (AD7 to AD0), and pins PF7 to PF0 are used as an address bus (AB15 to AB8). With pins PF7 to PF0, the number of bits functioning as the address bus can be varied according to the size of the external expansion memory, and memory can be expanded in steps from 256 bytes up to 31K/48K/56K/60K bytes (depending on the product). Pins which are not used for the address bus can be used as general-purpose input/output port pins (see Table 11-1). Table 11-1. PF7 to PF0 Address Bus Selection PF7 Port Port Port AB15 PF6 Port Port Port AB14 PF5 Port Port AB13 AB13 PF4 Port Port AB12 AB12 PF3 Port AB11 AB11 AB11 PF2 Port AB10 AB10 AB10 PF1 Port AB9 AB9 AB9 PF0 Port AB8 AB8 AB8 External Address Space Up to 256 bytes Up to 4K bytes Up to 16K bytes Up to 31K/48K/56K/60K bytesNote Note 31K (µPD78C18), 48K (µPD78C14/78C14A), 56K (µPD78C12A), 60K (µPD78C11A) When an external device reference instruction is executed in the 256-byte expansion mode, the µPD78C18/78C14/ 78C14A/78C12A/78C11A masks the high-order 8 bits of the 16-bit external reference address, and outputs a value from 00H to FFH from pins PD7 to PD0 (AD7 to AD0) as address information. 187 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Similarly, in the 4K-byte expansion mode, the µPD78C18/78C14/78C14A/78C12A/78C11A masks the high-order 4 bits of the 16-bit external reference address, and outputs a value from 000H to FFFH from pins PF3 to PF0 (AB11 to AB8) and pins PD7 to PD0 as address information. Similarly, in the 16K-byte expansion mode, the µPD78C18/78C14/78C14A/78C12A/78C11A masks the high-order 2 bits of the 16-bit external reference address, and outputs a value from 0000H to 3FFFH from pins PF5 to PF0 (AB13 to AB8) and pins PD7 to PD0 as address information. As the high-order bits of the 16-bit address are masked in this way in the 256-byte/4K-byte/16K-byte expansion modes, the external device can be located in any desired 256-byte/4K-byte/16K-byte area in the external 60K-byte area. However, if, in the 16K-byte expansion mode, external ROM is connected in the expansion area and addresses 1000H to 4FFFH following the on-chip ROM are used as the external ROM area, it should be noted that there will be the following differences between the program counter (PC) and the address which is actually output from pins PF5 through PF0 and PD7 through PD0. PC 1000H 3FFFH 4000H 4FFFH … … PF5-0, PD7-0 1000H 3FFFH 0000H 0FFFH … … When external ROM addresses are used as consecutive addresses, the external ROM area should be set in addresses 4000H to 7FFFH. Since, in this case, on-chip ROM and external ROM are not in consecutive addresses, a jump instruction must be used to move the program to the respective areas. The same applies if the external ROM area is set in addresses 8000H to BFFFH. Cautions 1. The internal address bus contents are output in all machine cycles to port D when it is functioning as an address/data bus. Also, the internal address bus contents are output in all machine cycles from port F pins functioning as an address bus. However, RD and WR signals are only output in a memory cycle. 2. Software which dynamically changes the operating mode of port D and port F cannot be emulated by an emulator, and therefore should not be used. 188 Figure 11-1. External Expansion Modes Set by Memory Mapping Register Port mode 0 On-chip ROM (4K/8K/16K/32K bytes) 256-byte expansion mode 4K-byte expansion mode 16K-byte expansion mode 31K/48K/56K/60K-byte expansion mode CHAPTER 11 On-chip ROM (4K/8K/16K/32K bytes) On-chip ROM (4K/8K/16K/32K bytes) On-chip ROM (4K/8K/16K/32K bytes) On-chip ROM (4K/8K/16K/32K bytes) 


,,,   
,  


,,,     
,,

  

 
,, 
,  
, , 

,    
,  
,    
,  
,   EXTERNAL DEVICE ACCESSES AND TIMINGS Not used External memory (16K bytes) Not used Not used External memory (31K/48K/56K/60K bytes) External memory (4K bytes) External memory (256 bytes) Not used Not used Not used On-chip RAM On-chip RAM On-chip RAM On-chip RAM On-chip RAM 64K 189 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11.1.1 Memory mapping register (MM) The memory mapping register is an 8-bit register which performs the following controls: • Port/expansion mode specification for PD7 to PD0 and PF7 to PF0 • Enabling/disabling of on-chip RAM accesses • Specification of on-chip EPROM access range (µPD78CP18/78CP14 only: See CHAPTER 12 PROM ACCESSES (µPD78CP18/78CP14 ONLY)) The configuration of the memory mapping register is shown in Figure 11-2. (1) Bits MM0 to MM2 These bits control the PD7 to PD0 port/expansion mode and input/output specification, and the PF7 to PF0 address output specification. As shown in Figure 11-2, there is a choice of four capacities for the connectable external memory: • 256 bytes • 4K bytes • 16K bytes • 31K/48K/56K/60K bytes: 31K bytes of external expansion memory can be connected to the µPD78C18, 48K bytes to the µPD78C14/78C14A, 56K bytes to the µPD78C12A, and 60K bytes to the µPD78C11A. Any of the pins PF7 to PF0 not used as address outputs can be used as general-purpose port pins. RESET input or the hardware STOP mode resets (0) these bits and sets PD7 to PD0 to input port mode (highimpedance). (2) MM3 bit (RAE) This bit controls enabling (RAE=1) and disabling (RAE=0) of on-chip RAM accesses. This bit should be set to "0" during standby operation and when externally connected RAM and not on-chip RAM is used. In normal operation this bit retains its value when RESET is input. Cautions 1. Overwriting the RAE bit during program execution allows an apparent increase of 256 bytes in the memory space. However, this operation cannot be emulated by an emulator, and should therefore not be performed. 2. The RAE bit is undefined after a power-on reset, and must therefore be initialized by an instruction. 190 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS In the µPD78CP18/78CP14, bit MM5 to MM7 are also valid: These are used to specify the access range of the on-chip EPROM. See CHAPTER 12 PROM ACCESSES (µPD78CP18/78CP14 ONLY) for details. Figure 11-2. Memory Mapping Register Format (µPD78C18/78C14/78C14A/78C12A/78C11A) 7 – 6 – 5 – 4 – 3 RAE 2 1 0 MM2 MM1 MM0 PD7 to PD0 = Input port Port mode 0 0 0 PF7 to PF0 = Port mode Single chip PD7 to PD0 = Output port PF7 to PF0 = Port mode 0 1 0 256 bytes PD7 to PD0 = Expansion mode PF7 to PF0 = Port mode PD7 to PD0 Expansion mode 1 0 0 4K bytes PF3 to PF0 = Expansion mode 0 0 1 PF7 to PF4 = Port mode PD7 to PD0 16K bytes PF5 to PF0 = Expansion mode 1 1 0 PF7 & PF6 = Port mode 1 1 1 31K/48K/56K/ 60K bytesNote PD7 to PD0 PF7 to PF0 = Expansion mode On-chip RAM access 0 1 Disable Enable Note 31K (µPD78C18), 48K (µPD78C14/78C14A), 56K (µPD78C12A), 60K (µPD78C11A) 191 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11.1.2 Example of memory expansion Figure 11-3 shows an example of a configuration with 16K bytes of external expansion ROM, and Figure 11-4 shows the data set in the memory mapping register for this configuration. Figure 11-3. Example of Memory Expansion (Reference Diagram) VDD 87AD series MODE1 MODE0 O0~7 Standby control STOP RD OE µ PD27C512 A0~7 VDD ALE LE VDD AVDD VAREF OE PF5-0 (AB13-8) AB13-8 Note CE A14, 15 A8~13 PD7-0 (AD7-0) AD7-0 DI DO µ PD74HC573 VSS AVSS PF7, 6 System reset RESET X1 X2 Note µPD27C512 uses only 16K bytes. 192 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Figure 11-4. Memory Mapping Register Settings 7 MM – 6 – 5 – 4 – 3 RAE 2 1 1 1 0 0 PD7 to PD0 : Expansion mode PF5 to PF0 : Expansion mode PF7 & PF6 : Port mode On-chip RAM access 0 1 Disable Enable 193 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11.1.3 Example of peripheral device connection In the µPD78C18/78C14/78C14A/78C12A/78C11A, a µPD8085 type bus system is used in which the data bus and low-order 8-bits of the address bus are multiplexed. Therefore, a large number of µPD8085 peripheral devices can be connected. When peripheral devices are connected, since the µPD78C18/78C14/78C14A/78C12A/78C11A has no I/O address space, memory mapped I/O must be used for all of them. The connection of typical peripheral devices is illustrated here. Figure 11-5 shows an example of a configuration in which external memory and a parallel interface unit (µPD71055) are connected. The memory maps for the µPD78C18/78C14/78C14A/78C12A/78C11A when set to the full expansion mode are shown in Figure 11-6 to 11-9. An example of the control program for the µPD71055 is shown below. PPIST ; LXI H, 0C03 H; Set base address MVI A, 1 0 0 0 0 0 1 1 B P23 to P20 Input P17 to P10 Input Mode 0 Selection P27 to P24 Output P07 to P00 Output Mode 0 Selection Mode selection STAX MVI STAX MVI MVI STAX ……… H A, 0F0H H A, 0C3H L, 00H H ; Port0 0C3H output (1C00H) ; (C000H) ; Port 2 0F0H output (1C02H) ; (C002H) ; Set control word (1C03H) ; (C003H) 194 Figure 11-5. µPD71055 Connection Diagram (Reference Diagram) VDD 87AD series µ PD71055 µ PD74HC139 PF7 MODE1 MODE0 PF6 B A G Y3 Y2 CS CHAPTER 11 VDD PF7-0 (AB15-8) ALE VDD AVDD VAREF PD7-0 (AD7-0) LE DI DO OE CE A14–0 CS A13–0 PF7 PD0 PD1 A0 A1 P07-P00 Port0 EXTERNAL DEVICE ACCESSES AND TIMINGS µ PD27C512Note 1 µ PD74HC573 OE O7–0 A15 µ PD43256Note 2 OE WE I/O8–1 A14 P17-P10 Port1 Standby control STOP D7-D0 RD VSS AVSS Notes 1. µPD27C512: 16K bytes used with µ PD78C14/78C14A, 24K bytes with µPD78C12A, 28K bytes with µPD78C11A. 2. µPD43256 : Only 16K bytes used WR VDD RD P27-P20 Port2 RESET WR VDD GND System reset System reset RESET 195 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Figure 11-6. Memory Map (µPD78C18) 0000H On-chip ROM 32K bytes 7FFFH 8000H External expansion RAM 16K bytes BFFFH C000H FBFFH FC00H FFFFH External expansion I/O On-chip RAMNote Note Can only be used when the RAE bit of the MM register is "1". Figure 11-7. Memory Map (µPD78C14/78C14A) 0000H On-chip ROM 16K bytes 3FFFH 4000H External expansion ROM 16K bytes 7FFFH 8000H External expansion ROM 16K bytes BFFFH C000H FEFFH FF00H FFFFH External expansion I/O On-chip RAMNote Note Can only be used when the RAE bit of the MM register is "1". 196 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Figure 11-8. Memory Map (µPD78C12A) 0000H On-chip ROM 8K bytes 1FFFH 2000H External expansion ROM 24K bytes 7FFFH 8000H External expansion RAM 16K bytes BFFFH C000H FEFFH FF00H FFFFH External expansion I/O On-chip RAMNote Note Can only be used when the RAE bit of the MM register is "1". Figure 11-9. Memory Map (µPD78C11A) 0000H On-chip ROM 4K bytes 1FFFH 1000H External expansion ROM 28K bytes 7FFFH 8000H External expansion RAM 16K bytes BFFFH C000H FEFFH FF00H FFFFH External expansion I/O On-chip RAM Note Note Can only used when the RAE bit of the MM register is "1". 197 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11.2 µPD78C17/78C10A External Device Access As the µPD78C17/78C10A have no on-chip ROM, it is possible to install an external device (program memory, data memory, or a peripheral device) in an external 63K byte area (0000H to FBFFH)/64K-byte area (0000H to FEFFH) in addition to on-chip RAM. The address space of an externally installed device is set by the MODE0 and MODE1 pins, with a choice of 4K bytes (addresses 0000H to 0FFFH), 16K bytes (addresses 0000H to 3FFFH), or 63K bytes (addresses 0000H to FBFFH)/64K bytes (addresses 0000H to FEFFH). Control Pins MODE1 MODE0 0 0 1 1 0 1 0 1 Operation Mode 4K-byte access 16K-byte access – 63K-byte access (µPD78C17 only) 64K-byte access (µPD78C10A only) External Address Area 4K bytes (addresses 0000H to 0FFFH) 16K bytes (addresses 0000H to 3FFFH) Setting Prohibited 63K bytes (addresses 0000H to FBFFH) On-Chip RAM Area Address FF00H to FFFFH Addresses FF00H to FFFFH Addresses FC00H to FFFFH 1 1 64K bytes (addresses 0000H to FEFFH) Addresses FF00H to FFFFH The external device is accessed using the RD, WR and ALE signals, with pins PD7 to PD0 functioning as a multiplexed address/data bus (AD7 to AD0) and pins PF7 to PF0 as an address bus (AB15 to AB8). When accessing a 4K-byte or 16K-byte area external device, pins PF7 to PF0 which are not used as address lines can be used as generalpurpose input/output port pins. The size of the external address space is determined by the setting of the MODE0 and MODE1 pins. 198 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11.2.1 MM register setting The low-order 3 bits of the µPD78C17/78C10A MM register should be set to "0". The RAE bit controls enabling and disabling of on-chip RAM accesses. When on-chip RAM is not used and that area is used by externally connected memory, the RAE bit should be set to "0" to disable on-chip RAM accesses. In normal operation, the RAE bit retains its current value when RESET signal is input. However, the RAE bit is undefined after a power-on reset, and must therefore be initialized by an instruction. Figure 11-10. MM Register Format (µPD78C17/78C10A) MM 
,
,  
, 
, 
, 3FFFH External device FC00H FFFFH On-chip RAM On-chip RAM On-chip RAM MODE0 = 0 MODE1 = 0 MODE0 = 1 MODE1 = 0 MODE0 = 1 MODE1 = 1



,,,,


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 , 
 ,, 7 – 6 – 5 – 4 – 3 2 0 1 0 0 0 RAE On-chip RAM access 0 1 Disable Enable Figure 11-11. µPD78C17 Address Space 16K-byte access 4K-byte access 63K-byte access 0000H 0000H 0000H External device 0FFFH External device 199 


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  ,, CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Figure 11-12. µPD78C10A Address Space 16K-byte access 4K-byte access 64K-byte access 0000H 0000H 0000H External device 0FFFH External device 3FFFH External device  
,
,    
,  
,  
, FF00H FFFFH On-chip RAM On-chip RAM On-chip RAM MODE0 = 0 MODE1 = 0 MODE0 = 1 MODE1 = 0 MODE0 = 1 MODE1 = 1 Cautions 1. Instructions on port D or port F must not be executed in the 64K-byte access mode, as this will result in an unpredictable operation. 2. A program which dynamically changes the port F input/output mode cannot be emulated by an emulator, and therefore should not be used. 3. A WR pulse is output if an output instruction is executed on port D or port F in the 64K-byte mode, and this must therefore on no account be performed. 4. With an emulator, the device may operate normally even if the RAE bit is not initialized by an instruction. 5. Overwriting the RAE bit during program execution allows an apparent increase of 256 bytes in the memory space. However, this operation cannot be emulated by an emulator, and should therefore not be performed. 200 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11.3 Timings µPD78C18 operation timings are shown in Figures 11-13 to 11-15. Three oscillator frequency cycles (from rise to fall) are defined as one state, represented by Tn. One machine cycle is completed in 3 states (9 clock cycles) for all normal read and write operations, but 4 states (12 clock cycles) are required for an OP code fetch. Wait states (TW) cannot be inserted. (1) OP code fetch timing (see Figure 11-13) This is the timing for fetching the OP (operation) code of all instructions, and consists of 4 states, T1 to T4. The two states T1 and T2 are used for the program memory read, and T3 and T4 are used for internal processing (decoding). The upper address signal from the low-order 8 bits of the external memory reference address is output to AB15 through AB8 (PF7 through PF0) from the start of T1 to the end of T4. AD7 to AD0 (PD7 to PD0) function as the multiplexed address/data bus: The low-order 8 bits of the external memory reference address are output during T1, and then AD7 to AD0 become high-impedance. Since the address information on the AD7 to AD0 bus is only output temporarily, it must be latched by the external device. In the 87AD series a special timing signal, ALE, is provided for latching AD7 to AD0. The ALE signal is output in the T1 state of each machine cycle. A low-level RD signal is output low from midway through the T1 state to the beginning of T4. (2) External device read timing (see Figure 11-14) The data read machine cycle when an external device reference instruction is executed consists of T1 to T3. Except for the absence of T4, the timing for AB15 to AB8 (PF7 to PF0), AD7 to AD0 (PD7 to PD0), and ALE is the same as an OP code fetch. A low-level RD signal is output from midway through T1 to the beginning of T3. (3) External device write timing (see Figure 11-15) The data write machine cycle when an external device reference instruction is executed consists of 3 states, T1 to T3. The address outputs (AB15 to AB8 and AD7 to AD0) and the ALE signal are the same as for the read timing machine cycle. The write data is output to AD7 through AD0 from the beginning of T2 to the end of T3. To enable writing to the addressed device, a low-level WR signal is output from midway through T1 to the beginning of T3. When PD7 to PD0 are set as the multiplexed address/data bus (AD7 to AD0) and PF7 to PF0 as the address bus (AB15 to AB8), both the RD signal and the WR signal become high in machine cycles in which the external device is not accessed. However, the ALE signal is output and the contents of the internal address bus are output directly to port D and port F. 201 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Figure 11-13. OP Code Fetch Timing T1 Oscillator frequency T2 T3 T4 ALE AB15-8 (PF7-0) AD7-0 (PD7-0) RD Address (lower) Address (upper) OP code Figure 11-14. External Device Read Timing T1 Oscillator frequency ALE AB15-8 (PF7-0) AD7-0 (PD7-0) RD Address (lower) T2 T3 Address (upper) Read data Figure 11-15. External Device Write Timing T1 Oscillator frequency ALE AB15-8 (PF7-0) AD7-0 (PD7-0) WR Address (lower) T2 T3 Address (upper) Write data 202 CHAPTER 12 PROM ACCESSES (µPD78CP18/78CP14 ONLY) The µPD78CP18 and µPD78CP14 incorporate 32K-byte and 16K-byte EPROM respectively. Four modes can be selected for the on-chip EPROM access range by means of bits MM5 to MM7 of the memory mapping register: • 4K-byte mode • 8K-byte mode • 16K-byte mode • 32K-byte modeNote : Access to addresses 0000H to 0FFFH (µPD78C11A mode) : Access to addresses 0000H to 1FFFH (µPD78C12A mode) : Access to addresses 0000H to 3FFFH (µPD78C14 mode) : Access to addresses 0000H to 7FFFH (µPD78C18 mode) Note The 32K-byte mode applies to the µPD78CP18 only. The configuration of the µPD78CP18/78C14 memory mapping registers is shown in Figures 12-1 and 12-2. (1) Bits MM0 to MM2 These bits control the PD7 to PD0 port/expansion mode and input/output specification, and the PF7 to PF0 address output specification. See 11.1.1 Memory mapping register (MM) for details. (2) MM3 bit (RAE) This bit controls enabling (RAE=1) and disabling (RAE=0) of on-chip RAM accesses. See 11.1.1 Memory mapping register (MM) for details. (3) Bits MM5 to MM7 These bits are used to specify the on-chip EPROM access range. When STOP or RESET is input, these bits are reset: The µPD78CP18 is set to the 32K-byte mode, and the µPD78CP14 to the 16K-byte mode. These bits are valid only in the µPD78CP18/78CP14/78CG14Note: If data is written to these bits in the µPD78C14/78C12A/78C11A, it is ignored by the CPU. Therefore, programs developed on the µPD78CP18/ 78CP14/78CG14 can be transferred directly to mask ROM. Note The µPD78CG14 is described in APPENDIX A INTRODUCTION TO PIGGYBACK PRODUCT. 203 CHAPTER 12 PROM ACCESSES (µPD78CP18/78CP14 ONLY) Figure 12-1. Memory Mapping Register Format (µPD78CP18) 7 6 5 4 – 3 2 1 0 MM7 MM6 MM5 RAE MM2 MM1 MM0 Port mode 0 0 0 PD7 to PD0 = Input port PF7 to PF0 = Port mode Single chip PD7 to PD0 = Output port PF7 to PF0 = Port mode 256 bytes PD7 to PD0 = Expansion mode PF7 to PF0 = Port mode PD7 to PD0  = Expansion mode  PF3 to PF0  PF7 to PF4 = Port mode 0 0 1 0 1 0 Expansion mode 1 0 0 4K bytes 1 1 0 16K bytes PD7 to PD0  = Expansion mode  PF5 to PF0  PF7 & PF6 = Port mode 1 1 1 31K/48K/56K/ 60K bytesNote PD7 to PD0  = Expansion mode  PF7 to PF0  Note Depending on bits MM7 to MM5 On-chip RAM access 0 1 Disable Enable On-chip PROM and on-chip RAM access ranges MM7 MM6 MM5 On-Chip PROM Access Range 0000H to 7FFFH (32K bytes: µ PD78C18 mode) 0000H to 3FFFH (16K bytes: µ PD78C14 mode) 0000H to 1FFFH (8K bytes: µ PD78C12A mode) 0000H to 0FFFH (4K bytes: µ PD78C11A mode) Setting prohibited On-Chip RAM Access Range 0 0 0 FC00H to FFFFH (1K bytes) 0 0 1 FF00H to FFFFH (256 bytes) 0 1 1 FF00H to FFFFH (256 bytes) 1 0 1 FF00H to FFFFH (256 bytes) Other than the above 204 CHAPTER 12 PROM ACCESSES (µPD78CP18/78CP14 ONLY) Figure 12-2. Memory Mapping Register Format (µPD78CP14) 7 6 5 – 4 – 3 2 1 0 MM7 MM6 RAE MM2 MM1 MM0 Port mode 0 0 0 PD7 to PD0 = Input port PF7 to PF0 = Port mode Single chip PD7 to PD0 = Output port PF7 to PF0 = Port mode 256 bytes PD7 to PD0 = Expansion mode PF7 to PF0 = Port mode PD7 to PD0  = Expansion mode  PF3 to PF0  PF7 to PF4 = Port mode 0 0 1 0 1 0 1 0 0 Expansion mode 4K bytes 1 1 0 16K bytes PD7 to PD0  = Expansion mode  PF5 to PF0  PF7 & PF6 = Port mode PD7 to PD0  = Expansion mode  PF7 to PF0  1 1 1 48K/56K/ 60K bytes Note Note Depending on setting of bits MM7 & MM6 On-chip RAM access 0 1 Disable Enable On-chip EPROM access Access to on-chip EPROM addresses 0000H to 3FFFH ( µPD78C14 mode) Access to on-chip EPROM addresses 0000H to 1FFFH ( µPD78C12A mode) Access to on-chip EPROM addresses 0000H to 0FFFH ( µPD78C11A mode) Setting prohibited 0 0 0 1 1 0 1 1 205 [MEMO] 206 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS (µPD78CP18/78CP14 ONLY) The µPD78CP18 and µPD78CP14 incorporate 32768 × 8-bit and 16384 × 8-bit PROM respectively as program memory. The pins shown in Table 13-1 are used for write/verify operations on this PROM. The µPD78CP18/78CP14 program timing is µPD27C256A compatible, and this chapter should be read in conjunction with documentation on the µPD27C256A. Table 13-1. Pin Functions in PROM Programming Pin Name RESET MODE0 MODE1 VPPNote1 CENote1 OENote1 A13 to A0Notes1, 2 Function Low-level input (in write/verify and read) High-level input (in write/verify and read) Low-level input (in write/verify and read) High-voltage input (in write/verify), high-level input (in read) Chip enable input Output enable input Address input Address input Low-level input (in write/verify and read) Data input (in write), data output (in verity/read) Power supply voltage input A14 to A0Notes1, 3 PF6Note2 O7-O0Note1 VDDNote1 Notes 1. These pins correspond to the µPD27C256A. 2. µPD78CP14 only 3. µPD78CP18 only Cautions 1. The µPD78CP18DW/78CP18KB/78CP14DW/78CP14KB/78CP14R, which are provided with an erase window, should be fitted with a light-protective cover film when EPROM erasure is not being performed. 2. The µPD78CP18CW/78CP18GF-3BE/78CP18GQ-36/78CP14CW/78CP14G-36/78CP14GF3BE/78CP14L one-time PROM products are not provided with an erase window, and thus UV erasure cannot be used on these devices. 207 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS (µPD78CP18/78CP14 ONLY) 13.1 PROM Programming Operating Modes The PROM programming operating mode is set as shown in table 13-2. Pins not used for programming should be connected as shown in Table 13-3. Table 13-2. PROM Programming Modes Operating Mode Program Program verify Program inhibit Read Output disable Standby CENote1 L H H L L H OENote1 H L H L H L/H +5 V +5 V VPPNote1 +12.5 V VDDNote1 +6 V RESET L MODE0 H MODE1 L PF6Note2 L Notes 1. These pins correspond to the µPD27C256A. 2. µPD78CP14 only Caution When VPP is set to +12.5 V and VDD to +6 V, driving CE and OE low is inhibited. Table 13-3. Recommended Connection of Unused Pins (In PROM Programming Mode) Pin Name INT1 X1 AN0 to AN7 VAREF AVDD AVSS Pins other than the above X2 Connect to VSS individually via a resistor Leave open Recommended Connection Connect to VSS 208 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS (µPD78CP18/78CP14 ONLY) 13.2 PROM Writing Procedure The procedure for writing data to the PROM is as shown below, allowing high-speed writing. (1) Connect unused pins to VSS with a pull-down resistor. Supply +6 V to the VDD pin and +12.5 V to the VPP pin. (2) Supply initial address. (3) Supply write data. (4) Supply a 1 ms program pulse (active low) to the CE pin. (5) Verify mode. If written, go to (7); if not written, repeat (3) through (5). If not written after 25 repetitions, go to (6). (6) Halt write operation due to defective device. (7) Supply write data and supply (times repeated in (3) through (5): ×) × 3 ms program pulse (additional write). (8) Increment address. (9) Repeat (3) through (8) up to final address. Figure 13-1. PROM Write/Verify Timing Repeat X times Write A14-10/PF6-2 A9/NMI A8/PF0 Verify Additional write Address (high-order 7 bits) A7-0/PA7-0 Address (low-order 8 bits) O7-0/PD7-0 Data input Data output Data input VPP VPP VIH VDD+1 VDD VDD VIH CE/PB6 VIL VIH OE/PB7 VIL 209 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS (µPD78CP18/78CP14 ONLY) 13.3 PROM Reading Procedure PROM contents can be read onto the external data bus (O7 to O0) using the following procedure. (1) Connect unused pins to GND with a pull-down resistor. (2) Supply 5 V to the VDD and VPP pins. (3) Input address of data to be read to pins A14 through A0. (4) Read mode. (5) Output data to pins O7 to O0. The timing for (2) to (5) above is shown in Figure 13-2. Figure 13-2. PROM Read Timing A14-10/PF6-2 A9/NMI A8/PF0 Address input CE/PB6 OE/PB7 O7-0/PD7-0 Data output 210 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS (µPD78CP18/78CP14 ONLY) 13.4 Erasure Procedure (Ceramic Package Products Only) The programmed data contents of the µPD78CP18DW/78CP18KB/78CP14DW/78CP14KB/78CP14R can be erased by exposure to ultraviolet radiation through the window in the top of the package. Erasure is possible using ultraviolet light with a wavelength of approximately 250 nm. The exposure required for complete erasure is 15 W .s/cm2 (UV intensity × erasure time). Using a commercially available UV lamp (254 nm wavelength, 12 m .W/cm2 intensity), erasure takes approximately 15 to 20 minutes. Cautions 1. Program contents may also be erased by extended exposure to direct sunlight or fluorescent light. The contents should therefore be protected by masking the window in the top of the package with light-shielding cover film. 2. Erasure should normally be carried out at a distance of 2.5 cm or less from the UV lamp. Remark The erasure time may be increased due to deterioration of the UV lamp or dirt on the package window. 13.5 One-Time PROM Products Screening One-time PROM products (µPD78CP18CW/78CP18GF-3BE/78CP18GQ-36/78CP14CW/78CP14G-36/78CP14GF3BE/78CP14L) can not be completely examined for shipment in NEC according to their structure matters. After needed data is written, screening, in which PROM verification is performed after high temperature storage based on the conditions below, is recommended. Storage Temperature 125 °C Storage Time 24 hours NEC performs fee-charged service, named "QTOPTM microcontroller", for one-time PROM writing, marking and screening including verification. For details, contact our salesman. 211 [MEMO] 212 CHAPTER 14 INSTRUCTION SET 14.1 Operand Notation and Description Method Operands are written in the operand field of an instruction in accordance with the description method for the operand notation for that instruction (For details, depends on assembler specifications). When there are several items listed under the description method, one of these is selected. Alphanumeric characters written in upper case and the symbols "–" and "+" are keywords, and are written in that form. The relevant numeric value or label is written as immediate data. 213 CHAPTER 14 INSTRUCTION SET Notation r r1 r2 sr sr1 sr2 sr3 sr4 rp rp1 rp2 rp3 rpa rpa1 rpa2 rpa3 wa word byte bit f irf V, A, B, C, D, E, H, L EAH, EAL, B, C, D, E, H, L A, B, C Description Method PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF, TXB, TM0, TM1, ZCM PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3 PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM ETM0, ETM1 ECNT, ECPT SP, B, D, H V, B, D, H, EA SP, B, D, H, EA B, D, H B, D, H, D+, H+, D–, H– B, D, H B, D, H, D+, H+, D–, H–, D+byte, H+A, H+B, H+EA, H+byte D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte 8-bit immediate data 16-bit immediate data 8-bit immediate data 3-bit immediate data CY, HC, Z NMINote, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB Note NMI can also be written as FNMI. Remark 1. sr~sr4 (special register) PA : PB : PC : PD : PF : MA : MB : MC : MCC : MF : MM : TM0 : TM1 : TMM : ETM0 : PORT A PORT B PORT C PORT D PORT F MODE A MODE B MODE C MODE CONTROL C MODE F MEMORY MAPPING TIMER REG0 TIMER REG1 TIMER MODE TIMER/EVENT COUNTER REG0 ETM1 : TIMER/EVENT COUNTER REG1 ECNT : TIMER/EVENT COUNTER UPCOUNTER ECPT : TIMER/EVENT COUNTER CAPTURE 2. rp~rp3 (register pair) 4. f(flag) CY HC Z : CARRY : HALF CARRY : ZERO ETMM : TIMER/EVENT SP : STACK POINTER COUNTER MODE B : BC EOM : TIMER/EVENT D : DE COUNTER OUTPUT H : HL MODE V : VA ANM : A/D CHANNEL EA : EXTENDED MODE ACCUMULATOR CR0 : A/D CONVERSION 3. rpa~rpa3 (rp addressing) CR3 : RESULT0~3 B : (BC) TXB : TX BUFFER D : (DE) RXB : RX BUFFER H : (HL) SMH : SERIAL MODE D+ : (DE)+ High H+ : (HL)+ SML : SERIAL MODE D– : (DE)– Low H– : (HL)– MKH : MASK High D++ : (DE)++ MKL : MASK Low H++ : (HL)++ ZCM : ZERO CROSS D+byte : (DE+byte) MODE H+A : (HL+A) H+B : (HL+B) H+EA : (HL+EA) H+byte : (HL+byte) 5. irf (interrupt flag) NMI FT0 FT1 F1 F2 FE0 FE1 FEIN FAD FSR FST ER OV AN4 : : : : : : : : : : : : : : NMI INPUT INTFT0 INTFT1 INTF1 INTF2 INTFE0 INTFE1 INTFEIN INTFAD INTFSR INTFST ERROR OVERFLOW ANALOG INPUT 4~7 ~ AN7 SB ~ : STANDBY 214 CHAPTER 14 INSTRUCTION SET 14.2 Explanation of Operation Code Symbols r R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 reg V A B C D E H L r1 T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 reg EAH EAL B C D E H L rpa A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 1 0 1 0 1 addressing (BC) (DE) (HL) (DE)+ (HL)+ (DE)– (HL)– (DE+byte) (HL+A) (HL+B) (HL+EA) (HL+byte) r2 r rpa1 rpa rpa2 sr S5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 sr3 U0 0 1 S4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 S3 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 S2 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 S1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 S0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Special-reg PA PB PC PD PF MKH MKL ANM SMH SML EOM ETMM TMM MM MCC MA MB MC MF TXB RXB TM0 TM1 CR0 CR1 CR2 CR3 ZCM sr4 V0 0 1 sr1 sr2 sr rpa3 C3 C2 00 00 01 01 10 11 11 11 11 C1 1 1 0 0 1 0 0 1 1 C0 0 1 0 1 1 0 1 0 1 addressing (DE) (HL) (DE)++ (HL)++ (DE+byte) (HL+A) (HL+B) (HL+EA) (HL+byte) Special-reg ETM0 ETM1 Special-reg ECNT ECPT irf I4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 I3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 I2 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 I0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 INTF NMI FT0 FT1 F1 F2 FE0 FE1 FEIN FAD FSR FST ER OV AN4 AN5 AN6 AN7 SB rp P2 0 0 0 0 1 P1 0 0 1 1 0 P0 0 1 0 1 0 reg-pair SP BC DE HL EA rp rp2 rp3 rp1 Q2 Q1 Q0 000 001 010 011 100 f reg-pair VA BC DE HL EA F2 0 0 0 1 F1 0 1 1 0 F0 0 0 1 0 flag – CY HC Z 215 CHAPTER 14 INSTRUCTION SET 14.3 Instruction Address Addressing The instruction address is determined by the contents of the program counter (PC), and is normally incremented (by one for each byte) automatically according to the number of instruction bytes fetched each time an instruction is executed. However, when an instruction associated with a branch is executed, the jump address information is loaded into the PC in accordance with the addressing methods shown below, and a jump is performed. 14.3.1 Register addressing The contents of the BC register pair or the EA accumulator are loaded into the PC and a jump is performed. This is performed when the following instructions are executed. JB CALB 7 B 07 C 0 15 PC 87 0 JEA 15 EA 87 0 15 PC 87 0 216 CHAPTER 14 INSTRUCTION SET 14.3.2 Immediate addressing The immediate data in the 2nd and 3rd bytes of the instruction is loaded into the PC and a jump is performed. This is performed when the following instructions are executed. JMP word . . CALL word CALF word In the case of the CALF instruction, the immediate data in the low-order 3 bits of the 1st byte and the 2nd byte is loaded into the PC. 7 CALL or JMP Low address High address 0 15 PC 87 0 7 CALF 32 faH faL 0 15 PC 11 10 87 0 00001 217 CHAPTER 14 INSTRUCTION SET 14.3.3 Direct addressing The contents of the memory addressed by the immediate data in the low-order 5 bits of the operation code are loaded into the PC and a jump is performed. This is performed when the following instruction is executed. CALT word 7654 Operation code 100 15 Effective address = 00000000 ta 87 65 10 ta 10 0 0 Effective address Effective address + 1 Memory Low address High address 15 PC 87 0 14.3.4 Relative addressing The result of adding the immediate data (displacement value: jdisp1) in the low-order 6 bits of the operation code to the start address of the next instruction is loaded into the PC and a jump is performed. The displacement value is handled as signed two's complement data (–32 to +31), with bit 5 as the sign bit. This is performed when the following instruction is executed. JR word 765 Operation code 1 1 jdisp1 0 15 PC + 1 + 15 X 6 54 S 0 0 15 PC S = 0: X = AII 0's S = 1: X = AII 1's 218        jdisp1 0 CHAPTER 14 INSTRUCTION SET 14.3.5 Extended relative addressing The result of adding the 9-bit immediate data (displacement value: jdisp) in the instruction to the start address of the next instruction is loaded into the PC and a jump is performed. The displacement value is handled as signed two's complement data (–256 to +255), with bit 8 (bit 0 of the 1st byte of the operation code) as the sign bit. This is performed when the following instruction is executed. JRE word 0 1 0 0 1 1 1 jH jdispL 15 PC + 2 + 15 X 987 S 0 0 15 PC S = 0: X = AII 0's S = 1: X = AII 1's              jdisp 0 219 CHAPTER 14 INSTRUCTION SET 14.4 Operand Address Addressing There are several methods (addressing methods), as described below, for specifying the register, memory etc. to be manipulated when executing an instruction. 14.4.1 Register addressing With this addressing method, the register to be manipulated is specified by the contents of the register specification code (R2R1R0, T2T1T0, S5S4S3S2S1S0, etc.) in the instruction. Register addressing is used when an instruction with the following operand formats is executed. In some cases an 8-bit register is specified, and in others a register pair (16 bits) is specified. Notation r r1 r2 sr sr1 sr2 sr3 sr4 rp rp1 rp2 rp3 f irf Description Method V, A, B, C, D, E, H, L EAH, EAL, B, C, D, E, H, L A, B, C PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF, TXB, TM0, TM1, ZCM PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3 PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM ETM0, ETM1 ECNT, ECPT SP, B, D, H V, B, D, H, EA SP, B, D, H, EA B, D, H CY, HC, Z NMINote, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB Note NMI can also be written as FNMI. 220 CHAPTER 14 INSTRUCTION SET Examples 1. MOV rl, A 7 Operation code 0 6 0 5 0 4 1 3 1 2 T2 1 T1 0 T0 If the E register is selected as r1, the instruction is written as shown below. The part after the semicolon (;) is a comment and has no effect on the operation of the instruction. MOV E, A; E ← A The corresponding operation code is shown below. Operation code 0 0 0 1 1 1 0 1 2. DCX rp Operation code 0 0 P1 P0 0 0 1 1 If the HL register pair selected as rp, the instruction is written as shown below. DCX H; HL ← HL – 1 The corresponding operation code is as shown below. Operation code 0 0 1 1 0 0 1 1 221 CHAPTER 14 INSTRUCTION SET 14.4.2 Register indirect addressing With this addressing method, the memory to be manipulated is addressed using the contents of the register pair specified by the register pair specification code (A3A2A1A0, C3C2C1C0) in the instruction as the operand address. Register indirect addressing is used when an instruction with the following operand formats is executed. Items with auto-increment/decrement, double auto-increment, base and base index functions are described separately. Notation rpa rpa1 rpa2 rpa3 Example 1. LDAX rpa2 Operation code A3 0 1 0 1 A2 A1 A0 Description Method B, D, H, D+, H+, D–, H– B, D, H B, D, H, D+, H+, D–, H–, D+byte, H+A, H+B, H+EA, H+byte D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte If the BC register pair is selected as rpa2, the instruction is written as shown below. LDAX B; A ← (BC) The corresponding operation code is shown below. Operation code 0 0 1 0 1 0 0 1 222 CHAPTER 14 INSTRUCTION SET 14.4.3 Auto-increment addressing This is a special mode of register indirect addressing using the HL and DE register pairs, in which, after the memory to be manipulated is addressed using the contents of the register pair specified by the addressing specification code (A3A2A1A0) in the instruction as the operand address, the contents of that register pair are automatically incremented by 1, thus preparing for the next addressing operation. Auto-increment addressing is used when an instruction with the following operand formats is executed. Notation rpa rpa2 Examples 1. STAX rpa2 Operation code A3 0 1 1 1 A2 A1 A0 Description Method D+, H+ D+, H+ If the auto-increment mode is selected for the DE register pair used as rpa2, the instruction is written as shown below. STAX D+; (DE) ← A, DE ← DE + 1 The corresponding operation code is shown below. Operation code 0 0 1 1 1 1 0 0 2. Execution of the BLOCK instruction Although not specified by an operand, when the BLOCK instruction is executed, the HL register pair is automatically selected as the source address register and the DE register pair as the destination address register. After the data transfer from the source address to the destination address has been performed, the HL and the DE register pairs are both automatically incremented by 1. BLOCK ; (DE) ← (HL), DE ← DE + 1, HL ← HL + 1 3. Execution of a return instruction on POP instruction Although not specified by an operand, when a return instruction or POP instruction which restores data saved to the stack area is executed, auto-incrementing of the stack pointer (SP) is performed. RET; PCL ← (SP), PCH ← (SP+1), SP ← SP + 2 223 CHAPTER 14 INSTRUCTION SET 14.4.4 Auto-decrement addressing This is a special mode of register indirect addressing using the HL and DE register pairs, in which, after the memory to be manipulated is addressed using the contents of the register pair specified by the addressing specification code (A3A2A1A0) in the instruction as the operand address, the contents of that register pair are automatically decremented by 1, thus preparing for the next addressing operation. Auto-decrement addressing is used when an instruction with the following operand formats is executed. Notation rpa rpa2 Description Method D–, H– D–, H– Examples 1. ADDX rpa Operation code 0 1 1 1 1 0 1 0 0 0 0 0 0 A2 A1 A0 If the auto-decrement mode is selected for the HL register pair used as rpa, the instruction is written as shown below. ADDX H–; A ← A + (HL), HL ← HL –1 The corresponding operation code is shown below. Operation code 0 1 2. 1 1 1 0 1 0 0 0 0 1 0 1 0 1 Interrupt generation or execution of a CALL instruction or PUSH instruction Although not specified by an operand, when an interrupt is generated or a CALL instruction or PUSH instruction is executed, in all of which cases register contents are stored in the stack, auto-decrementing of the stack pointer (SP) is performed. SOFTI ; (SP–1) ← PSW, (SP–2) ← PC+1H (SP–3) ← PC+1L, PC ← 0060H 224 CHAPTER 14 INSTRUCTION SET 14.4.5 Double auto-increment addressing This is a special mode of register indirect addressing using the HL and DE register pairs, which is effective for 16-bit data transfers between the extended accumulator (EA) and memory. With double auto-increment addressing, after the memory to be manipulated is addressed using the contents of the register pair specified by the addressing specification code (C3C2C1C0) in the instruction as the operand address, the contents of that register pair are automatically incremented by 2, thus preparing for the next addressing operation. Double auto-increment addressing is used when an instruction with the following operand format is executed. Notation rpa3 Example 1. Description Method D++, H++ STEAX rpa3 Operation code 0 1 1 0 0 0 0 1 1 0 0 0 C3 C2 C1 C0 If the double auto-increment mode is selected for the HL register pair used as rpa3, the instruction is written as shown below. STEAX H++; (HL) ← EAL, (HL+1) ← EAH, HL ← HL+2 The corresponding operation code is shown below. Operation code 0 1 1 0 0 0 0 1 1 0 0 1 0 0 0 1 225 CHAPTER 14 INSTRUCTION SET 14.4.6 Base addressing This is a special mode of register indirect addressing using the HL and DE register pairs, in which the memory to be manipulated is addressed using as the operand address the sum of the contents of the register pair (base register) specified by the addressing specification code (A3A2A1A0, C3C2C1C0) in the instruction, and the immediate data of the operand (displacement value). Base addressing is used when an instruction with the following operand formats is executed. The immediate data (displacement value) is handled as a non-negative number. Notation rpa2 rpa3 Example 1. STAX rpa2 Operation code A3 0 1 1 1 A2 A1 A0 Description Method D+byte, H+byte D+byte, H+byte Data If base addressing is selected using the sum of the HL register pair and 10H as rpa2, the instruction is written as shown below. STAX H + 10H; (HL + 10H) ← A Operation code 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 0 226 CHAPTER 14 INSTRUCTION SET 14.4.7 Base index addressing This is a special mode of register indirect addressing using the HL and DE register pairs, in which the memory to be manipulated is addressed using as the operand address the sum of the contents of the register pair (base register) specified by the addressing specification code (A3A2A1A0, C3C2C1C0) in the instruction, and a register (A, B, EA). Base index addressing is used when an instruction with the following operand formats is executed. The register A/B data is handled as a non-negative number. Notation rpa2 rpa3 Example 1. Description Method H+A, H+B, H+EA H+A, H+B, H+EA LDAX rpa2 Operation code A3 0 1 0 1 A2 A1 A0 If base index addressing is selected using the sum of the HL register pair and the B register as rpa2, the instruction is written as shown below. LDAX H + B; A ← (HL + B) The corresponding operation code is shown below. Operation code 1 0 1 0 1 1 0 1 227 CHAPTER 14 INSTRUCTION SET 14.4.8 Working register addressing With this addressing method, a working register in the memory area to be manipulated is selected with the working register vector register (V) as the high-order 8 bits of the address and the 8-bit immediate data in the instruction as the low-order 8 bits of the address. This kind of addressing combines register indirect addressing by the V register and direct addressing by the immediate data wa. Working register addressing is used when an instruction with the following operand format is executed. Notation wa Example 1. DCRW wa Operation code 0 0 1 1 0 0 0 0 Description Method Label, numeric value up to 8 bits Offset If 77H is specified as wa, the instruction is written as shown below. DCRW 77H The corresponding operation code is shown below. Operation code 0 0 0 1 1 1 1 1 0 0 0 1 0 1 0 1 If the contents of the V register are assumed to be 20H, the generated operand address will be 2077H, and the contents of the working register in that address will be decremented by 1. 228 CHAPTER 14 INSTRUCTION SET 14.4.9 Accumulator indirect addressing This is a special example of register indirect addressing in which the contents of the memory addressed by PC + 3 + A are loaded into the C register, and the contents of the memory addressed by PC + 3 + A + 1 are loaded into the B register. Accumulator indirect addressing is used when the TABLE instruction is executed. Example 1. Assuming the accumulator contents to be 0 and the PC contents to be 100H, the operation is as follows: TABLE; C ← (103H), B ← (104H) 14.4.10 Immediate addressing This addressing method has 1-byte operand data for manipulation in the operation code. Immediate addressing is used when an instruction with the following operand format is executed. Notation byte Example 1. Description Method Label, numeric value up to 8 bits ADI A, byte Operation code 0 1 0 0 0 1 1 0 Data If 79H is used as "byte", the instruction is written as shown below. ADI A, 79H; A ← A + 79H The corresponding operation code is shown below. Operation code 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 229 CHAPTER 14 INSTRUCTION SET 14.4.11 Extended immediate addressing This addressing method has 2-byte operand data for manipulation in the operation code. Extended immediate addressing is used when an instruction with the following operand format is executed. Notation word Example 1. Description Method Label, numeric value up to 16 bits LXI rp2, word Operation code 0 P2 P1 P0 0 1 0 0 Low byte High byte If HL is used as rp2 and 3F54H as "word", the instruction is written as shown below. LXI H, 3F54H; HL ← 3F54H The corresponding operation code is shown below. Operation code 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 230 CHAPTER 14 INSTRUCTION SET 14.4.12 Direct addressing With this addressing method, the memory to be manipulated is addressed using the immediate data in the instruction as the operand address. Direct addressing is used when an instruction with the following operand format is executed. Notation word Example 1. Description Method Label, numeric value up to 16 bits MOV r, word Operation code 0 0 1 1 1 1 1 0 0 1 0 0 0 R2 R1 R0 Low address High address If the B register is used as r and EEFFH as "word", the instruction is written as shown below. MOV B, 0EEFFH; The corresponding operation code is shown below. Operation code 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 1 0 231 CHAPTER 14 INSTRUCTION SET Example 2. SDED word Operation code 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 Low address High address If the label DST is used as "word", the instruction is written as shown below. SDED DST If DST is assumed to be 4000H, the corresponding operation code is as follows: Operation code 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 14.5 Number of States Required for Skipping The number in parentheses indicated in " Number of states" in the instruction set descriptions is the number of idle states consumed without any operation when that instruction is skipped. The number of idle states when the instruction is skipped is 4 in the case of the OP code and 3 in the case of immediate data. Example MVI sr2, byte instruction (3-byte instruction) 0 S3 1 0 1 0 0 0 0 0 1 S2 0 S1 0 S0 Data As the 1st and 2nd bytes are the OP code the number of idle states is 4, and as the 3rd byte is immediate data, the number of idle states is 3. Therefore, the number of idle states consumed when this instruction is skipped is 4 + 4 + 3 = 11. 232 CHAPTER 14 INSTRUCTION SET 14.6 Instruction Descriptions 14.6.1 8-bit data transfer instructions MOV r1, A (Move A to Register) Operation code : 0 1 0 0 1 1 T2 T1 T0 Number of bytes : Number of states : Function : 4 (4) r1 ← A Transfers the accumulator contents to register r1 (EAH, EAL, B, C, D, E, H, L) specified by T2T1T0 (0 to 7). When EAH is specified by r1 the contents are transferred to the high-order 8 bits of the extended accumulator, and when EAL is specified, to the low-order 8 bits. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MOV B, A; Transfer A to B. MOV A, r1 (Move Register to A) Operation code : 0 1 0 0 0 1 T2 T1 T0 Number of bytes : Number of states : Function : 4 (4) A ← r1 Transfers the contents of register r1 (EAH, EAL, B, C, D, E, H, L) specified by T2T1T0 (0 to 7) to the accumulator. When EAH is specified by r1 the contents of the high-order 8 bits of the extended accumulator are transferred to the accumulator, and when EAL is specified the low-order 8 bits of the extended accumulator are transferred. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MOV A, C; Transfer C to A. 233 CHAPTER 14 INSTRUCTION SET MOV sr, A (Move A to Special Register) Operation code : 0 1 1 1 0 S5 0 S4 1 S3 1 S2 0 S1 1 S0 Number of bytes : Number of states : Function : 2 10 (7) sr ← A Transfers the accumulator contents to the special register sr (PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF, TXB, TM0, TM1, ZCM) specified by S5S4S3S2S1S0 (0 to 3, 5 to D, 10 to 14, 17, 18, 1A, 1B, 28). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MOV PA, A; Transfer A to port A latch. MOV A, sr1 (Move Special Register to A) Operation code : 0 1 1 1 0 S5 0 S4 1 S3 1 S2 0 S1 0 S0 Number of bytes : Number of states : Function : 2 10 (7) A ← sr1 Transfers the contents of the special register sr1 (PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3) specified by S5S4S3S2S1S0 (0 to 3, 5 to 9, B, D, 19, 20 to 23) to the accumulator. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MOV A TMM; Transfer timer mode register contents to A. 234 CHAPTER 14 INSTRUCTION SET MOV r, word (Move Memory to Register) Operation code : 0 0 1 1 1 1 1 0 0 1 0 0 0 R2 R1 R0 Low address High address Number of bytes : Number of states : Function : 4 17 (14) r ← (word) Transfers the contents of the memory addressed by the 3rd byte (Low address) and 4th byte (High address) to the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MOV B, 89ABH; Transfer contents of address 89ABH to B. MOV word, r (Move Register to Memory) Operation code : 0 0 1 1 1 1 1 1 0 1 0 0 0 R2 R1 R0 Low address High address Number of bytes : Number of states : Function : 4 17 (14) (word) ← r Transfers the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) to the memory addressed by the 3rd byte (Low address) and 4th byte (High address). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MOV EXAM, A; Transfer A to memory addressed by label EXAM. 235 CHAPTER 14 INSTRUCTION SET MVI r, byte (Move Immediate to Register) Operation code : 0 1 1 0 1 R2 R1 R0 Data Number of bytes : Number of states : Function : 2 7 (7) r ← byte Transfers the immediate data in the 2nd byte (Data) to the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Has a stacking effect when A or L is specified as r. Flags affected : SK ← 0, L1 ← 1, L0 ← 0 (when r = A) SK ← 0, L1 ← 0, L0 ← 1 (when r = L) SK ← 0, L1 ← 0, L0 ← 0 (other cases) Example : MVI D, 0AFH; Load AFH into the D register. MVI sr2, byte (Move Immediate to Special Register) Operation code : 0 1 1 0 0 0 0 0 1 S2 0 S1 0 S0 S3 0 Data Number of bytes : Number of states : Function : 3 14 (11) sr2 ← byte Transfers the immediate data in the 3rd byte to the special register sr2 (PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM) specified by S3S2S1S0 (0 to 3, 5 to 9, B, D). Flags affected : SK ← 0, L1 ← 0, L0 ← 0 236 CHAPTER 14 INSTRUCTION SET MVIW wa, byte (Move Immediate to Working Register) Operation code : 0 1 1 1 0 0 0 1 Offset Data Number of bytes : Number of states : Function : 3 13 (10) (V.wa) ← byte Transfers the immediate data (Data) in the 3rd byte to the working register addressed by the V register (specifying the high-order 8 bits of the memory address) and the 2nd byte (specifying the low-order 8 bits). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MVIV, 00H, 20H; Store 20H in working register in address 4000H. MVIX rpa1, byte (Move Immediate to Memory addressed by Register Pair) Operation code : 0 1 0 0 1 0 A1 A0 Data Number of bytes : Number of states : Function : 2 10 (7) (rpa1) ← byte Transfers the immediate data (Data) in the 2nd byte to the memory addressed by the register pair rpa1 (BC, DE, HL) specified by A1A0 (1 to 3). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MVIX B, 00H; Store 0 in memory addressed by the BC register pair. 237 CHAPTER 14 INSTRUCTION SET STAW wa (Store A to Working Register) Operation code : 0 1 1 0 0 0 1 1 Offset Number of bytes : Number of states : Function : 2 10 (7) (V. wa) ← A Stores the accumulator contents in the working register addressed by the V register (specifying the highorder 8 bits of the memory address) and the 2nd byte (specifying the low-order 8 bits). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 MVI V, 0EEH STAW 0FFH ; Store A in address EEFFH. LDAW wa (Load A With Working Register) Operation code : 0 0 0 0 0 0 0 1 Offset Number of bytes : Number of states : Function : 2 10 (7) A ← (V. wa) Loads the contents of the working register addressed by the V register (specifying the high-order 8 bits of the memory address) and the 2nd byte (specifying the low-order 8 bits) into the accumulator. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 238 CHAPTER 14 INSTRUCTION SET STAX rpa2 (Store A to Memory addressed by Register Pair) Operation code : A3 0 1 1 1 A2 A1 A0 Data Number of bytes/states: The number of bytes and number of states are as shown below, depending on the rpa2 specification. rpa2 Number of bytes Number of states (rpa2) ← A B D H D+ H+ D– H– 1 7 (4) D+byte 2 H+A H+B 1 13 (7) H+EA H+byte 2 Function : Stores the accumulator contents in the memory addressed by the register pair rpa2 (BC, DE, HL, DE+, HL+, DE–, HL–, DE+byte, HL+A, HL+B, HL+EA, HL+byte) specified by A3A2A1A0 (1 to 7, B to F). If auto-increment/ auto-decrement is specified, the contents of the register pair (DE or HL) are automatically incremented or decremented by 1 after the accumulator contents have been stored. If DE+byte or HL+byte is specified as rpa2, the memory is addressed by the result of adding the 2nd byte (Data) of the instruction to the contents of DE/HL. If HL+A, HL+B, or HL+EA is specified, the memory is addressed by the result of adding the contents of the register (A, B, EA) to the contents of HL. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 LXI … STAX STAX D, 4000H ; DE ← 4000H D+ D+10H ; (4000H) ← A, DE ← 4001H ; (4011H) ← A, DE ← 4001H This example stores A in addresses 4000H and 4011H. 239 CHAPTER 14 INSTRUCTION SET LDAX rpa2 (Load A with Memory addressed by Register Pair) Operation code : A3 0 1 0 1 A2 A1 A0 Data Number of bytes/states: The number of bytes and number of states are as shown below, depending on the rpa2 specification. rpa2 Number of bytes Number of states A ← (rpa2) B D H D+ H+ D– H– 1 7 (4) D+byte 2 H+A H+B 1 13 (7) H+EA H+byte 2 Function : Loads the contents of the memory addressed by the register pair rpa2 (BC, DE, HL, DE+, HL+, DE–, HL–, DE+byte, HL+A, HL+B, HL+EA, HL+byte) specified by A3A2A1A0 (1 to 7, B to F) into the accumulator. If auto-increment/auto-decrement is specified, the contents of the register pair (DE or HL) are automatically incremented or decremented by 1 after the accumulator has been loaded. If DE+byte or HL+byte is specified as rpa2, the memory is addressed by the result of adding the 2nd byte (Data) of the instruction to the contents of DE/HL. If HL+A, HL+B, or HL+EA is specified, the memory is addressed by the result of adding the contents of the register (A, B, EA) to the contents of HL. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 LXI … MVI LDAX H, 4000H ; HL ← 4000H B, 20H H+B ; B ← 20H ; A ← (4020H) This example loads the contents of address 4020H into A. EXX (Exchange Register Sets) Operation code : 0 1 0 0 1 0 0 0 1 Number of bytes : Number of states : Function Flags affected : : 4 (4) B → B', C →C', D →D', E →E', H →H', L →L' ← ← ← ← ← ← SK ← 0, L1 ← 0, L0 ← 0 Exchanges the contents of registers B, C, D, E, H, L with the contents of registers B', C', D', E', H', L'. 240 CHAPTER 14 INSTRUCTION SET EXA (Exchange V, A, EA and V', A', EA') Operation code : 0 1 0 0 1 0 0 0 0 Number of bytes : Number of states : Function : 4 (4) V → V', A → A', EA →EA' ← ← ← Exchanges the contents of V and A registers and EA with the contents of the V' and A' registers and EA'. : SK ← 0, L1 ← 0, L0 ← 0 Flags affected EXH (Exchange HL and H'L') Operation code : 0 1 1 0 1 0 0 0 0 Number of bytes : Number of states : Function Flags affected : : 4 (4) H → H', L → L' ← ← SK ← 0, L1 ← 0, L0 ← 0 Exchanges the contents of H and L registers with the contents of the H' and L' registers. BLOCK (Block Data Transfer) Operation code : 0 1 0 1 1 0 0 0 1 Number of bytes : Number of states : Function : 13 × (C+1), (4) (DE) ← (HL), DE ← DE+1, HL ← HL+1, C ← C–1, end if borrow. Performs a block transfer to the memory addressed by the DE register pair comprising the number of bytes specified by the C register used as a counter (C register value +1) of the contents of the memory addressed by the HL register pair. Each time a byte is transferred, HL and DE are auto-incremented and the C register is decremented. When the C register value reaches FFH, the instruction is terminated and the program moves on to the next instruction. Interrupts can be acknowledged during repeated transfers by means of a BLOCK instruction, in which case the transfer continues after returning from the interrupt service routine. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 241 CHAPTER 14 INSTRUCTION SET 14.6.2 16-bit data transfer instructions DMOV rp3, EA (Move EA to Register Pair) Operation code : 1 1 0 1 1 0 1 P1 P0 Number of bytes : Number of states : Function : 4 (4) rp3L ← EAL, rp3H ← EAH Transfers the contents of the lower half (EAL) of the extended accumulator to the lower register (C, E, L) of the register pair rp3 (BC, DE, HL) specified by P1P0 (1 to 3), and the contents of the upper half (EAH) to the upper register (B, D, H) of the register pair. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 DMOV B, EA; C ← EAL, B ← EAH DMOV EA, rp3 (Move Register Pair to EA) Operation code : 1 1 0 1 0 0 1 P1 P0 Number of bytes : Number of states : Function : 4 (4) EAL ← rp3L, EAH ← rp3H Transfers the contents of the lower register (C, E, L) of the register pair rp3 (BC, DE, HL) specified by P1P0 (1 to 3) to the lower half (EAL) of the extended accumulator, and the contents of the upper register (B, D, H) of the register pair to the upper half (EAH). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 DMOV EA, B; EAL ← C, EAH ← B DMOV sr3, EA (Move EA to Special Register) Operation code : 0 1 1 1 0 0 0 1 1 0 0 0 0 1 0 U0 Number of bytes : Number of states : Function 1). Flags affected Example : : : 2 14 (8) sr3 ← EA Transfers the extended accumulator contents to the special register sr3 (ETM0, ETM1) specified by U0 (0, SK ← 0, L1 ← 0, L0 ← 0 DMOV ETM0, EA; Transfer EA to ETM0. 242 CHAPTER 14 INSTRUCTION SET DMOV EA, sr4 (Move Special Register to EA) Operation code : 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 V0 Number of bytes : Number of states : Function Flags affected : : 2 14 (8) EA ← sr4 SK ← 0, L1 ← 0, L0 ← 0 Transfers the contents of the special register sr4 (ECNT, ECPT) specified by V0 (0, 1) to the extended accumulator. SBCD word (Store B&C Direct) Operation code : 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 Low address High address Number of bytes : Number of states : Function : 4 20 (14) (word) ← C, (word+1) ← B Stores the contents of the C register in the memory addressed by the 3rd byte (lower address) and 4th byte (upper address), and stores the contents of the B register in the next memory address. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 SBCD 4000H; Store C register contents in address 4000H, and store B register ; contents in address 4001H. SDED word (Store D&E Direct) Operation code : 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 Low address High address Number of bytes : Number of states : Function : 4 20 (14) (word) ← E, (word+1) ← D Stores the contents of the E register in the memory addressed by the 3rd byte (lower address) and 4th byte (upper address), and stores the contents of the D register in the next memory address. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 243 CHAPTER 14 INSTRUCTION SET SHLD word (Store H&L Direct) Operation code : 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 Low address High address Number of bytes : Number of states : Function : 4 20 (14) (word) ← L, (word+1) ← H Stores the contents of the L register in the memory addressed by the 3rd byte (lower address) and 4th byte (upper address), and stores the contents of the H register in the next memory address. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 SSPD word (Store SP Direct) Operation code : 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 Low address High address Number of bytes : Number of states : Function : 4 20 (14) (word) ← SPL, (word+1) ← SPH Stores the low-order 8 bits (SPL) of the stack pointer in the memory addressed by the 3rd byte (lower address) and 4th byte (upper address), and stores the high-order 8 bits (SPH) in the next memory address. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 244 CHAPTER 14 INSTRUCTION SET STEAX rpa3 (Store EA to Memory addressed by Register Pair) Operation code : 0 1 1 0 0 0 0 1 1 0 0 0 C3 C2 C1 C0 Data Number of bytes/states: The number of bytes and number of states are as shown below, depending on the rpa3 specification. rpa3 Number of bytes Number of states D H D++ 2 14 (8) (rpa3) ← EAL, (rpa3+1) ← EAH H++ D+byte 3 H+A H+B 2 20 (11) H+EA H+byte 3 Function : Stores the contents of the low-order 8 bits (EAL) of the extended accumulator in the memory addressed by the register pair rpa3 (DE, HL, DE++, HL++, DE+byte, HL+A, HL+B, HL+EA, HL+byte) specified by C3C2C1C0 (2 to 5, B to F), and stores the contents of the high-order 8 bits (EAH) in the memory addressed by rpa3 + 1. If DE+byte or HL+byte is specified as rpa3, memory is addressed by the result of adding the 3rd byte (Data) of the instruction to the contents of DE/HL. If HL+A, HL+B, or HL+EA is specified, the memory is addressed by the result of adding the contents of the register (A, B, EA) to the contents of HL. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 LXI D, 4000H ; DE ← 4000H ; (4000H) ← EAL, (4001H) ← EAH ; DE ← 4002H STEAX D+10H ; (4012H) ← EAL, (4013H) ← EAH ; DE=4002H This example stores the low-order 8 bits (EAL) of the extended accumulator in address 4000H and address 4012H, and stores the high-order 8 bits (EAH) in address 4001H and address 4013H. STEAX D++ 245 CHAPTER 14 INSTRUCTION SET LBCD word (Load B&C Direct) Operation code : 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 Low address High address Number of bytes : Number of states : Function : 4 20 (14) C ← (word), B ← (word+1) Loads the contents of the memory addressed by the 3rd byte (lower address) and 4th byte (upper address) into the C register, and loads the contents of the next memory address into the B register. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 LDED word (Load D&E Direct) Operation code : 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 1 Low address High address Number of bytes : Number of states : Function : 4 20 (14) E ← (word), D ← (word+1) Loads the contents of the memory addressed by the 3rd byte (lower address) and 4th byte (upper address) into the E register, and loads the contents of the next memory address into the D register. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 246 CHAPTER 14 INSTRUCTION SET LHLD word (Load H&L Direct) Operation code : 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 Low address High address Number of bytes : Number of states : Function : 4 20 (14) L ← (word), H ← (word+1) Loads the contents of the memory addressed by the 3rd byte (lower address) and 4th byte (upper address) into the L register, and loads the contents of the next memory address into the H register. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 LSPD word (Load SP Direct) Operation code : 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 Low address High address Number of bytes : Number of states : Function : 4 20 (14) SPL ← (word), SPH ← (word+1) Loads the contents of the memory addressed by the 3rd byte (lower address) and 4th byte (upper address) into the low-order 8 bits (SPL) of the stack pointer, and loads the contents of the next memory address into the high-order 8 bits (SPH). Flags affected : SK ← 0, L1 ← 0, L0 ← 0 247 CHAPTER 14 INSTRUCTION SET LDEAX rpa3 (Load EA with Memory addressed by Register Pair) Operation code : 0 1 1 0 0 0 0 0 1 0 0 0 C3 C2 C1 C0 Data Number of bytes/states: The number of bytes and number of states are as shown below, depending on the rpa3 specification. rpa3 Number of bytes Number of states D H D++ 2 14 (8) EAL ← (rpa3), EAH ← (rpa3+1) H++ D+byte 3 H+A H+B 2 20 (11) H+EA H+byte 3 Function : Loads the contents of the memory addressed by the register pair rpa3 (DE, HL, DE++, HL++, DE+byte, HL+A, HL+B, HL+EA, HL+byte) specified by C3C2C1C0 (2 to 5, B to F) into the low-order 8 bits (EAL) of the extended accumulator, and loads the contents of the memory addressed by rpa3+1 into the high-order 8 bits (EAH). If DE+byte or HL+byte is specified as rpa3, the memory is addressed by the result of adding the 3rd byte (Data) of the instruction to the contents of DE/HL. If HL+A, HL+B, or HL+EA is specified, the memory is addressed by the result of adding the contents of the register (A, B, EA) to the contents of HL. Flags affected : SK ← 0, L1 ← 0, L0 ← 0 248 CHAPTER 14 INSTRUCTION SET PUSH rp1 (Push Register Pair on Stack) Operation code : 1 1 0 1 1 0 Q2 Q1 Q0 Number of bytes : Number of states : Function : 13 (4) (SP–1) ← rp1H, (SP–2) ← rp1L, SP ← SP–2 Saves the upper half (V, B, D, H, EAH) of the register pair rp1 (VA, BC, DE, HL) or extended accumulator specified by Q2Q1Q0 (0 to 4) to the stack memory addressed by (SP–1), and saves the lower half (A, C, E, L, EAL) to the stack memory addressed by (SP–2). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 PROGRAM START LXI SP, 0E000H ; INTERRUPT ROUTINE PUSH V PUSH B PUSH D PUSH H PUSH EA POP EA POP H POP D POP B POP V EI RETI … … Stack             Stack contents when PUSH EA  is executed           DFF6H DFF7H DFF8H DFF9H DFFAH DFFBH DFFCH DFFDH DFFEH DFFFH EAL EAH L H E D C B A V 249 CHAPTER 14 INSTRUCTION SET POP rp1 (Pop Register Pair off Stack) Operation code : 1 1 0 1 0 0 Q2 Q1 Q0 Number of bytes : Number of states : Function : 10 (4) rp1L ← (SP), rp1H ← (SP+1), SP ← SP+2 Restores the contents of the stack memory addressed by (SP) to the lower half (A, C, E, L, EAL) of the register pair rp1 (VA, BC, DE, HL) or extended accumulator specified by Q2Q1Q0 (0 to 4), and restores the contents of the stack memory addressed by (SP+1) to the upper half (V, B, D, H, EAH). Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 PUSH B PUSH D POP D POP B As the stack pointer indicates the last stack address saved to, the POP instruction restores items in the reverse order from that used in the PUSH instruction. … LXI rp2, word (Load Register Pair with Immediate) Operation code : 0 P2 P1 P0 0 1 0 0 Low byte High byte Number of bytes : Number of states : Function : 3 10 (10) rp2 ← word Loads the 2nd byte into the low-order 8 bits (SPL) of the SP or the lower half (C, E, L, EAL) of the register pair rp2 (BC, DE, HL) or extended address specified by P2P1P0 (0 to 4), and loads the 3rd byte into the upper half (SPH, B, D, H, EAH). A stacking effect is produced when HL is specified as the register pair. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 1 (when rp2 = HL) SK ← 0, L1 ← 0, L0 ← 0 (other cases) LXI B, 4000H; Load 40H into B register and 00H into C register. 250 CHAPTER 14 INSTRUCTION SET TABLE (Table pick up) Operation code : 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 Number of bytes : Number of states : Function : 2 17 (8) C ← (PC+3+A), B ← (PC+3+A+1) Loads the table contents addressed by PC+3+A into the C register, and loads the table contents addressed by PC+3+A+1 into the B register. Flags affected Example : : SK ← 0, L1 ← 0, L0 ← 0 TB0 : MVI TB1 : MVI TB2 : MVI SLL PC TABLE PC+2 JB PC + 3 PC + 4 PC + 5 PC + 6 PC + 7 PC + 8 A, 0 ; A=0 A, 1 ; A=1 A, 2 ; A=2 A ; Shift Logical Left Accumulator ; BC ← (TABLE) ; PC ← BC   A=0    A=1    A=2  251 CHAPTER 14 INSTRUCTION SET 14.6.3 8-bit operation instructions (Register) ADD A, r (Add Register to A) Operation code : 0 1 1 1 1 0 0 0 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A ← A+r Adds the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) to the contents of the accumulator, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY ADD A, C; Add A and C registers and store result in A. ADD r, A (Add A to Register) Operation code : 0 0 1 1 1 0 0 0 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r ← r+A Adds the contents of the accumulator to the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the specified register. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY ADD B, A; Add B and A registers and store the result in B. ADC A, r (Add Register to A with Carry) Operation code : 0 1 1 1 1 0 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A ← A+r+CY Adds the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) to the contents of the accumulator including the CY flag, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY ADC A, E; A ← A+E+CY 252 CHAPTER 14 INSTRUCTION SET ADC r, A (Add A to Register with Carry) Operation code : 0 0 1 1 1 0 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r ← r+A+CY Adds the contents of the accumulator to the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) including the CY flag, and stores the result in the specified register. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY Add the register pairs HL and DE, and store the result in HL: MOV ADD MOV ADC A, E L, A A, D H, A ; ; ; ; A←E L ← L+A A←D H ← H+A+CY ADDNC A, r (Add Register to A. Skip if No Carry) Operation code : 0 1 1 0 1 1 0 0 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A ← A+r; Skip if no carry. Adds the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), to the contents of the accumulator, and stores the result in the accumulator. Skips if no carry is generated as a result of the addition. Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY ADDNC A, V; A ← A+V A skip is performed if no carry is generated as a result of the addition. 253 CHAPTER 14 INSTRUCTION SET ADDNC r, A (Add A to Register. Skip if No Carry) Operation code : 0 0 1 0 1 1 0 0 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r ← r+A; Skip if no carry. Adds the contents of the accumulator to the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the specified register. Skips if no carry is generated as a result of the addition. Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY Add A to the HL register pair. ADDNC L, A; L ← L+A, SKIP IF NO CARRY. ADI H, I; H ← H+1 If no carry is generated a skip is performed and the addition ends; if a carry is generated, the carry is added to the upper byte and the addition ends. SUB A, r (Subtract Register from A) Operation code : 0 1 1 1 1 1 0 0 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A←A←r Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) from the contents of the accumulator, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY SUB A, B; A ← A–B 254 CHAPTER 14 INSTRUCTION SET SUB r, A (Subtract A from Register) Operation code : 0 0 1 1 1 1 0 0 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r ← r–A Subtracts the contents of the accumulator from the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the specified register. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY SUB A, A; A ← A–A=0 This operation clears the HC and CY flags and sets the Z flag. SBB A, r (Subtract Register from A with Borrow) Operation code : 0 1 1 1 1 1 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A ← A–r–CY Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) including the CY flag from the contents of the accumulator, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY SBB A, L; A ← A–L–CY SBB r, A (Subtract A from Register with Borrow) Operation code : 0 0 1 1 1 1 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r ← r–A–CY Subtracts the contents of the accumulator including the CY flag from the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the specified register. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY SBB B, A; B ← B–A–CY 255 CHAPTER 14 INSTRUCTION SET SUBNB A, r (Subtract Register from A. Skip if No Borrow) Operation code : 0 1 1 0 1 1 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A ← A–r; Skip if no borrow. Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) from the contents of the accumulator, and stores the result in the accumulator. Skips if no borrow is generated as a result of the subtraction. Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY SUBNB A, D; A ← A–D A skip is performed if no borrow is generated as a result of the subtraction. SUBNB r, A (Subtract A from Register. Skip if No Borrow) Operation code : 0 0 1 0 1 1 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r ← r–A; Skip if no borrow. Subtracts the contents of the accumulator from the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the specified register. Skips if no borrow is generated as a result of the subtraction. Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY To subtract A from the HL register pair. SUBNB SUI L, A; L ← L–A, SKIP IF NO BORROW. H, I; H ← H–1 256 CHAPTER 14 INSTRUCTION SET ANA A, r (And Register with A) Operation code : 0 1 1 0 1 0 0 0 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A←A r Obtains the logical product of the contents of the accumulator and the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 ANA A, L; A ← A L ANA r, A (And A with Register) Operation code : 0 0 1 0 1 0 0 0 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r←r A Obtains the logical product of the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) and the contents of the accumulator, and stores the result in the specified register. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 ANA H, A; H ← H A ORA A, r (Or Register with A) Operation code : 0 1 1 0 1 0 0 1 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A←A r Obtains the logical sum of the contents of the accumulator and the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 ORA A, H; A ← A H 257 CHAPTER 14 INSTRUCTION SET ORA r, A (Or A with Register) Operation code : 0 0 1 0 1 0 0 1 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r←r A Obtains the logical sum of the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and the contents of the accumulator, and stores the result in the specified register. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 ORA L, A; L ← L A XRA A, r (Exclusive-Or Register with A) Operation code : 0 1 1 0 1 0 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A←A r Obtains the exclusive logical sum of the contents of the accumulator and the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 XRA A, B; A ← A B XRA r, A (Exclusive-Or A with Register) Operation code : 0 0 1 0 1 0 0 1 0 0 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r←r A Obtains the exclusive logical sum of the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) and the contents of the accumulator, and stores the result in the specified register. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 XRA C, A; C ← C A 258 CHAPTER 14 INSTRUCTION SET GTA A, r (Greater Than Register) Operation code : 0 1 1 0 1 1 0 0 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A–r–1 ← Skip if no borrow. Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) and 1 from the contents of the accumulator. Skips if no borrow is generated as a result of the subtraction (A > r). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY GTA A, B; A–B–1 A skip is performed if A is greater than B. GTA r, A (Greater Than A) Operation code : 0 0 1 0 1 1 0 0 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r–A–1 ← Skip if no borrow. Subtracts the contents of the accumulator and 1 from the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Skips if no borrow is generated as a result of the subtraction (r > A). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY GTA B, A; B–A–1 A skip is performed if B is greater than A. 259 CHAPTER 14 INSTRUCTION SET LTA A, r (Less Than Register) Operation code : 0 1 1 0 1 1 0 1 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A–r; Skip if borrow. Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) from the contents of the accumulator. Skips if a borrow is generated as a result of the subtraction (A < r). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY LTA A, L; A–L A skip is performed if A is less than the L register. LTA r, A (Less Than A) Operation code : 0 0 1 0 1 1 0 1 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r–A; Skip if borrow. Subtracts the contents of the accumulator from the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Skips if a borrow is generated as a result of the subtraction (r < A). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY LTA H, A; H–A A skip is performed if the H register is less than A. 260 CHAPTER 14 INSTRUCTION SET NEA A, r (Not Equal Register with A) Operation code : 0 1 1 1 1 1 0 0 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A–r; Skip if no zero. Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) from the contents of the accumulator. Skips if the result of the subtraction is not zero (A ≠ r). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY NEA A, B; SKIP IF A ≠ B If A < B the CY flag is set; if A = B the Z flag is set. NEA r, A (Not Equal A with Register) Operation code : 0 0 1 1 1 1 0 0 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r–A; Skip if no zero. Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7), Skips if the result of the subtraction is not zero (r ≠ A). Flags affected Example : : Z, SK, HC, L1← 0, L0 ← 0, CY NEA C, A; SKIP IF C ≠ A If C < A the CY flag is set; if C = A the Z flag is set. EQA A, r (Equal Register with A) Operation code : 0 1 1 1 1 1 0 1 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A–r; Skip if zero. Subtracts the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7) from the contents of the accumulator. Skips if the result of the subtraction is zero (A = r). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY EQA A, D; SKIP IF A = D 261 CHAPTER 14 INSTRUCTION SET EQA r, A (Equal A with Register) Operation code : 0 0 1 1 1 1 0 1 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) r–A; Skip if zero. Subtracts the contents of the accumulator from the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Skips if the result of the subtraction is zero (r = A). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY EQA E, A; SKIP IF E = A ONA A, r (On-Test Register with A) Operation code : 0 1 1 1 1 0 0 0 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A r; Skip if no zero. Obtains the logical product of the contents of the accumulator and the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Skips if the logical product is not zero. Flags affected : Z, SK, L1 ← 0, L0 ← 0 OFFA A, r (Off-Test Register with A) Operation code : 0 1 1 1 1 0 0 1 0 1 0 0 0 R2 R1 R0 Number of bytes : Number of states : Function : 2 8 (8) A r; Skip if zero. Obtains the logical product of the contents of the accumulator and the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Skips if the logical product is zero. Flags affected : Z, SK, L1 ← 0, L0 ← 0 262 CHAPTER 14 INSTRUCTION SET 14.6.4 8-bit operation instructions (Memory) ADDX rpa (Add Memory addressed by Register Pair to A) Operation code : 0 1 1 1 1 0 1 0 0 0 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A ← A + (rpa) Adds the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+ DE–, HL–) specified by A2A1A0 (1 to 7) to the contents of the accumulator, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY MOV LXI ADDX A, 4000H H ; A ← (4000H) ; A ← A+(HL) H, 4200H ; HL ← 4200H This example adds together the contents of address 4000H and address 4200H. ADCX rpa (Add Memory addressed by Register Pair to A with Carry) Operation code : 0 1 1 1 1 0 1 1 0 0 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A ← A+(rpa)+CY Adds the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7) to the contents of the accumulator including the CY flag, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY ADCX D+; A ← A + (DE) + CY, DE ← DE + 1 This example adds the contents of the memory addressed by the DE register pair to A and stores the result in A, and then increments DE. 263 CHAPTER 14 INSTRUCTION SET ADDNCX rpa (Add Memory addressed by Register Pair to A. Skip if No Carry) Operation code : 0 1 1 0 1 1 1 0 0 0 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A ← A + (rpa); Skip if no carry. Adds the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7) and the contents of the accumulator, and stores the result in the accumulator. Skips if no carry is generated as a result of the addition. Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY LXI LXI MOV ADDNCX STAX JMP H, 4200H ; HL ← 4200H D, 4000H ; DE ← 4000H A, 4100H ; A ← (4100H) D+ H MOTOE ; A ← A+(DE), DE ← DE+1 ; (HL) ← A This example adds together the contents of address 4100H and address 4000H, and stores the result in address 4200H if no carry is generated. If a carry is generated, the STAX instruction is skipped and the JMP instruction is executed to jump to MOTOE. SUBX rpa (Subtract Memory addressed by Register Pair from A) Operation code : 0 1 1 1 1 1 1 0 0 0 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A ← A–(rpa) Subtracts the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7) from the contents of the accumulator, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY SUBX D; A ← A–(DE) 264 CHAPTER 14 INSTRUCTION SET SBBX rpa (Subtract Memory addressed by Register Pair from A) Operation code : 0 1 1 1 1 1 1 1 0 0 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A ← A–(rpa)–CY Subtracts the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7) including the CY flag from the contents of the accumulator, and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, HC, L1 ← 0, L0 ← 0, CY SBBX D–; A ← A–(DE)–CY, DE ← DE–1 This example subtracts the contents of the memory addressed by the DE register pair including the CY flag from A and stores the result in A, and then decrements DE. SUBNBX rpa (Subtract Memory addressed by Register Pair from A. Skip if No Borrow) Operation code : 0 1 1 0 1 1 1 1 0 0 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A ← A–(rpa); Skip if no borrow. Subtracts the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7) from the contents of the accumulator, and stores the result in the accumulator. Skips if no borrow is generated as a result of the subtraction. Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY SUBNBX B; A ← A–(BC) A skip is performed if no borrow is generated as a result of the subtraction. 265 CHAPTER 14 INSTRUCTION SET ANAX rpa (And Memory addressed by Register Pair with A) Operation code : 0 1 1 0 1 0 1 0 0 1 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A←A (rpa) Obtains the logical product of the contents of the accumulator and the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7), and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 ANA H–; A ← A (HL), HL ← HL–1 This example obtains the logical product of A and the memory contents addressed by the HL register pair and stores the result in A, and then decrements HL. ORAX rpa (Or Memory addressed by Register Pair with A) Operation code : 0 1 1 0 1 0 1 1 0 1 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A←A (rpa) Obtains the logical sum of the contents of the accumulator and the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7), and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 ORAX D; A ← A (DE) 266 CHAPTER 14 INSTRUCTION SET XRAX rpa (Exclusive-Or Memory addressed by Register Pair with A) Operation code : 0 1 1 0 1 0 1 1 0 0 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A←A (rpa) Obtains the exculsive logical sum of the contents of the accumulator and the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7), and stores the result in the accumulator. Flags affected Example : : Z, SK ← 0, L1 ← 0, L0 ← 0 LXI MVI SK JMP H, 4000H ; HL ← 4000H A, 0A8H Z KORED A8H A8H 00H 4000H A8H ; A ← A8H ; A←A (HL) ; SKIP IF ZERO ; (DE) ← A Memory XRAX H STAX D 10101000 10101000 ↓ 00000000 In this example, since the contents of A and the contents of address 4000H are the same, the exclusive logical sum is 0, and the Z flag is set. Thus the STAX instruction is skipped by the following SK Z instruction, and the JMP instruction is executed. GTAX rpa (Greater Than Memory addressed by Register Pair) Operation code : 0 1 1 0 1 1 1 0 0 1 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A–(rpa)–1; Skip if no borrow. Subtracts the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7) and 1 from the contents of the accumulator. Skips if no borrow is generated as a result of the subtraction (A>(rpa)). Flags affected Example : : Z, SK, HC, L1 ← 0, L0 ← 0, CY GTAX D; A–(DE)–1 A skip is performed if A is greater than the contents of the memory addressed by the DE register pair. 267 CHAPTER 14 INSTRUCTION SET LTAX rpa (Less Than Memory addressed by Register Pair) Operation code : 0 1 1 0 1 1 1 1 0 1 0 0 0 A2 A1 A0 Number of bytes : Number of states : Function : 2 11 (8) A–(rpa); Skip if borrow. Subtracts the contents of the memory addressed by the register pair rpa (BC, DE, HL, DE+, HL+, DE–, HL–) specified by A2A1A0 (1 to 7) from the contents of the accumulator. Skips if a borrow is generated as a result of the subtraction (Abyte). Flags affected : Z, SK, HC, L1 ← 0, L0 ← 0, CY GTI r, byte (Greater Than Immediate) Operation code : 0 0 1 0 1 1 1 0 0 1 1 0 0 R2 R1 R0 Data Number of bytes : Number of states : Function : 3 11 (11) r–byte–1; Skip if no borrow. Subtracts the immediate data in the 3rd byte and 1 from the contents of the register r (V, A, B, C, D, E, H, L) specified by R2R1R0 (0 to 7). Skip if no borrow is generated as a result of the subtraction (r>byte). Flags affected : Z, SK, HC, L1 ← 0, L0 ← 0, CY GTI sr2, byte (Greater Than Immediate) Operation code : 0 S3 1 0 1 1 0 0 0 1 1 S2 0 S1 0 S0 Data Number of bytes : Number of states : Function : 3 14 (11) sr2–byte–1; Skip if no borrow. Subtracts the immediate data in the 3rd byte and 1 from the contents of the special register sr2 (PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM) specified by S3S2S1S0 (0 to 3, 5 to 9, B, D). Skips if no borrow is generated as a result of the subtraction (sr2>byte). Flags affected : Z, SK, HC, L1 ← 0, L0 ← 0, CY 279 CHAPTER 14 INSTRUCTION SET LTI A, byte (Less Than Immediate) Operation code : 0 0 1 1 0 1 1 1 Data Number of bytes : Number of states : Function : 2 7 (7) A–byte ; Skip if borrow. Subtracts the immediate data in the 2nd byte from the contents of the accumulator. Skips if a borrow is generated as a result of the subtraction (A