NP100P04PLG-E1-AY

DATA SHEET MOS FIELD EFFECT TRANSISTOR NP100P04PLG SWITCHING P-CHANNEL POWER MOSFET DESCRIPTION The NP100P04PLG is P-channel MOS Field Effect Transistor designed for high current switching applications. ORDERING INFORMATION PART NUMBER NP100P04PLG-E1-AY NP100P04PLG-E2-AY Note Note LEAD PLATING Pure Sn (Tin) PACKING Tape 800 p/reel PACKAGE TO-263 (MP-25ZP) Note Pb-free (This product does not contain Pb in external electrode.) FEATURES • Super low on-state resistance RDS(on)1 = 3.7 mΩ MAX. (VGS = −10 V, ID = −50 A) RDS(on)2 = 5.1 mΩ MAX. (VGS = −4.5 V, ID = −50 A) • High current rating: ID(DC) = m100 A • Built-in gate protection diode (TO-263) ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25°C) Drain Current (pulse) Note1 VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg −40 m20 m100 m300 200 1.8 175 −55 to +175 74 550 V V A A W W °C °C A mJ Total Power Dissipation (TC = 25°C) Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy Note2 Note2 IAS EAS Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1% 2. Starting Tch = 25°C, VDD = −30 V, RG = 25 Ω, VGS = −20 → 0 V THERMAL RESISTANCE Channel to Case Thermal Resistance Channel to Ambient Thermal Resistance Rth(ch-C) Rth(ch-A) 0.75 83.3 °C/W °C/W The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. D18694EJ3V0DS00 (3rd edition) Date Published May 2007 NS CP(K) Printed in Japan 2007 The mark shows major revised points. The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what:" field. NP100P04PLG ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate to Source Threshold Voltage Forward Transfer Admittance Note Note SYMBOL IDSS IGSS VGS(th) | yfs | RDS(on)1 RDS(on)2 TEST CONDITIONS VDS = −40 V, VGS = 0 V VGS = m20 V, VDS = 0 V VDS = −10 V, ID = −1 mA VDS = −10 V, ID = −50 A VGS = −10 V, ID = −50 A VGS = −4.5 V, ID = −50 A VDS = −10 V, VGS = 0 V, f = 1 MHz VDD = −20 V, ID = −50 A, VGS = −10 V, RG = 0 Ω MIN. TYP. MAX. −10 m10 UNIT μA μA V S −1.0 43 −1.6 88 2.8 3.4 15100 2400 1130 38 30 300 100 −2.5 Drain to Source On-state Resistance 3.7 5.1 mΩ mΩ pF pF pF ns ns ns ns nC nC nC Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Note Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr VDD = −32 V, VGS = −10 V, ID = −100 A IF = −100 A, VGS = 0 V IF = −100 A, VGS = 0 V, di/dt = −100 A/μs 320 37 85 0.91 70 123 1.5 V ns nC Note Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2% TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = −20 → 0 V − ID VDD 50 Ω L VDD PG. BVDSS VDS VGS(−) 0 τ Starting Tch τ = 1 μs Duty Cycle ≤ 1% VDS Wave Form TEST CIRCUIT 2 SWITCHING TIME D.U.T. RL RG VDD VDS(−) 90% 10% 10% 90% VGS(−) VGS Wave Form 0 10% VGS 90% IAS VDS 0 td(on) ton tr td(off) toff tf TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = −2 mA PG. 50 Ω RL VDD 2 Data Sheet D18694EJ3V0DS NP100P04PLG TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA dT - Percentage of Rated Power - % 120 100 80 60 40 20 0 0 25 50 75 100 125 150 175 200 240 TOTAL POWER DISSIPATION vs. CASE TEMPERATURE PT - Total Power Dissipation - W 200 160 120 80 40 0 0 25 50 75 100 125 150 175 200 Tch - Channel Temperature - °C FORWARD BIAS SAFE OPERATING AREA TC - Case Temperature - °C -1000 ID(pulse) PW =1 i ID - Drain Current - A -100 RDS(on) Limited (VGS = −10 V) 00 μs 1i ID(DC) ms i DC w Po 1i 0 ms i -10 D er i ss ip io at -1 T C = 25 ° C Single Pulse d it e im nL -0.1 -0.1 -1 -10 -100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - °C/W 1000 100 10 1 Rth(ch-C) = 0.75°C/Wi 0.1 0.01 Single Pulse 0.001 Rth(ch-A) = 83.3°C/Wi 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet D18694EJ3V0DS 3 NP100P04PLG DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE -300 -250 ID - Drain Current - A FORWARD TRANSFER CHARACTERISTICS -1000 VGS = −10 V ID - Drain Current - A -100 −4.5 V VDS = −10 V Pulsed -200 -150 -100 -50 -10 -1 -0.1 -0.01 Tch = −55°C −25°C 25°C 75°C 125°C 150°C 175°C -0 -1 -2 -3 -4 -5 Pulsed 0 0 -0.5 -1 -1.5 -2 -0.001 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT | yfs | - Forward Transfer Admittance - S GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE VGS(th) - Gate to Source Threshold Voltage - V -3 -2.5 -2 -1.5 -1 -0.5 0 -75 -25 25 75 125 175 225 Tch - Channel Temperature - °C DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 1000 Tch = −55°C −25°C 25°C 75°C 100 10 125°C 150°C 175°C 1 VDS = −10 V Pulsed 0.1 -0.1 -1 VDS = −10 V ID = −1 mA -10 -100 -1000 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ 10 8 6 4 2 Pulsed 0 0 -5 -10 -15 -20 ID = −100 A −50 A −20 A RDS(on) - Drain to Source On-state Resistance - mΩ 6 5 4 3 −10 V 2 1 Pulsed 0 -1 -10 -100 -1000 VGS = −4.5 V ID - Drain Current - A VGS - Gate to Source Voltage - V 4 Data Sheet D18694EJ3V0DS NP100P04PLG DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE RDS(on) - Drain to Source On-state Resistance - mΩ CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 100000 Ciss, Coss, Crss - Capacitance - pF 8 6 Ciss 10000 Coss VGS = −4.5 V 4 −10 V 2 ID = −50 A Pulsed 0 -75 -25 25 75 125 175 225 1000 VGS = 0 V f = 1 MHz 100 -0.1 -1 Crss -10 -100 Tch - Channel Temperature - °C SWITCHING CHARACTERISTICS 10000 VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns VDS - Drain to Source Voltage - V DYNAMIC INPUT/OUTPUT CHARACTERISTICS -40 VDD = −32 V −20 V −8 V -12 VGS - Gate to Source Voltage - V 1000 td(off) tf td(on) tr -30 -9 100 -20 VGS -10 VDS 0 ID = −100 A 0 50 100 150 200 250 300 -6 10 1 -0.1 VDD = −20 V VGS = −10 V RG = 0 Ω -1 -10 -100 -1000 -3 0 350 ID - Drain Current - A QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE -1000 IF - Diode Forward Current - A REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 1000 trr - Reverse Recovery Time - ns -100 -10 -1 -0.1 Pulsed -0.01 0 0.5 1 1.5 VF(S-D) - Source to Drain Voltage - V VGS = −10 V 0V 100 10 di/dt = −100 A/μs VGS = 0 V 1 -0.1 -1 -10 -100 IF - Diode Forward Current - A Data Sheet D18694EJ3V0DS 5 NP100P04PLG PACKAGE DRAWING (Unit: mm) TO-263 (MP-25ZP) 10.0 ±0.3 7.88 MIN. 8.0 TYP. 1.35 ±0.3 No plating 4.45 ±0.2 1.3 ±0.2 4 9.15 ±0.3 15.25 ±0.5 0.5 0.025 to 0.25 0.6 ±0 2.54 12 3 2.5 1. Gate 2. Drain 3. Source 4. Fin (Drain) EQUIVALENT CIRCUIT Drain Gate Gate Protection Diode Body Diode Source Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. 6 Data Sheet D18694EJ3V0DS 2.54 ±0.25 0.75 ±0.2 .2 0 to 8 ˚ 0.25 NP100P04PLG • T he information in this document is current as of May, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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