UPA2452

DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2452 N-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING PACKAGE DRAWING (Unit: mm) 1 0.5±0.1 0.5±0.1 DESCRIPTION The µ PA2452 is a switching device which can be driven directly by a 2.5 V power source. This µ PA2452 features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on. 6 1.85±0.1 0.145±0.05 2 3 5 4 0.25 +0.1 -0.05 4.4±0.1 FEATURES • 2.5 V drive available • Low on-state resistance RDS(on)1 = 17.5 mΩ TYP. (VGS = 4.5 V, ID = 4.0 A) RDS(on)2 = 18.5 mΩ TYP. (VGS = 4.0 V, ID = 4.0 A) RDS(on)3 = 21.0 mΩ TYP. (VGS = 3.1 V, ID = 4.0 A) RDS(on)4 = 25.0 mΩ TYP. (VGS = 2.5 V, ID = 4.0 A) • Built-in G-S protection diode against ESD 5.0±0.1 7 0.05 +0 -0.05 (0.9) ORDERING INFORMATION PART NUMBER PACKAGE 6PIN HWSON (4521) (0.15) (3.05) Each lead has same dimensions 5,6: Source 2 1,2: Source 1 4: Gate 2 3: Gate 1 7: Drain (0.50) µ PA2452TL ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) Note1 Note2 Note1 VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg 24.0 ±12.0 ±7.8 ±80.0 2.5 0.7 150 −55 to +150 V V A A W W °C °C Gate1 EQUIVALENT CIRCUIT Drain1 Drain2 Drain Current (pulse) Total Power Dissipation (2 units) Channel Temperature Storage Temperature Body Diode (1.45) 0.8 MAX. 2.0±0.1 Gate2 Gate Protection Diode Source2 Body Diode Total Power Dissipation (2 units) Note3 Gate Protection Diode Source1 2 Notes 1. Mounted on ceramic substrate of 50 cm x 1.1 mm 2. PW ≤ 10 µs, Duty Cycle ≤ 1% 2 3. Mounted on FR-4 board of 50 cm x 1.6 mm Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G16272EJ1V0DS00 (1st edition) Date Published October 2003 NS CP(K) Printed in Japan 2003 µ PA2452 ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Forward Transfer Admittance Note Note SYMBOL IDSS IGSS VGS(off) | yfs | RDS(on)1 RDS(on)2 RDS(on)3 RDS(on)4 TEST CONDITIONS VDS = 24.0 V, VGS = 0 V VGS = ±12.0 V, VDS = 0 V VDS = 10.0 V, ID = 1.0 mA VDS = 10.0 V, ID = 4.0 A VGS = 4.5 V, ID = 4.0 A VGS = 4.0 V, ID = 4.0 A VGS = 3.1 V, ID = 4.0 A VGS = 2.5 V, ID = 4.0 A VDS = 10.0 V VGS = 0 V f = 1.0 MHz VDD = 20.0 V ID = 4.0 A VGS = 4.0 V RG = 6.0 Ω VDD = 20.0 V VGS = 4.0 V ID = 7.8 A IF = 7.8 A, VGS = 0 V IF = 7.8 A, VGS = 0 V di/dt = 100 A/µs MIN. TYP. MAX. 10.0 ±10.0 UNIT µA µA V S 0.5 3 12.0 12.5 15.8 16.8 0. 7 1.5 Drain to Source On-state Resistance 17.5 18.5 21.0 25.0 390 130 90 20 120 180 210 6.5 1.0 3.0 0.8 210 330 21.5 22.5 26.5 30.0 mΩ mΩ mΩ mΩ pF pF pF ns ns ns ns nC nC nC V ns nC Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Note Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2% TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE D.U.T. RL VGS PG. RG Wave Form D.U.T. VGS 0 10% VGS 90% IG = 2 mA 50 Ω RL VDD VDD PG. 90% VDS 90% 10% 10% VGS 0 τ τ = 1 µs Duty Cycle ≤ 1% VDS VDS Wave Form 0 td(on) ton tr td(off) toff tf 2 Data Sheet G16272EJ1V0DS µ PA2452 DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA dT - Percentage of Rated Power - % 120 3 TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE PT - Total Power Dissipation - W Mounted on ceramic board of 100 80 60 40 20 0 0 25 50 75 100 125 150 175 2.5 2 1.5 1 0.5 0 0 25 50 50 cm2 x 1.1 mm, 2 units Mounted on FR-4 board of 50 cm2 x 1.6 mm, 2 units 75 100 125 150 175 TA - Ambient Temperature - °C TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 1000 PW = 10 µs RDS(on) Limited (at VGS = 4.5 V) ID(pulse) 100 µs ID - Drain Current - A 100 10 ID(DC) 1 ms 10 ms DC (2 units) 100 ms 1 0.1 Single pulse Mounted on ceramic board of 50 cm2 x 1.1 mm 0.01 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(ch-A) - Transient Thermal Resistance - °C/W 1000 Mounted on FR-4 board of 50 cm2 x 1.6 mm 100 Mounted on ceramic board of 10 50 cm2 x 1.1 mm 1 Single pulse PD (FET1) : PD (FET2) = 1:1 0.1 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G16272EJ1V0DS 3 µ PA2452 DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 50 Pulsed VGS = 4.5 V 4.0 V 3.1 V FORWARD TRANSFER CHARACTERISTICS 100 10 VDS =10.0 V Pulsed ID - Drain Current - A ID - Drain Current - A 40 1 0.1 0.01 0.001 0.0001 30 2.5 V 20 TA = 125°C 75°C 25°C −25°C 10 0 0 0.4 0.8 1.2 1.6 0 0.5 1 1.5 2 2.5 VDS - Drain to Source Voltage - V GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE 1 VGS - Gate to Source Voltage - V FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT | yfs | - Forward Transfer Admittance - S 10 VDS = 10.0 V Pulsed VGS(off) - Gate Cut-off Voltage - V VDS = 10.0 V ID = 1.0 mA 0.8 1 0.6 TA = −25°C 25°C 75°C 125°C 0.4 0.1 0.2 0 -50 0 50 100 150 0.01 0.01 0.1 1 10 Tch - Channel Temperature - °C DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT RDS(on) - Drain to Source On-state Resistance - mΩ RDS(on) - Drain to Source On-state Resistance - mΩ 50 Pulsed ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 50 ID = 4.0 A Pulsed 40 40 30 VGS = 2.5 V 3.1 V 4.0 V 4.5 V 30 20 20 10 10 0 0.01 0 0 2 4 6 8 10 12 0.1 1 10 100 ID - Drain Current - A VGS - Gate to Source Voltage - V 4 Data Sheet G16272EJ1V0DS µ PA2452 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE RDS(on) - Drain to Source On-state Resistance - mΩ 50 ID = 4.0 A Pulsed CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 1000 40 Ciss, Coss, Crss - Capacitance - pF 30 VGS = 2.5 V 3.1 V 4.0 V 4.5 V Ciss 100 Coss Crss 20 10 VGS = 0 V f = 1.0 MHz 0 -50 0 50 100 150 10 0.1 1 10 100 Tch - Channel Temperature - °C SWITCHING CHARACTERISTICS 1000 4 VDS - Drain to Source Voltage - V DYNAMIC INPUT CHARACTERISTICS VGS - Gate to Source Voltage - V ID = 7.8 A td(on), tr, td(off), tf - Switching Time - ns VDD = 20.0 V VGS = 4.0 V RG = 6.0 Ω tr tf 3 VDD = 5.0 V 12.0 V 20.0 V 100 td(off) 2 1 td(on) 10 0.1 1 10 100 0 0 2 4 6 8 ID - Drain Current - A SOURCE TO DRAIN DIODE FORWARD VOLTAGE 100 VGS = 0 V Pulsed QG - Gate Charge - nC IF - Diode Forward Current - A 10 1 0.1 0.01 0.2 0.4 0.6 0.8 1.0 1.2 VF(S-D) - Source to Drain Voltage - V Data Sheet G16272EJ1V0DS 5 µ PA2452 When you use this device, in order to prevent a customer’s hazard and damage, use it with understanding the following contents. If used exceeding recommended conditions, there is a possibility of causing failure of the device and characteristic degradation. 1. When you mount the device on a substrate, carry out within our recommended soldering conditions of infrared reflow. If mounted exceeding the conditions, the characteristic of a device may be degraded and it may result failure. 2. When you wash the device mounted the substrate, carry out within our recommended conditions. If washed exceeding the conditions, the characteristic of a device may be degraded and it may result in failure. 3. When you use ultrasonic wave to substrate after the device mounting, prevent from touching a resonance generator directly. If it touches, the characteristic of a device may be degraded and it may result in failure. 4. Please refer to Figure 1 as an example of the land pattern. Optimize the land pattern in consideration of density, appearance of solder fillets, common difference, etc in an actual design. Figure 1. Example of the land pattern 3.86 Unit: mm 2.04 1.16 0.50 0.30 0.83 6 Data Sheet G16272EJ1V0DS µ PA2452 5. This device is very thin device and should be handled with caution for mechanical stress. The rate of distortion applied to the device should become below 2000 µε.Note1 If the rate of distortion exceeds 2000 µε, the characteristic of a device may be degraded and it may result in failure. Figure 2. Direction of substrate and stress The substrate that mounted the device is on a stand with a support width of 24 mm. The device is turned downward. The stress is applied from a top. Substrate: 33 x 6 mm, t = 0.5 mm, FR-4 Stress The direction of a device: Bend Support width 24 mm Measurement position Device Figure 3. Example of the bend and the rate of distortion Note2 6000 The rate of distortion - µ ε 5000 4000 3000 2000 1000 0 0 0.5 1 Recommended condition Bend - mm Note 1. Definition (written as ε in this document) ε = (l − l0)/l0 l0: Distance for two arbitrary points before receiving stress. l: Distance above-mentioned when receiving stress. 2. The relation of the distortion and the bend changes with several conditions, such as a size of substrate and so on. Data Sheet G16272EJ1V0DS 7 µ PA2452 • T he information in this document is current as of October, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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