UPA2719GR

DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2719GR SWITCHING P-CHANNEL POWER MOS FET PACKAGE DRAWING (Unit: mm) 8 5 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8 : Drain DESCRIPTION The µ PA2719GR is P-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and Li-ion battery protection circuit. FEATURES • Low on-state resistance RDS(on)1 = 13 mΩ MAX. (VGS = −10 V, ID = −5.0 A) RDS(on)2 = 20.9 mΩ MAX. (VGS = −4.5 V, ID = −5.0 A) • Low Ciss: Ciss = 2010 pF TYP. • Built-in gate protection diode • Small and surface mount package (Power SOP8) 6.0 ±0.3 4.4 +0.10 –0.05 1 1.44 4 5.37 MAX. 0.8 1.8 MAX. 0.15 ORDERING INFORMATION PART NUMBER PACKAGE Power SOP8 0.05 MIN. 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M µ PA2719GR ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) Drain Current (pulse) Note1 Note2 Note3 VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg –30 m20 m10 m100 2 2 150 –55 to + 150 −10 10 V V A A W W °C °C A mJ Gate Gate Protection Diode Body Diode EQUIVALENT CIRCUIT Drain Total Power Dissipation Total Power Dissipation Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy Notes 1. 2. 3. 4. Note4 Note4 IAS EAS Source PW ≤ 10 µs, Duty Cycle ≤ 1% Mounted on ceramic substrate of 1200 mm2 x 2.2 mm Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm, PW = 10 sec Starting Tch = 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G16953EJ1V0DS00 (1st edition) Date Published July 2004 NS CP(K) Printed in Japan 2004 µ PA2719GR ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Forward Transfer Admittance Note Note SYMBOL IDSS IGSS VGS(off) | yfs | RDS(on)1 RDS(on)2 RDS(on)3 TEST CONDITIONS VDS = −30 V, VGS = 0 V VGS = m20 V, VDS = 0 V VDS = −10 V, ID = −1 mA VDS = −10 V, ID = −5.0 A VGS = −10 V, ID = −5.0 A VGS = −4.5 V, ID = −5.0 A VGS = −4.0 V, ID = −5.0 A VDS = −10 V VGS = 0 V f = 1 MHz VDD = −15 V, ID = −5.0 A VGS = −10 V RG = 10 Ω MIN. TYP. MAX. UNIT –1 m10 –1.0 8 10.6 14.2 16.6 2010 460 350 12 15 290 180 13 20.9 25.5 µA µA V S mΩ mΩ mΩ pF pF pF ns ns ns ns nC nC nC V ns nC –2.5 Drain to Source On-state Resistance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Note Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr VDD = −24 V VGS = −10 V ID = −10 A IF = 10 A, VGS = 0 V IF = 10 A, VGS = 0 V di/dt = 50 A/µs 43 5.5 12 0.84 105 6.7 Note Pulsed TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = −20 → 0 V − ID VDD 50 Ω L VDD PG. BVDSS VDS VGS(−) 0 τ Starting Tch τ = 1 µs Duty Cycle ≤ 1% VDS Wave Form TEST CIRCUIT 2 SWITCHING TIME D.U.T. RL RG VDD VDS(−) 90% 10% 10% 90% VGS(−) VGS Wave Form 0 10% VGS 90% IAS VDS 0 td(on) ton tr td(off) toff tf TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = −2 mA PG. 50 Ω RL VDD 2 Data Sheet G16953EJ1V0DS µ PA2719GR ELECTRICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA dT - Percentage of Rated Power - % 120 PT - Total Power Dissipation - W 100 80 60 40 20 0 0 25 50 75 100 125 150 175 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 2.8 2.4 2 1.6 1.2 0.8 0.4 0 0 25 50 75 100 125 150 175 TA - Ambient Temperature - °C Mounted on ceramic substrate of 1200 mm2 x 2.2 mm TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE -1000 -100 -10 -1 -0.1 ID(pulse) RDS(on)Limited (at VGS = −10 V) PW = 100 µs ID(DC) 1 ms DC Power Dissipation Limited TA = 25°C Single pulse Mounted on ceramic substrate of 1200 mm x 2.2 mm 2 ID - Drain Current - A 10 ms 100 ms -0.01 -0.01 -0.1 -1 -10 -100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(ch-A) - Transient Thermal Resistance - °C/W Rth(ch-A)2 100 Rth(ch-A)1 10 1 Single pulse, TA = 25°C Rth(ch-A)1 : Mounted on ceramic substrate of 1200 mm2 x 2.2 mm Rth(ch-A)2 : Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm 0.1 100 µ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G16953EJ1V0DS 3 µ PA2719GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE -125 Pulsed ID - Drain Current - A ID - Drain Current - A -100 VGS = −10 V -75 −4 V -50 -25 0 0 -0.5 -1 -1.5 -2 VDS - Drain to Source Voltage - V −4.5 V -10 -100 VDS = −10 V Pulsed TA = 150°C 75°C 25°C −40°C FORWARD TRANSFER CHARACTERISTICS -1 -0.1 -0.01 0 -1 -2 -3 -4 -5 VGS - Gate to Source Voltage - V GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE VGS(off) - Gate Cut-off Voltage - V VDS = −10 V ID = −1 mA | yfs | - Forward Transfer Admittance - S -2.5 -2 -1.5 -1 -0.5 0 -50 0 50 100 150 Tch - Channel Temperature - °C DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 100 TA = 150°C 75°C 25°C −40°C 10 1 0.1 VDS = −10 V Pulsed 0.01 -0.01 -0.1 -1 -10 -100 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 40 I D = −5 A Pulsed 30 RDS(on) - Drain to Source On-state Resistance - mΩ 40 Pulsed 30 VGS = −10 V −4.5 V −4 V RDS(on) - Drain to Source On-state Resistance - mΩ 20 20 10 10 0 -1 -10 -100 -1000 ID - Drain Current - A 0 0 -5 -10 -15 -20 VGS - Gate to Source Voltage - V 4 Data Sheet G16953EJ1V0DS µ PA2719GR DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 30 VGS = −10 V −4.5 V −4 V Ciss, Coss, Crss - Capacitance - pF CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ 10000 VGS = 0 V f = 1 MHz Ciss 20 1000 Coss Crss 100 10 I D = −5 A Pulsed 0 -50 0 50 100 150 Tch - Channel Temperature - °C 10 -0.1 -1 -10 -100 VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS 10000 VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns VDD = −15 V VGS = −10 V RG = 1 0 Ω DYNAMIC INPUT/OUTPUT CHARACTERISTICS -30 ID = −10 A VDD = −24 V −15 V −6 V -15 VGS - Gate to Source Voltage - V 1000 td(off) tf tr -20 -10 100 -10 VDS 0 10 td(on) VGS -5 1 -0.1 0 0 20 40 60 QG - Gate Charge - nC -1 -10 -100 ID - Drain Current - A SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 1000 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VF(S-D) - Source to Drain Voltage - V trr - Reverse Recovery Time - ns 1000 Pulsed IF - Diode Forward Current - A VGS = 0 V di/dt = 50 A/µs VGS = −10 V 0V 100 10 0.1 1 10 100 IF - Diode Forward Current - A Data Sheet G16953EJ1V0DS 5 µ PA2719GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD SINGLE AVALANCHE ENERGY DERATING FACTOR 100 Energy Derating Factor - % 80 60 40 20 0 VDD = −15 V RG = 2 5 Ω VGS = −20 → 0 V IAS ≤ −10 A - 100 IAS - Single Avalanche Current - A - 10 IAS = −10 A EAS = 10 mJ -1 - 0.1 0.01 V DD = −15 V RG = 25 Ω V GS = −20 → 0 V Starting Tch = 25°C 0.1 1 10 25 50 75 100 125 150 L - Inductive Load - mH Starting Tch - Starting Channel Temperature - °C 6 Data Sheet G16953EJ1V0DS µ PA2719GR • T he information in this document is current as of July, 2004. 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