UPA2757GR-E2-AT

DATA SHEET MOS FIELD EFFECT TRANSISTOR μ PA2757GR SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION The μ PA2757GR is Dual N-channel MOS Field Effect Transistors designed for switching application. 8 PACKAGE DRAWING (Unit: mm) 5 1 : Source 1 2 : Gate 1 7, 8 : Drain 1 3 : Source 2 4 : Gate 2 5, 6 : Drain 2 6.0 ± 0.3 4.4 +0.10 –0.05 FEATURES • Low on-state resistance RDS(on)1 = 36.0 mΩ MAX. (VGS = 10 V, ID = 3.0 A) RDS(on)2 = 50.0 mΩ MAX. (VGS = 4.5 V, ID = 3.0 A) 1.44 1 5.37 MAX. 1.8 MAX. 4 • Low gate charge QG = 10 nC TYP. (VGS = 10 V) • Built-in G-S protection diode • Small and surface mount package (Power SOP8) 0.8 0.15 0.05 MIN. 0.5 ± 0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 ORDERING INFORMATION PART NUMBER LEAD PLATING Note Note 0.12 M PACKING Tape 2500 p/reel PACKAGE Power SOP8 μ PA2757GR-E1-AT μ PA2757GR-E2-AT Pure Sn Note Pb-free (This product does not contain Pb in the external electrode and other parts.) EQUIVALENT CIRCUIT (1/2 circuit) Drain Gate Body Diode Gate Protection Diode Source Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. Caution This product is electrostatic-sensitive device due to low ESD capability and should be handled with caution for electrostatic discharge. VESD ± 600 V TYP. (C = 100 pF, R = 1.5 kΩ) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G18206EJ2V0DS00 (2nd edition) Date Published November 2007 NS Printed in Japan 2006, 2007 The mark shows major revised points. The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what:" field. μ PA2757GR ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25°C) Drain Current (pulse) Note1 Note2 Note2 Note2 VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg 30 ±20 ±5.0 ±20 1.7 2.0 150 −55 to +150 5 2.5 V V A A W W °C °C A mJ Total Power Dissipation (1 unit) Total Power Dissipation (2 units) Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy Note3 Note3 IAS EAS Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1% 2. Mounted on ceramic substrate of 2000 mm × 1.6 mmt 3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V 2 2 Data Sheet G18206EJ2V0DS μ PA2757GR ELECTRICAL CHARACTERISTICS (TA = 25°C. All terminals are connected.) CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate to Source Cut-off Voltage Forward Transfer Admittance Note Note SYMBOL IDSS IGSS VGS(off) | yfs | RDS(on)1 RDS(on)2 TEST CONDITIONS VDS = 30 V, VGS = 0 V VGS = ±16 V, VDS = 0 V VDS = 10 V, ID = 1 mA VDS = 10 V, ID = 3 A VGS = 10 V, ID = 3.0 A VGS = 4.5 V, ID = 3.0 A VDS = 10 V, VGS = 0 V, f = 1 MHz VDD = 15 V, ID = 3 A, VGS = 10 V, R G = 10 Ω MIN. TYP. MAX. 10 UNIT μA μA V S ±10 1.0 2.0 28.5 36.0 400 80 50 7 4 21 5 36.0 50.0 2.5 Drain to Source On-state Resistance mΩ mΩ pF pF pF ns ns ns ns nC nC nC V ns nC Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Note Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr ID = 5 A , VDD = 24 V, VGS = 10 V IF = 5 A, VGS = 0 V IF = 5 A, VGS = 0 V, di/dt = 50 A/μs 10 1.5 2.7 0.86 20 16 Note Pulsed TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V 50 Ω TEST CIRCUIT 2 SWITCHING TIME D.U.T. L VDD PG. RG VGS RL VDD VDS 90% 90% 10% 10% VGS Wave Form 0 10% VGS 90% BVDSS IAS ID VDD VDS VGS 0 τ τ = 1 μs Duty Cycle ≤ 1% VDS VDS Wave Form 0 td(on) ton tr td(off) toff tf Starting Tch TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = 2 mA PG. 50 Ω RL VDD Data Sheet G18206EJ2V0DS 3 μ PA2757GR TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 120 dT - Percentage of Rated Power - % PT - Total Power Dissipation - W 2.5 2 1.5 1 0.5 0 2 units Mounted on ceramic substrate of 2 2000 mm x 1.6 mmt 100 80 60 40 20 0 0 20 40 60 80 100 120 140 160 TA - Ambient Temperature - °C 1 unit 0 20 40 60 80 100 120 140 160 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 100 ID(pulse) PW ID - Drain Current - A 10 = i ID(DC) DC d it e m Li V ) n) i0 o 1 S( = D R GS (V 1i 0 Po w 1i m i 20 m 0 1i 0 μs 0 m s s i s 1 er D is si p at io n 0.1 Mounted on ceramic substrate of 2000 mm2 x 1.6 mmt, 1 unit T A = 2 5° C Single pulse Li m it e d 0.01 0.01 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(t) - Transient Thermal Resistance - °C/W 100 Rth(ch-A) = 73.5°C/Wi 10 1 Mounted on ceramic substrate of 2000 mm2 x 1.6 mmt, 1 unit TA = 25°C Single pulse 1m 10 m 100 m 1 PW - Pulse Width – s 10 100 1000 0.1 100 μ 4 Data Sheet G18206EJ2V0DS μ PA2757GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 25 20 ID - Drain Current - A 100 VGS = 10 V ID - Drain Current - A 10 1 0.1 0.01 0.001 Pulsed 0.0001 VDS = 10 V Pulsed 15 10 5 0 0 0.5 4.5 V TA = 150°C 75°C 25°C −25°C 1 1.5 0 1 2 3 4 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V GATE TO SOURCE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE VGS(off) - Gate to Source Cut-off Voltage - V | yfs | - Forward Transfer Admittance - S 2.5 2 1.5 1 0.5 0 -50 0 50 100 150 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 10 1 0.1 0.01 VDS = 10 V ID = 1 m A 0.001 −25°C 25°C 75°C TA = 150°C VDS = 10 V Pulsed 100 μ 1m 10 m 100 m 1 10 Tch - Channel Temperature - °C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT RDS(on) - Drain to Source On-state Resistance - mΩ 100 Pulsed 80 60 40 20 0 1 10 100 10 V DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ 100 80 60 40 20 0 0 5 10 15 20 ID = 3.0 A Pulsed VGS = 4.5 V ID - Drain Current - A VGS - Gate to Source Voltage - V Data Sheet G18206EJ2V0DS 5 μ PA2757GR DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE RDS(on) - Drain to Source On-state Resistance - mΩ 100 80 60 40 10 V 20 0 -50 0 50 100 150 ID = 3.0 A Pulsed CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 1000 Ciss, Coss, Crss - Capacitance - pF Ciss Coss 100 Crss VGS = 4.5 V VGS = 0 V f = 1 MHz 10 0.01 0.1 1 10 100 Tch - Channel Temperature - °C VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS 100 td(on), tr, td(off), tf - Switching Time - ns VDS - Drain to Source Voltage - V DYNAMIC INPUT/OUTPUT CHARACTERISTICS 30 12 VDD = 24 V 15 V 6V 10 8 6 VGS VDS 4 2 ID = 5 A 0 0 2 4 6 8 10 12 VGS - Gate to Source Voltage - V td(off) tf td(on) VDD = 15 V VGS = 10 V R G = 10 Ω 25 20 15 10 5 0 10 tr 1 0.1 1 10 100 ID - Drain Current - A QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE 100 10 VGS = 4.5 V 1 0.1 0.01 Pulsed 0.001 0 0.5 1 1.5 VF(S-D) - Source to Drain Voltage - V 0V trr - Reverse Recovery Time - ns IF - Diode Forward Current - A REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 100 10 VGS = 0 V di/dt = 50 A/μs 1 0.1 1 10 100 IF - Diode Forward Current - A 6 Data Sheet G18206EJ2V0DS μ PA2757GR TAPE INFORMATION There are two types (-E1, -E2) of taping depending on the direction of the device. Reel side Draw-out side −E1 TYPE −E2 TYPE MARKING INFORMATION A2757 Lot code 1 pin mark Pb-free plating marking RECOMMENDED SOLDERING CONDITIONS The μ PA2757GR should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Soldering Method Infrared reflow Soldering Conditions Maximum temperature (Package's surface temperature): 260°C or below Time at maximum temperature: 10 seconds or less Time of temperature higher than 220°C: 60 seconds or less Preheating time at 160 to 180°C: 60 to 120 seconds Maximum number of reflow processes: 3 times Maximum chlorine content of rosin flux (percentage mass): 0.2% or less Recommended Condition Symbol IR60-00-3 Partial heating Maximum temperature (Pin temperature): 350°C or below Time (per side of the device): 3 seconds or less Maximum chlorine content of rosin flux: 0.2% (wt.) or less P350 Caution Do not use different soldering methods together (except for partial heating). Data Sheet G18206EJ2V0DS 7 μ PA2757GR • T he information in this document is current as of November, 2007. The information is subject to change without notice. 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