UPC358GR5-9LG-E1-A

DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG SINGLE POWER SUPPLY DUAL OPERATIONAL AMPLIFIERS DESCRIPTION The μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG are dual operational amplifiers which are designed to operate for a single power supply. It includes features of low-voltage operation, a common-mode input voltage that range from V− (GND) level, an output from a V− (GND) level that is determined by the output stage of class C pushpull circuit and a 50 μA(TYP.) constant current, and a low current consumption. In addition, this can operate at both positive and negative power supply and it can be extensively used in various amplifier circuits. The μ PC1251GR-9LG, μ PC1251MP-KAA which expands temperature type is suited for wide operating ambient temperature use, and μ PC358GR-9LG is used for general purposes. A DC parameter selection that is compatible to operational amplifiers is also available. μ PC451GR-9LG, μ PC324GR-9LG which are quad types with the same circuit configuration are also available as series of operational amplifiers. FEATURES • Input Offset Voltage • Input Offset Current • Large Signal Voltage Gain • Small Package The mounting area is reduced to 40% or 66% compared to the conventional 8-pin plastic SOP as shown in the following diagram. Package Subject part number Standard SOP TSSOP TSSOP (2.8 x 2.9) ±2 mV (TYP.) ±5 nA (TYP.) 100000 (TYP.) • Internal frequency compensation • Output short-circuit protection μ PC1251G2, μ PC358G2 μ PC1251GR-9LG, μ PC358GR-9LG μ PC1251MP-KAA Outline comparison 6.5 4.4 6.4 2.8 4.0 5.2 (Mounting area ratio) (100%) 3.15 (60%) 2.9 (34%) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G17929EJ3V0DS00 (3rd edition) Date Published December 2007 NS Printed in Japan 2006, 2007 The mark shows major revised points. The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what:" field. μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG ORDERING INFORMATION Part Number Selected Grade Note Package 8-pin plastic TSSOP (5.72 mm(225)) Package Type • 12 mm wide embossed taping • Pin 1 on draw-out side μ PC1251GR-9LG-E1-A μ PC1251GR-9LG-E2-A Standard Note Standard 8-pin plastic TSSOP (5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 at take-up side μ PC1251GR(5)-9LG-E1-A μ PC1251GR(5)-9LG-E2-A μ PC1251MP-KAA-E1-A μ PC1251MP-KAA-E2-A Note DC parameter selection 8-pin plastic TSSOP (5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 on draw-out side Note DC parameter selection 8-pin plastic TSSOP (5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 at take-up side Note Standard 8-pin plastic TSSOP (2.8 x 2.9) • 12 mm wide embossed taping • Pin 1 on draw-out side Note Standard 8-pin plastic TSSOP (2.8 x 2.9) • 12 mm wide embossed taping • Pin 1 at take-up side μ PC1251MP(5)-KAA-E1-A μ PC1251MP(5)-KAA-E2-A μ PC358GR-9LG-E1-A μ PC358GR-9LG-E2-A Note Note DC parameter selection 8-pin plastic TSSOP (2.8 x 2.9) • 12 mm wide embossed taping • Pin 1 on draw-out side Note DC parameter selection Standard 8-pin plastic TSSOP (2.8 x 2.9) • 12 mm wide embossed taping • Pin 1 at take-up side 8-pin plastic TSSOP(5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 on draw-out side Note Standard 8-pin plastic TSSOP(5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 at take-up side μ PC358GR(5)-9LG-E1-A μ PC358GR(5)-9LG-E2-A Note DC parameter selection 8-pin plastic TSSOP(5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 on draw-out side Note DC parameter selection 8-pin plastic TSSOP(5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 at take-up side Note Pb-free (This product does not contain Pb in the external electrode and other parts.) 2 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG EQUIVALENT CIRCUIT (1/2 Circuit) V+ PIN CONFIGURATION (Marking side) 100 μ A 6 μA Q2 Q1 Q3 Q4 6 μA Q5 CC Q7 RSC OUT Q6 OUT1 II1 IN1 V− 1 2 3 4 −+ +− 2 1 8 7 6 5 V+ OUT2 II2 IN2 II + IN − Q10 Q8 Q9 Q11 Q12 Q13 50 μA V− ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter + − Note1 Symbol + − μ PC1251GR-9LG, μ PC1251GR(5)-9LG μ PC1251MP-KAA, μ PC1251MP(5)-KAA −0.3 to +32 ±32 V − 0.3 to V + 32 V − 0.3 to V + 0.3 440 Indefinite − + − − μ PC358GR-9LG, μ PC358GR(5)-9LG Unit Voltage between V and V Differential Input Voltage Input Voltage Note2 V −V VID VI V V V V mW s −40 to +85 −55 to +125 + Output applied Voltage Total Power Dissipation Note3 Note4 Note5 VO PT tS TA Tstg Output Short Circuit Duration Operating Ambient Temperature Storage Temperature −40 to +125 −55 to +150 °C °C Note1. Note that reverse connections of the power supply may damage ICs. 2. The input voltage is allowed to input without damage or destruction independent of the magnitude of V . Either input signal is not allowed to go negative by more than 0.3 V. In addition, the input voltage that operates normally as an operational amplifier is within the Common Mode Input Voltage range of an electrical characteristic. 3. A range where input voltage can be applied to an output pin externally with no deterioration or damage to the feature (characteristic). The input voltage can be applied regardless of the electric supply voltage. This specification which includes the transition state such as electric power ON/OFF must be kept. 4. This is the value of when the glass epoxy substrate (size: 100 mm x 100 mm, thickness: 1 mm, 15% of the substrate area where only one side is copper foiled is filling wired) is mounted. Note that restrictions will be made to the following conditions for each product, and the derating ratio depending on the operating ambient temperature. μ PC1251GR-9LG: Derate at −5.5 mW/°C when TA > 69°C. (Junction − ambient thermal resistance Rth(J-A) = 183°C/W) μ PC1251MP-KAA: Derate at −4.8 mW/°C when TA > 58°C. (Junction − ambient thermal resistance Rth(J-A) = 208°C/W) μ PC358GR-9LG: Derate at −5.5 mW/°C when TA > 44°C. (Junction − ambient thermal resistance Rth(J-A) = 183°C/W) 5. Short circuits from the output to V can cause destruction. Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4. + Data Sheet G17929EJ3V0DS 3 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage (Split) Power Supply Voltage (V = GND) − Symbol V V ± + MIN. ±1.5 +3 TYP. MAX. ±15 +30 Unit V V ELECTRICAL CHARACTERISTICS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG (TA = 25°C, V+ = +5 V, V− = GND) Parameter Input Offset Voltage Input Offset Current Input Bias Current Note1 Symbol VIO IIO IB AV ICC CMR SVR VO VICM IO SOURCE IO SINK1 IO SINK2 RL ≥ 2 kΩ RS = 0 Ω Conditions MIN. TYP. ±2 ±5 14 MAX. ±7 ±50 250 Unit mV nA nA Large Signal Voltage Gain Circuit Current Note2 25000 100000 0.7 1.2 mA dB dB V − 1.5 V − 1.5 40 20 50 120 + + RL = ∞, IO = 0 A 65 65 RL = 2 kΩ (Connect to GND) 0 0 VIN (+) = +1 V, VIN (−) = 0 V VIN (−) = +1 V, VIN (+) = 0 V VIN (−) = +1 V, VIN (+) = 0 V, VO = 200 mV f = 1 to 20 kHz 20 10 12 Common Mode Rejection Ratio Supply Voltage Rejection Ratio Output Voltage Swing Common Mode lnput Voltage Range Output Source Current Output Sink Current 70 100 V V mA mA μA dB Channel Separation μ PC1251GR(5)-9LG, μ PC1251MP(5)-KAA, μ PC358GR(5)-9LG (TA = 25°C, V+ = +5 V, V− = GND) Parameter Input Offset Voltage Input Offset Current Input Bias Current Note1 Symbol VIO IIO IB AV ICC CMR SVR VO VICM IO SOURCE IO SINK1 IO SINK2 RL ≥ 2 kΩ RS = 0 Ω Conditions MIN. TYP. ±2 ±5 14 MAX. ±3 ±50 60 Unit mV nA nA Large Signal Voltage Gain Circuit Current Note2 50000 100000 0.7 0.9 mA dB dB V − 1.5 V − 1.4 40 20 50 120 70 + + RL = ∞, IO = 0 A 65 65 RL = 2 kΩ (Connect to GND) 0 0 VIN (+) = +1 V, VIN (−) = 0 V VIN (−) = +1 V, VIN (+) = 0 V VIN (−) = +1 V, VIN (+) = 0 V, VO = 200 mV f = 1 to 20 kHz 30 15 30 Common Mode Rejection Ratio Supply Voltage Rejection Ratio Output Voltage Swing Common Mode lnput Voltage Range Output Source Current Output Sink Current 70 100 V V mA mA μA dB Channel Separation Notes1. The input bias current flows in the direction where the IC flows out because the first stage is configured with a PNP transistor. 2. This is a current that flows in the internal circuit. This current will flow irrespective of the channel used. 4 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, TYP.) (Reference value) PT vs. TA ICC vs. V+ 2 ICC - Supply Current - mA RL = ∞ IO = 0 A 1.5 TA = 25°C 1 125°C 600 μP PT - Total Power Dissipation - mW LG -9 R G 51 12 A PC KA μ P1M 25 C1 500 400 300 200 With 100 mm x 100 mm, 100 0 0 thickness 1 mm glass epoxy substrate (refer to "ABSOLUTE MAXIMUM RATINGS Note 4" ) μP G 58 C3 20 40 60 TA - Operating Ambient Temperature - °C VIO vs. V+ G 9L R80 100 120 140 0.5 −40°C 0 0 + 10 20 30 − 40 V - Power Supply Voltage - V (V = GND) VIO vs. TA 3 VIO - Input Offset Voltage - mV 2 1 0 -1 -2 -3 V+ = +5 V, V− = GND each 5 samples data -50 0 50 100 150 3 VIO - Input Offset Voltage - mV 2 1 0 -1 -2 -3 0 10 20 30 40 V+ - Power Supply Voltage - V (V− = GND) TA - Operating Ambient Temperature - °C IB vs. V+ 30 30 IB vs. TA V+ = +15 V IB - Input Bias Current - nA 20 IB - Input Bias Current - nA V− = GND 20 10 10 0 0 + 0 10 20 30 − 40 -50 0 50 100 150 V - Power Supply Voltage - V (V = GND) TA - Operating Ambient Temperature - °C Data Sheet G17929EJ3V0DS 5 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG IO SHORT vs. TA AV vs. V+ 70 IO SHORT - Output Short Current - mA − + IO SHORT AV - Voltage Gain - dB 160 RL = 20 kΩ 120 2 kΩ 60 50 80 40 40 30 -20 0 20 40 60 80 0 0 10 20 30 40 V+ - Power Supply Voltage - V (V− = GND) TA - Operating Ambient Temperature - °C AV, φ vs. f 140 AV - Voltage Gain - dB, φ - Phase Margin - deg. 120 100 ±7.5 V 80 ±2.5 V 60 40 20 0 0.1 1 V ± = ±15 V φ AV ±15 V ±7.5 V ±2.5 V 10 100 1k 10 k 100 k 1M f - Frequency - Hz VO vs. f CMR vs. f CMR - Common Mode Rejection Ratio - dB 20 VO - Output Voltage Signal - Vp-p 100 kΩ 1 kΩ +15 V − VO 2 kΩ 120 100 80 60 40 20 0 100 1k 10 k 100 k 1M 15 +7 V + VIN 10 5 0 1k 3 5 10 k 30 50 100 k 3005001 M f - Frequency - Hz f - Frequency - Hz 6 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG PULSE RESPONSE VIN - Input Voltage - V VO - Output Voltage - V SR - TA 4 3 2 1 0 3 2 1 RL ≥ 2 kΩ V + = +15 V SR - Slew Rate - V/μs 0.4 SR − SR + 0.2 0.3 0.1 V ± = ±15 V VO = ±10 V 0 20 40 t - time - μs 60 80 0 -50 0 50 100 TA - Operating Ambient Temperature - °C VO vs. IO SINK 10 5 V+ ΔVO vs. IO SOURCE ΔVO - Output Voltage to V+ - V TA = −40°C VO - Output Voltage - V 1 25°C 4 3 V+ /2 + − ΔVO IO SOURCE V+ = +15 V 0.1 125°C V+ V+ /2 IO SINK VO TA = −40°C 2 1 125°C 0 0.01 0.1 1 10 100 25°C − + 0.01 0.01 0.1 1 10 100 IO SINK - Output Sink Current - mA IO SOURCE - Output Source Current - mA Data Sheet G17929EJ3V0DS 7 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG PRECAUTIONS FOR USE O The process of unused circuits If there is an unused circuit, the following connection is recommended. Process example of unused circuits V+ V+ R − + R V− To potentials within the range of common-mode input voltage (VICM) V− Remark A midpoint potential of V+ and V− is applied to this example. O Ratings of input/output pin voltage When the voltage of input/output pin exceeds the absolute maximum rating, it may cause degradation of characteristics or damages, by a conduction of a parasitic diode within an IC. In addition, when the input pin may be lower than V−, or the output pin may exceed the power supply voltage, it is recommended to make a clump circuit by a diode whose forward voltage is low (e.g.: Schottky diode) for protection. O Range of common-mode input voltage When the supply voltage does not meet the condition of electrical characteristics, the range of common-mode input voltage is as follows. VICM (TYP.): V− to V+ − 1.5 (V) (TA = 25°C) During designing, temperature characteristics for use with allowance. O The maximum output voltage The range of the TYP. value of the maximum output voltage when the supply voltage does not meet the condition of electrical characteristics is as follows: VOm+ (TYP.): V+ − 1.5 (V) (TA = 25°C), VOm− (TYP.) (IO SINK ≤ 50 μA): Approx. V− (V) (TA = 25°C) During designing, consider variations in characteristics and temperature characteristics for use with allowance. In addition, also note that the output voltage range (VOm+ − VOm−) becomes narrow when an output current increases. O Operation of output This IC consist an output level of a class C push-pull. Therefore, when a load resistance is connected to the midpoint potential of V+, V−, a crossover distortion occurs at the transition state of output current flow direction (source, sink). O Handling of ICs When stress is added to ICs due to warpage or bending of a board, the characteristic fluctuates due to piezoelectric effect. Therefore, pay attention to warpage or bending of a board. 8 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG PACKAGE DRAWINGS (Unit: mm) 8-PIN PLASTIC TSSOP (5.72mm (225)) D D1 detail of lead end 8 5 c A3 θ L Lp 1 4 (UNIT:mm) ZD b x e M ITEM D D1 DIMENSIONS 3.15 ± 0.15 3.00 ± 0.10 4.40 ± 0.10 6.40 ± 0.20 1.20 MAX. 0.10 ± 0.05 1.00 ± 0.05 0.25 + 0.06 0.24 − 0.05 0.145 ± 0.055 0.50 0.60 ± 0.15 1.00 ± 0.20 3° +5° −3° 0.65 0.10 0.10 0.60 P8GR-65-9LG S A HE E L1 E HE A A1 A2 A3 A2 S b c L Lp L1 y S A1 θ NOTE Each lead centerline is located within 0.10mm of its true position at maximum material condition. e x y ZD Data Sheet G17929EJ3V0DS 9 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG 8-PIN PLASTIC TSSOP(2.8x2.9) D1 D detail of lead end 8 5 A3 E θ 1 4 Lp A A2 HE L1 S S c (UNIT:mm) ITEM D D1 E HE e b A A1 A2 A3 L1 c Lp x y DIMENSIONS 2.90 3.00 ± 0.20 2.80 4.00 ± 0.20 0.65 0.22 ± 0.05 1.03 MAX. 0.08 ± 0.05 0.85 ± 0.05 0.25 0.60 ± 0.20 0.145 + 0.05 0.03 0.37 ± 0.10 0.10 0.10 + 5° 3° 3° 0.525 P8MP-65-KAA A1 b ZD e xM S yS NOTE Each lead centerline is located within 0.10 mm of its true position at maximum material condition. ZD NEC Electronics Corporation 2006 10 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG RECOMMENDED SOLDERING CONDITIONS The μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Surface Mount Device μ PC1251GR-9LG-A μ PC358GR-9LG-A Process Infrared ray reflow Note , μ PC1251GR(5)-9LG-A Note , Note , μ PC358GR(5)-9LG-A Note : 8-pin plastic TSSOP (5.72 mm (225)) : 8-pin plastic TSSOP (2.8 x 2.9) Conditions Symbol IR60-00-3 μ PC1251MP-KAA-A Note , μ PC1251MP(5)-KAA-A Note Peak temperature: 260°C, Reflow time: 60 seconds or less (at 220°C or higher), Maximum number of reflow processes: 3 times. Wave soldering Solder temperature: 260°C or below, Flow time: 10 seconds or less, Maximum number of flow processes: 1 time, Pre-heating temperature: 120°C or below (Package surface temperature). WS60-00-1 Partial heating method Pin temperature: 350°C or below, Heat time: 3 seconds or less (Per each side of the device). P350 Note Pb-free (This product does not contain Pb in external electrode and other parts.) Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the device will be damaged by heat stress. Remark Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. REFERENCE DOCUMENTS Document Name QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES SEMICONDUCTOR DEVICE MOUNT MANUAL NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM-STANDARD LINEAR IC REVIEW OF QUALITY AND RELIABILITY HANDBOOK NEC SEMICONDUCTOR DEVICE RELIBIALITY/QUALITY CONTROL SYSTEM C12769E C10983E C11531E http://www.necel.com/pkg/en/mount/index.html IEI-1212 Document No. Data Sheet G17929EJ3V0DS 11 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG • T he information in this document is current as of December, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). 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