UPC659A

DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC659A 8-BIT A/D CONVERTER FOR VIDEO PROCESSING WITH REFERENCE GENERATOR AND CLAMP CIRCUIT The µPC659A is a 8-bit A/D converter for video signal processing, the power consumption of which is lower than the µPC659. The high speed and high quality bipolar processing technology has enabled fast conversion rate and high resolution to be achieved. Conversion rate is up to 20 Msps (sampling per second) and linearity error within ± 0.5 LSB while operating at low power consumption. Wide variety of application can be realized in digital application field such as digital TV system and high speed facsimile. Also, this IC includes sample and hold circuit, clamp circuit and reference voltage generator, which enable simple external circuit to be constructed. The µPC659A and the µPC659 are different in the number of clock pulses till transformed data is output after analog signal is captured. This should be taken into consideration when using the µPC659A instead of the µPC659. For details, refer to the timing chart. FEATURES • Resolution • Conversion rate • Power supply • Analog input voltage • Power consumption • Built-in circuit : 8-bit : 20 Msps : +5 V : 1.0 Vp-p : 215 mW TYP. : Sample and hold circuit Clamp circuit (Clamp voltage and clamp pulse must be supplied.) Reference voltage generator (VRB = 2.3 V, VRT = 3.3 V TYP.) • Differential non-linearity : ± 0.5 LSB MAX. ORDERING INFORMATION Part Number Package 24-pin plastic SOP (300 mil) µPC659AGS The information in this document is subject to change without notice. Document No. S10990EJ4V0DS00 (4th edition) Date Published July 1997 N Printed in Japan The mark shows major revised points. © 1992, 1996 µPC659A BLOCK DIAGRAM VCL 7 3 Flash A/D convertor 5 5 Adder Latch 23 OVER 22 DB1 VIN 4 Clamp S/H 5 PCL 6 Sample and Hold Flash A/D convertor D/A + – 21 DB2 20 DB3 17 DB4 16 DB5 15 DB6 14 DB7 13 DB8 24 CLK 8 AVCC 1 VRT 10 VRB 5 AGND 18 DVCC 19 DGND Timing Generator 2 µPC659A PIN CONFIGURATION (Top View) VRT NC AVCC VIN AGND PCL VCL AVCC AGND VRB AVCC AGND 1 2 3 4 24 23 22 21 CLK OVER DB1 DB2 DB3 DGND DVCC DB4 DB5 DB6 DB7 DB8 µPC659AGS 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 AGND AVCC CLK DB8 to DB1 DGND DVCC NC OVER PCL VCL VIN VRB VRT : Ground for Analog Circuit : Power Supply for Analog Circuit : Clock : Digital Data Bus : Ground for Digital Circuit : Power Supply for Digital Circuit : No Connection : Digital Over Range : Clamp Pulse : Clamp Voltage : Analog Signal : Reference Voltage (Bottom) : Reference Voltage (Top) 3 µPC659A PIN FUNCTIONS Pin Name VRT 1 Pin No. Input/ Output Input Function Reference voltage (Top) Equivalent Circuit VRT VRB 10 Input Reference voltage (Bottom) AVCC 1.41 kΩ 800 Ω 1.91 kΩ AGND VRB AGND VIN 4 Input Analog signal Input analog signal from this pin. The signal is read at rising edge of the clock. The clamp function also will be worked on this pin. So it’s necessary to connect capacitance and low impedance signal source. The burst signal is protected at pedestal clamp because of soft clamp circuit. AVCC AVCC AVCC AGND AGND AGND PCL 6 Input Clamp pulse Analog signal input from analog input pin is clamped to the voltage; VCL according to the high level term of this pulse. During high level signal is input, analog input pin voltage is nearly clamped to voltage VCL. AVCC AVCC AGND AGND VCL 7 Input Clamp voltage Set voltage at clamping analog input signal. Analog input signal is clamped nearly to this input voltage VCL according to the clamp pulse PCL high level period. AVCC AVCC AGND CLK 24 Input Clock Analog data acquisition and digital data out are synchronized with the rising edge of this clock. AVCC AVCC AGND AGND AVCC 3, 8, 11 – Power supply for analog circuit AVCC 4 µPC659A Pin Name AGND Pin No. 5, 9, 12 Input/ Output – Function Ground for analog circuit Equivalent Circuit AGND DB8 to DB4 DB3 to DB1 13 to 17, 20 to 22 Output Digital signal DB8 is LSB, DB1 is MSB. DVCC DVCC OVER 23 Output Digital over range Overflow (active high). DGND DVCC 18 – Power supply for digital circuit DGND DVCC DGND 19 – Ground for digital circuit DGND NC 2 – No Connection 5 µPC659A ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 ˚C) Parameter Supply voltage Digital input voltage Analog input voltage Reference input voltage Clamp voltage Clamp pulse input voltage Operating ambient temperature Storage temperature Power dissipation Symbol AVCC, DVCC VIND VINA VRT, VRB VCL VPCL TA Tstg Pd Ratings –0.3 to +6.0 –0.3 to DVCC + 0.3 –0.3 to AVCC + 0.3 –0.3 to AVCC + 0.3 –0.3 to AVCC + 0.3 –0.3 to AVCC + 0.3 –20 to +70 –40 to +150 560 Unit V V V V V V ˚C ˚C mW Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Recommended Operating Conditions (TA = –20 to +70 ˚C) Parameter Supply voltage Supply voltage difference Analog input voltage Clamp input voltage Sampling clock Sampling clock high level pulse width Sampling clock low level pulse width Clock input high level voltage Clock input low level voltage Clamp pulse width Clamp pulse input high level voltage Clamp pulse input low level voltage Clamp capacitance Maximum analog input frequency Symbol AVCC, DVCC |AVCC-DVCC| VINA VCL fsamp tPWH Conditions AGND=DGND = 0 V AGND=DGND = 0 V VCC = 5.0 V VCC = 5.0 V VRB – 0.4 VRB – 0.4 1 25 MIN. 4.7 TYP. 5.0 0 MAX. 5.3 0.1 VRT + 0.4 VRT + 0.4 20 500 Unit V V V V MHz ns tPWL 25 500 ns VCKH VCKL tPWCL VPCLH 2.0 0.8 1.0 2.0 V V µs V VPCLL 0.8 V CCL fAIN 10 8 µF MHz 6 µPC659A DC Characteristics and AC Characteristics (TA = –20 to +70 ˚C, AVCC = DVCC = 5.0 ±0.3 V) Parameter Supply current Resolution Non-linearity Symbol ICC RES NL VCC = 5.0 V, TA = 25 ˚C VIN = 1.0 Vp-p, fsamp = 20 MHz VCC = 5.0 V, TA = 25 ˚C VIN = 1.0 Vp-p, fsamp = 20 MHz fsamp = 14.318 MHz NTSC ramp wave (40 IRE) fsamp = 14.318 MHz NTSC ramp wave (40 IRE) Delay time from rising edge of sampling clock. DB1 to DB8, OVER, CL = 15 pF IOL = 1.6 mA DB1 to DB8, OVER IOH = –400 µA DB1 to DB8, OVER VIN = 0.8 V VIN = 2.0 V Measure input current from analog input pin VCC = 5.0 V VCC = 5.0 V VIN = VRB 2.1 3.1 10 2.7 12 1.5 Conditions VCC = 5.0 V, TA = 25 ˚C MIN. 26 TYP. 43 8 ± 1.5 ± 0.5 MAX. 62 Unit mA bit LSB Differential non-linearity DNL LSB Differential gain DG 3 % Differential phase DP 0.8 3 deg Digital data output delay time tD 20 35 ns Digital output low level voltage VOL 0.4 V Digital output high level voltage VOH V Digital input low level current Digital input high level current Analog input current IINDL IINDH IINA –200 10 35 µA µA µA V V pF Reference voltage (Bottom) Reference voltage (Top) Analog input equivalent capacitance Clock input equivalent capacitance Reference voltage (Difference) VRB VRT CIN 2.3 3.3 3 2.5 3.5 CCLK 2 pF VREF VRT – VRB, VCC = 5.0 V 1 V Caution The values of ICC and tD are different between the µPC659 and the µPC659A 7 µPC659A Test Circuit 8-bit digital data output DGND DGND OVER Clock 0.01µF 47 µ F + +5 V 24 23 22 21 20 19 18 17 16 15 14 13 DGND µ PC659AGS 1 2 3 4 5 6 7 8 9 10 11 12 + + 2.2 µF + V 0.01 µ F AGND 0.01 µ F 47 µF 2.2 µF 0.01 µF V +5 V Clamp pulse input Analog data input AGND AGND AGND DGND DG, DP Test Block Video signal generator Video signal µPC659A 8-bit digital data High-precision Video signal D/A converter Vector scope Clock 4fsc (14.318 MHz) Remark The video signal from the video signal generator is NTSC, 40 IRE ramp signal. 8 µPC659A Timing Chart tPWH CLK tPWL n+1 Data acquisition VIN n+2 5.3 ns TYP. 20 ns TYP. DB1 to DB8 OVER n–1 n n+1 n+2 Analog signal is captured at the rising edge, and converted data will be output at the rising edge after 1 clock pulseNote. Note For the µ PC659, 2 clock pulses. Caution The value of data output delay time (tD) is different between the µPC659 and the µPC659A. 9 µPC659A Output Code for Analog Input Output digital code Analog input OVER VRB to 1/2 LSB 1/2 LSB to (1 + 1/2) LSB to (254 + 1/2) LSB to (255 + 1/2) LSB (255 + 1/2) LSB to VRT VRT to AVCC 0 0 to 0 1 1 DB1 (MSB) 0 0 to 1 1 1 DB2 0 0 to 1 1 1 DB3 0 0 to 1 1 1 DB4 0 0 to 1 1 1 DB5 0 0 to 1 1 1 DB6 0 0 to 1 1 1 DB7 0 0 to 1 1 1 DB8 (LSB) 0 1 to 1 1 1 · VRT – VRB = 3.906 mV TYP., VRB = 2.3 V TYP., VRT = 3.3 V TYP. · Remark LSB = · · 256 APPLICATION CIRCUIT EXAMPLE 4fsc Clock input DGND AVCC (+5 V) 47 µF + 2.2 µF + 0.01 µF 22 Ω 100 µF + 1 VRT 2 NC 3 AVCC 4 VIN 5 AGND 6 PCL 7 VCL 8 AVCC CLK 24 OVER 23 DB1 22 DB2 21 DB3 20 DGND 19 DVCC 18 DB4 17 DB5 16 DB6 15 DB7 14 DB8 13 + 15 kΩ 1 kΩ 10 µF + OVER DB1 to DB8 51 Ω AGND AGND 4.7 kΩ 0.01 µ F 47 µ F AGND AGND 15 kΩ + 9 AGND VR1 20 kΩ 2.2 µF 10 VRB 11 AVCC 12 AGND Clamp pulse 2.2 µF + 0.01 µF 2 kΩ AGND DVCC (+5 V) DGND AGND DGND Remarks 1. VR1: Clamp voltage adjustment 2. Must be thick line wiring for the power supply lines. And reduce the resistance and reactance ingredient. AVCC and DVCC must be connected at one point. AGND and DGND must be connected at one point. 10 µPC659A ATTENTION FOR APPLICATION • Converted data output Analog signal is captured at the rising edge, and converted data will be output at the rising edge after 1 clock pulse. For the µPC659, 2 clock pulses. • Analog input terminal In case the pedestal level is clamped, the clamp circuit uses the soft clamp circuit to protect the burst level. However, if a high impedance output is connected to the VIN pin (pin 4), the burst level will be reduced (for example, for an external impedance of 10 Ω, the burst level is reduced by approx. 3 %). Therefore, connect the lowest possible impedance signal to the analog signal input pin. VIN 4 Clamp pulse 6 Low output impedance buffer PCL µPC659A 7 Clamp voltage VCL AGND • If don’s use the clamp circuit PCL pin (pin 6) and GND must be short-circuit. And insert by-pass capacitor of about 0.1 µF between the VCL pin (pin 7) and GND. Input analog signal to VIN pin (pin 4). In case an external clamp circuit is used, connect the PCL pin (pin 6) to GND, and leave the VCL pin (pin 7) unconnected. Set the voltage of the VIN pin (pin 4) between 2.3 V and 3.3 V. • Clamp voltage There is a few difference clamp voltage between the supply clamp voltage VCL (pin 7) and really clamp voltage. Really clamp voltage = VCL + α Take account of the α (about ± 20 mV) at supply VCL to pin 7. • When reference voltage is set from external, VRB (pin 10) = 2.3 V, VRT (pin 1) = 3.3 V . • Circuit current TYP. (Unit: mA) Analog circuit current Digital circuit current Sum 37 6 43 • Set the sampling clock frequency between 1 MHz and 20 MHz. If a frequency outside this range is used, the internal sample-and-hold circuit will not function properly. • First apply 5 V to the AVCC pins (pins 3 and 11) and the DVCC pin (pin 18), then input the analog signal to the VIN pin (pin 4). If the analog signal is input first, the output data may latch up. 11 µPC659A DIFFERENCE BETWEEN THE µPC659 AND THE µPC659A The following table shows the differences between the µPC659 and the µPC659A. This should be taken into consideration when using the µPC659A instead of the µPC659. Parameter Supply current VCC = 5.0 V TA = 25 ˚C Digital data output delay time Internal reference resistance VRT pin (pin 1), VRB pin (pin 10 ) tD ICC MIN. TYP. MAX. TYP. MAX. µPC659 50 mA 79 mA 110 mA 12 ns 20 ns µPC659A 26 mA 43 mA 62 mA 20 ns 35 ns AVCC 844 Ω VRT 1 480 Ω VRT 1 AVCC 1.41 kΩ 800 Ω 10 VRB 1.15 kΩ AGND AGND 1.91 kΩ AGND AGND 10 VRB Timing chart CLK CLK VIN Data output VIN n–2 n–1 n Data output n–1 n 12 µPC659A PACKAGE DRAWING 24 PIN PLASTIC SOP (300 mil) 24 13 detail of lead end 1 A 12 H G P I J F K E C D M M N B L NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 15.54 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 –0.05 0.1±0.1 1.8 MAX. 1.55 7.7±0.3 5.6 1.1 0.20 +0.10 –0.05 0.6±0.2 0.12 0.10 ° 3 ° +7° –3 INCHES 0.612 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 –0.003 0.004±0.004 0.071 MAX. 0.061 0.303±0.012 0.220 0.043 0.008 +0.004 –0.002 0.024 +0.008 –0.009 0.005 0.004 ° 3 ° +7° –3 P24GM-50-300B-4 13 µPC659A RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Surface mount device µPC659AGS : 24-pin plastic SOP (300 mil) Process Infrared ray reflow Conditions Peak temperature: 235 ˚C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 ˚C or higher), Maximum number of reflow processes: 2 times. Peak temperature: 215 ˚C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 ˚C or higher), Maximum number of reflow processes: 2 times. Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less, Pre-heating temperature: 120 ˚C or below (Package surface temperature), Maximum number of flow processes: 1 time. Pin terminal temperature: 300 ˚C or below, Heat time: 3 seconds or less (Per each side of the device). Symbol IR35-00-2 Vapor phase soldering VP15-00-2 Wave Soldering WS60-00-1 Partial heating method – Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the device will be damaged by heat stress. 14 µPC659A [MEMO] 15 µPC659A The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2