UPC8105GR-E1

SILICON MMIC QUADRATURE MODULATOR FEATURES • WIDE SUPPLY VOLTAGE RANGE: 2.7 ~ 5.5 V • BROADBAND OPERATION: MODOUT = 100 - 400 MHz, I/Q = DC to 10 MHz • INTERNAL 90° PHASE SHIFTER • POWER SAVE FUNCTION • LOW POWER CONSUMPTION: 16 mA Typ. @ 3 V • SMALL SSOP 16 PACKAGE • TAPE AND REEL PACKAGING AVAILABLE φ 90˚ 0˚ UPC8105GR FUNCTIONAL BLOCK DIAGRAM LO I I Q Q DESCRIPTION The UPC8105GR Silicon MMIC I/Q Modulator is manufactured using the NESAT III MMIC process. The NESAT III process produces transistors with fT approaching 20 GHz. The device was designed for use in Digital Mobile Communications circuits such as 900 MHz Digital Cordless and Cellular Phones, WLAN and PCN/PCS Handset Transmitters. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, VPS ≥ 1.8 V) PART NUMBER PACKAGE OUTLINE SYMBOLS ICC PMOD LOLEAK ImR IM3I/Q RLIN ZI/Q TPS(RISE) TPS (FALL) PARAMETERS AND CONDITIONS Total Circuit Current (no signal) VPS ≥ 1.8 V VPS ≤ 1.0 V UNITS mA µA dBm dBc dBc dBc dB kΩ µS µS MIN 10 -21 UPC8105GR S16 (SSOP 16) TYP 16 0.1 -16.5 -40 -40 -50 20 20 2 2 MAX 21 5 -12 -30 -30 Output Power - Modulator Local Oscillator Leakage VI/Q = 1.5 V (DC) Image Rejection + 500 mVp-p (AC) I/Q 3rd Order Intermodulation Distortion I/Q LO Input Return Loss Input Impedance I and Q Port Power Save Rise Time VPS ≤ 1.0 V to VPS ≥ 1.8V Power Save Fall Time VPS ≥1.8 V to VPS ≤1.0 V 5 5 California Eastern Laboratories UPC8105GR ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C) SYMBOLS VCC VPS PD TOP TSTG PARAMETERS Supply Voltage Enable Voltage for Power Save Power Dissipation2 Operating Temperature Storage Temperature UNITS V V mW °C °C RATINGS 6.0 6.0 530 -40 to +85 -65 to +150 RECOMMENDED OPERATING CONDITIONS SYMBOLS VCC TOP fMODOUT fLOIN fI/QIN PARAMETERS Supply Voltage Operating Temperature UNITS MIN TYP MAX V °C 2.7 -40 100 100 DC 3.0 5.5 +25 +85 400 400 10 Modulator Output Frequency MHz LO1 Input Frequency1 MHz MHz Notes: 1. Operation in excess of any one of these parameters may result in permanent damage. 2. Mounted on a 50x50x1.6 mm double copper clad epoxy glass PWB (TA = 85°C). I/Q Input Frequency2 Notes: 1. PLOIN = -10 dBm. 2. PI/QIN = 600 mVp-p max. TYPICAL PERFORMANCE CURVES (TA = 25°C, VCC = VPS = 3 V, I/Q DC Offset = I/Q DC Offset = 1.5 V, I/Q Input Signal = 500 mVp-p (Single-ended), PLOIN = -10 dBm unless otherwise specified) MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs.LO INPUT POWER -10 MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs. LO INPUT FREQUENCY -10 -10 Modulator Output Power, PMODOUT (dBm) Modulator Output Power, PMODOUT (dBm) LO Leakage, LOL ; Image Rejection, ImR; IM3 I/Q (dBc) LO Leakage, LOL; Image Rejection, ImR; IM3 I/Q (dBc) POUT -20 IMR POUT -10 -20 LOL -30 -40 -50 -60 -70 -30 -30 -20 -20 -30 -30 -40 LOL -40 IMR -40 -50 IM3 I/O -50 IM3 I/O -20 -10 0 -50 +10 -60 -60 -70 50 100 200 500 -70 LO Input Power, PLOIN (dBm) LO Input Frequency, fLO (MHz) MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs. I/Q INPUT SIGNAL -10 Modulator Output Power, PMODOUT (dBm) LO Leakage, LOL ; Image Rejection, ImR; IM3 I/Q (dBc) POUT -10 -20 -30 LOL -40 -50 -60 -70 0 0.5 1 IMR -20 -30 -40 IM3 I/Q -50 I/Q Input Signal, P I/QIN (Vp-p) UPC8105GR PIN FUNCTIONS Pin No. 1 Symbol LOIN Supply Voltage — Pin Voltage 0 Description LO input for the phase shifter. This input impedance is internally matched to 50 Ω. Bypass of the LO input.This pin is grounded through an internal capacitor. For a single-ended design this pin should be left open. Connect to ground with minimum inductance. Track length should be kept as short as possible. VCC/2*2 — Input for I signal. This input impedance is larger than 20 kΩ. The relationship between the amplitude and the DC bias of the input signal are as follows: *1 VCC/2 (V) Amp. (mVp-p) ≥1.35 400 ≥1.5 600 ≥1.75 1000 Input for I signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. Input for Q signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. Input for Q signal. This input impedance is larger than 20 kΩ. The relationship between the amplitude and the DC bias of the input signal are as follows: VCC/2 (V) ≥1.35 ≥1.5 ≥1.75 12 MODOUT — Amp. (mVp-p) 400 600 1000 1 50 Ω Equivalent Circuit 2 LOIN (Bypass) — 2 3 8 GND 4 I 4 5 5 I VCC/2*2 — 6 Q VCC/2*2 — 7 Q VCC/2*2 — 7 6 Output from the modulator. This is emitter follower output. Connect approx. 15 Ω in series to match to 50 Ω. 12 *1: In case I/Q input signals are single ended. I/Q signal inputs can be used either single-ended or differentially with proper terminations. *2: VCC/2 DC bias must be supplied to I, I, Q, Q. UPC8105GR PIN FUNCTIONS Pin No. 13 14 Symbol GND Supply Voltage 0 Pin Voltage — Description Connect to the ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can control the On/Sleep state with bias as follows: VPS (V) 1.8~5.5 0~1.0 16 VCC 2.7~5.5 — STATE ON SLEEP Equivalent Circuit 15 VPS (Power Save) VPS 15 Supply voltage pin for the modulator. An internal regulator helps keep the device stable against temperature or VCC variation. MODULATOR INTERNAL FUNCTIONS Block Function/Operation Block Diagram from LOin Input signal from LO is sent to a T-type flip-flop through a frequency doubler. The output signal from the T-type F/F is changed to the same frequency as LO input with a quadrature phase shift of 0°, 90°, 180°, or 270°. These circuits provide self phase correction for proper quadrature signals. 90° Phase Shifter x2 . .2 F/F Buffer Amplifier Buffer amplifiers for each phase signal are sent to each mixer. Mixer Each signal from the buffer amps is quadrature modulated with two doublebalanced mixers. High accurate phase and amplitude inputs are realized to provide excellent image rejection. I I Q Q Adder Output signal from each mixer is added and sent through a final amplifier stage to pin 16 for further off-chip filtering if necessary. To MODout UPC8105GR INTERNAL BLOCK DIAGRAM 1 2 3 4 5 6 7 8 16 VCC REG 15 V PS (POWER SAVE) GND I I Q Q GND OUTLINE DIMENSIONS (Units in mm) PACKAGE OUTLINE SSOP 16 LO1 IN LO1 IN 90˚ Phase Shifter 16 9 14 GND 13 GND 12 MOD OUT 11 N.C. 10 N.C. 9 N.C. 1.44 1.8 Max 0.1±0.1 1 NEC C8105G XXXXX 8 5.50 Max XXX = Lot/Date Code 6.2±0.3 4.4±0.2 +0.10 0.15 -0.05 0.9±0.2 0.65 0.20±0.10 0.475 Max 0.5±0.2 ORDERING INFORMATION PART NUMBER UPC8105GR-E1 Note: Embossed Tape, 12 mm wide. QUANTITY 2500/Reel LEAD CONNECTIONS 1. LOIN 2. LOIN 3. GND 4. I Input 5. I Input 6. Q Input 7. Q Input 8. GND 9. N.C. 10. N.C. 11. N.C. 12. MODOUT 13. GND 14. GND 15. VPS (Power Save) 16. VCC All dimensions are typical unless specified otherwise. APPLICATION CIRCUIT Low-noise Transistor RX DEMO I Q VCO SW +N PLL PLL UPC8105GR I 0˚ TX PA UPC8106T Phase Shifter 90˚ Q EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -3/97 DATA SUBJECT TO CHANGE WITHOUT NOTICE