UPC8181TB

DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC8181TB 3 V, SILICON MMIC MEDIUM OUTPUT POWER AMPLIFIER FOR MOBILE COMMUNICATIONS DESCRIPTION The µPC8181TB is a silicon monolithic integrated circuit designed as amplifier for mobile communications. This IC operates at 3 V. The medium output power is suitable for RF-TX of mobile communications system. This IC is manufactured using NEC’s 30 GHz fmax UHS0 (Ultra High Speed Process) silicon bipolar process. This process uses direct silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent corrosion/migration. Thus, this IC has excellent performance, uniformity and reliability. FEATURES • Supply voltage • Circuit current • Medium output power : VCC = 2.7 to 3.3 V : ICC = 23.0 mA TYP. @ VCC = 3.0 V : PO(1dB) = +8.0 dBm TYP. @ f = 0.9 GHz PO(1dB) = +7.0 dBm TYP. @ f = 1.9 GHz PO(1dB) = +7.0 dBm TYP. @ f = 2.4 GHz • Power gain : GP = 19.0 dB TYP. @ f = 0.9 GHz GP = 21.0 dB TYP. @ f = 1.9 GHz GP = 22.0 dB TYP. @ f = 2.4 GHz • Upper limit operating frequency • High-density surface mounting : fu = 4.0 GHz TYP. @ 3 dB bandwidth (Standard value) : 6-pin super minimold package (2.0 × 1.25 × 0.9 mm) APPLICATION • Buffer amplifiers on 1.9 to 2.4 GHz mobile communications system. ORDERING INFORMATION Part Number Package 6-pin super minimold Marking C3E Supplying Form • Embossed tape 8 mm wide • 1, 2, 3 pins face the perforation side of the tape • Qty 3 kpcs/reel µPC8181TB-E3 Remark To order evaluation samples, please contact your local NEC sales office. Part number for sample order: µPC8181TB Caution Electro-static sensitive devices The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P15114EJ2V0DS00 (2nd edition) Date Published July 2001 N CP(K) Printed in Japan The mark shows major revised points. © 2000, 2001 µPC8181TB PRODUCT LINE-UP (TA = +25°C, VCC = Vout = 3.0 V, ZS = ZL = 50 Ω) fu (GHz) 4.0 PO(1 dB) (dBm) +8.0 @ f = 0.9 GHz +7.0 @ f = 1.9 GHz +7.0 @ f = 2.4 GHz GP (dB) 19.0 @ f = 0.9 GHz 21.0 @ f = 1.9 GHz 22.0 @ f = 2.4 GHz 21.5 @ f = 0.9 GHz 20.5 @ f = 1.9 GHz 20.5 @ f = 2.4 GHz 13.0 @ f = 0.9 GHz 15.5 @ f = 1.9 GHz 20.0 @ f = 0.9 GHz 21.0 @ f = 1.9 GHz 21.0 @ f = 0.9 GHz 21.0 @ f = 1.5 GHz 36.0 27.0 26.5 6-pin minimold 6-pin super minimold 6-pin minimold 6-pin super minimold 6-pin minimold 6-pin super minimold C2H C2A C1Z 30.0 6-pin super minimold C3F ICC (mA) 23.0 Part No. Package 6-pin super minimold Marking C3E µPC8181TB µPC8182TB 2.9 +9.5 @ f = 0.9 GHz +9.0 @ f = 1.9 GHz +8.0 @ f = 2.4 GHz µPC2762T µPC2762TB µPC2763T µPC2763TB µPC2771T µPC2771TB 2.9 +8.0 @ f = 0.9 GHz +7.0 @ f = 1.9 GHz 2.7 +9.5 @ f = 0.9 GHz +6.5 @ f = 1.9 GHz 2.2 +11.5 @ f = 0.9 GHz +9.5 @ f = 1.5 GHz Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. Caution The package size distinguishes between minimold and super minimold. SYSTEM APPLICATION EXAMPLE Digital cellular telephone RX I Q DEMOD. ÷N SW PLL PLL I 0° TX PA : µ PC8181TB applicable φ 90° Q Caution The insertion point is different due to the specifications of conjunct devices. 2 Data Sheet P15114EJ2V0DS µPC8181TB PIN CONNECTIONS (Top View) 3 2 1 (Bottom View) 4 5 6 4 5 6 3 2 1 Pin No. 1 Pin Name INPUT GND GND OUTPUT GND VCC C3E 2 3 4 5 6 PIN EXPLANATION Applied Voltage (V) – Pin Voltage (V) Note Pin No. Pin Name Function and Applications Internal Equivalent Circuit 1 INPUT 0.99 Signal input pin. A internal matching circuit, configured with resistors, enables 50 Ω connection over a wide band. A multi-feedback circuit is designed to cancel the deviations of hFE and resistance. This pin must be coupled to signal source with capacitor for DC cut. Ground pin. This pin should be connected to system ground with minimum inductance. Ground pattern on the board should be formed as wide as possible. All the ground pins must be connected together with wide ground pattern to decrease impedance difference. Signal output pin. The inductor must be attached between VCC and output pins to supply current to the internal output transistors. 6 2 3 5 GND 0 – 4 1 4 OUTPUT Voltage as same as VCC through external inductor 2.7 to 3.3 – 3 2 5 6 VCC – Power supply pin, which biases the internal input transistor. This pin should be externally equipped with bypass capacitor to minimize its impedance. Note Pin voltage is measured at VCC = 3.0 V. Data Sheet P15114EJ2V0DS 3 µPC8181TB ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Total Circuit Current Power Dissipation Operating Ambient Temperature Storage Temperature Input Power Symbol VCC ICC PD TA Tstg Pin TA = +25°C Conditions TA = +25°C, pin 4 and pin 6 TA = +25°C TA = +85°C Note Ratings 3.6 60 270 −40 to +85 −55 to +150 +10 Unit V mA mW °C °C dBm Note Mounted on double copper clad 50 × 50 × 1.6 mm epoxy glass PWB RECOMMENDED OPERATING RANGE Parameter Supply Voltage Symbol VCC MIN. 2.7 TYP. 3.0 MAX. 3.3 Unit V Remark Same voltage should be applied to pin 4 and pin 6. 4 Data Sheet P15114EJ2V0DS µPC8181TB ELECTRICAL CHARACTERISTICS (Unless otherwise specified, TA = +25°C, VCC = Vout = 3.0 V, ZS = ZL = 50 Ω) Parameter Circuit Current Power Gain Symbol ICC GP No signal f = 0.9 GHz, Pin = −30 dBm f = 1.9 GHz, Pin = −30 dBm f = 2.4 GHz, Pin = −30 dBm Noise Figure NF f = 0.9 GHz f = 1.9 GHz f = 2.4 GHz Isolation ISL f = 0.9 GHz, Pin = −30 dBm f = 1.9 GHz, Pin = −30 dBm f = 2.4 GHz, Pin = −30 dBm Input Return Loss RLin f = 0.9 GHz, Pin = −30 dBm f = 1.9 GHz, Pin = −30 dBm f = 2.4 GHz, Pin = −30 dBm Output Return Loss RLout f = 0.9 GHz, Pin = −30 dBm f = 1.9 GHz, Pin = −30 dBm f = 2.4 GHz, Pin = −30 dBm Gain 1 dB Compression Output Power PO(1dB) f = 0.9 GHz f = 1.9 GHz f = 2.4 GHz Saturated Output Power PO(sat) f = 0.9 GHz, Pin = −5 dBm f = 1.9 GHz, Pin = −5 dBm f = 2.4 GHz, Pin = −5 dBm Upper Limit Operating Frequency fu 3 dB down below from gain at f = 0.1 GHz Conditions MIN. − 17.0 18.0 19.0 − − − 28.0 27.0 26.5 5.5 8.5 9.0 6.5 7.5 9.0 +6.0 +4.5 +4.5 − − − − TYP. 23.0 19.0 21.0 22.0 4.5 4.5 4.5 33.0 32.0 31.5 7.5 10.5 11.0 9.0 10.0 12.0 +8.0 +7.0 +7.0 +9.5 +9.0 +9.0 4.0 MAX. 30.0 22.0 24.0 25.0 6.0 6.0 6.0 − − − − − − − − − − − − − − − − GHz dBm dBm dB dB dB dB Unit mA dB Data Sheet P15114EJ2V0DS 5 µPC8181TB TEST CIRCUIT VCC 1 000 pF C3 6 50 Ω IN 1 000 pF C1 1 4 L C2 1 000 pF 50 Ω OUT 2, 3, 5 COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS Type C1, C2 C3 L Bias Tee Capacitor Bias Tee Value 1 000 pF 1 000 pF 1 000 nH EXAMPLE OF ACTUAL APPLICATION COMPONENTS Type C1 to C3 L Chip capacitor Chip inductor Value 1 000 pF 100 nH 10 nH Operating Frequency 100 MHz or higher 100 MHz or higher 2.0 GHz or higher INDUCTOR FOR THE OUTPUT PIN The internal output transistor of this IC consumes 20 mA, to output medium power. To supply current for output transistor, connect an inductor between the Vcc pin (pin 6) and output pin (pin 4). Select large value inductance, as listed above. The inductor has both DC and AC effects. In terms of DC, the inductor biases the output transistor with minimum voltage drop to output enable high level. In terms of AC, the inductor make output-port-impedance higher to get enough gain. In this case, large inductance and Q is suitable. For above reason, select an inductance of 100 Ω or over impedance in the operating frequency. The gain is a peak in the operating frequency band, and suppressed at lower frequencies. The recommendable inductance can be chosen from example of actual application components list as shown above. CAPACITORS FOR THE VCC, INPUT, AND OUTPUT PINS Capacitors of 1 000 pF are recommendable as the bypass capacitor for the Vcc pin and the coupling capacitors for the input and output pins. The bypass capacitor connected to the Vcc pin is used to minimize ground impedance of Vcc pin. So, stable bias can be supplied against Vcc fluctuation. The coupling capacitors, connected to the input and output pins, are used to cut the DC and minimize RF serial impedance. Their capacitance are therefore selected as lower impedance against a 50 Ω load. The capacitors thus perform as high pass filters, suppressing low frequencies to DC. To obtain a flat gain from 100 MHz upwards, 1 000 pF capacitors are used in the test circuit. In the case of under 10 MHz operation, increase the value of coupling capacitor such as 10 000 pF. Because the coupling capacitors are determined by equation, C = 1/(2πRfc). 6 Data Sheet P15114EJ2V0DS µPC8181TB ILLUSTRATION OF THE TEST CIRCUIT ASSEMBLED ON EVALUATION BOARD AMP-2 Top View 3 1 IN → 5 4 OUT C L 2 C 3E C Mounting direction VCC C COMPONENT LIST Value C L 1 000 pF Example: 10 nH 6 Remarks 1. 30 × 30 × 0.4 mm double sided copper clad polyimide board. 2. Back side: GND pattern 3. Solder plated on pattern 4. : Through holes Data Sheet P15114EJ2V0DS 7 µPC8181TB TYPICAL CHARACTERISTICS (Unless otherwise specified, TA = +25°C) CIRCUIT CURRENT vs. OPERATING AMBIENT TEMPERATURE 40 No signal 35 Circuit Current ICC (mA) Circuit Current ICC (mA) 30 25 20 15 10 5 0 0 1 2 3 4 Supply Voltage VCC (V) 35 30 25 20 15 10 5 0 −60 −40 −20 0 +20 +40 +60 +80 +100 No signal VCC = 3.0 V CIRCUIT CURRENT vs. SUPPLY VOLTAGE 40 Operating Ambient Temperature TA (°C) NOISE FIGURE, POWER GAIN vs. FREQUENCY 30 VCC = 3.3 V 25 Noise Figure NF (dB) Power Gain GP (dB) GP 20 VCC = 2.7 V 15 10 NF 5 0 0.1 VCC = 2.7 V 0.3 1.0 3.0 VCC = 3.3 V VCC = 3.0 V VCC = 3.0 V Power Gain GP (dB) 25 20 15 10 5 0 0.1 30 POWER GAIN vs. FREQUENCY VCC = 3.0 V TA = −40°C TA = +25°C TA = −85°C 5 4 3 0.3 1.0 3.0 Frequency f (GHz) Frequency f (GHz) ISOLATION vs. FREQUENCY 0 −10 IsoIation ISL (dB) −20 −30 −40 −50 0.1 VCC = 3.0 V Input Return Loss RLin (dB) Output Return Loss RLout (dB) INPUT RETURN LOSS, OUTPUT RETURN LOSS vs. FREQUENCY 0 −10 RLout −20 −30 −40 −50 VCC = 3.0 V RLin 0.3 1.0 3.0 0.1 0.3 1.0 3.0 Frequency f (GHz) Frequency f (GHz) 8 Data Sheet P15114EJ2V0DS µPC8181TB OUTPUT POWER vs. INPUT POWER +15 +10 Output Power Pout (dBm) +5 0 −5 −10 −15 −20 −25 −30 −50 −40 −30 −20 −10 0 +10 VCC = 3.0 V f = 0.9 GHz +15 VCC = 3.3 V Output Power Pout (dBm) +10 VCC = 2.7 V +5 0 −5 −10 −15 −20 −25 −30 −50 −40 −30 −20 −10 0 +10 TA = +25°C f = 0.9 GHz VCC = 3.0 V OUTPUT POWER vs. INPUT POWER TA = +85°C TA = −40°C Input Power Pin (dBm) Input Power Pin (dBm) OUTPUT POWER vs. INPUT POWER +15 +10 Output Power Pout (dBm) +5 0 −5 −10 −15 −20 −25 −30 −50 −40 −30 −20 −10 0 +10 VCC = 3.0 V VCC = 2.7 V f = 1.9 GHz VCC = 3.3 V Output Power Pout (dBm) +15 +10 +5 0 −5 −10 −15 −20 −25 OUTPUT POWER vs. INPUT POWER f = 1.9 GHz VCC = 3.0 V TA = +85°C TA = −40°C TA = +25°C −30 −50 −40 −30 −20 −10 0 +10 Input Power Pin (dBm) Input Power Pin (dBm) OUTPUT POWER vs. INPUT POWER +15 +10 Output Power Pout (dBm) +5 0 −5 −10 −15 −20 −25 −30 −50 −40 −30 −20 −10 0 +10 VCC = 2.7 V VCC = 3.0 V f = 2.4 GHz VCC = 3.3 V Output Power Pout (dBm) +15 +10 +5 0 −5 −10 −15 −20 −25 OUTPUT POWER vs. INPUT POWER f = 2.4 GHz VCC = 3.0 V TA = +85°C TA = −40°C TA = +25°C −30 −50 −40 −30 −20 −10 0 +10 Input Power Pin (dBm) Input Power Pin (dBm) Data Sheet P15114EJ2V0DS 9 µPC8181TB OUTPUT POWER vs. INPUT POWER +15 +10 Output Power Pout (dBm) +5 0 −5 −10 −15 −20 −25 −30 −50 −40 −30 −20 −10 0 +10 f = 0.9 GHz f = 1.9 GHz VCC = 3.0 V SATURATED OUTPUT POWER vs. FREQUENCY Saturated Output Power PO(sat) (dBm) +12 VCC = 3.3 V +10 +8 +6 +4 +2 0 0.1 VCC = 3.0 V f = 2.4 GHz VCC = 2.7 V 0.3 1.0 3.0 Input Power Pin (dBm) Frequency f (GHz) 3rd Order Intermoduration Distortion IM3 (dBc) 60 50 40 30 VCC = 2.7 V 20 10 0 −15 3rd Order Intermoduration Distortion IM3 (dBc) 3RD ORDER INTERMODULATION DISTORTION vs. OUTPUT POWER OF EACH TONE f1 = 900 MHz f2 = 902 MHz 3RD ORDER INTERMODULATION DISTORTION vs. OUTPUT POWER OF EACH TONE 60 50 40 VCC = 3.0 V 30 20 VCC = 2.7 V 10 0 −15 f1 = 1 900 MHz f2 = 1 902 MHz VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V −10 −5 0 +5 +10 +15 −10 −5 0 +5 +10 Output Power of Each Tone PO(each) (dBm) Output Power of Each Tone PO(each) (dBm) 3rd Order Intermoduration Distortion IM3 (dBc) 3RD ORDER INTERMODULATION DISTORTION vs. OUTPUT POWER OF EACH TONE 60 50 40 VCC = 3.3 V 30 VCC = 2.7 V 20 10 0 −15 VCC = 3.0 V f1 = 2 400 MHz f2 = 2 402 MHz −10 −5 0 +5 +10 Output Power of Each Tone PO(each) (dBm) Remark The graphs indicate nominal characteristics. 10 Data Sheet P15114EJ2V0DS µPC8181TB S-PARAMETERS (VCC = Vout = 3.0 V) S11-Frequency 0.1 G 2.0 G 4.0 G 3.0 G 1.0 G S22-Frequency 0.1 G 1.0 G 3.0 G 4.0 G 2.0 G 1 Data Sheet P15114EJ2V0DS 11 µPC8181TB TYPICAL S-PARAMETER VALUES (TA = +25°C) VCC = Vout = 3.0 V, ICC = 23 mA FREQUENCY MHz 100.0000 200.0000 300.0000 400.0000 500.0000 600.0000 700.0000 800.0000 900.0000 1000.0000 1100.0000 1200.0000 1300.0000 1400.0000 1500.0000 1600.0000 1700.0000 1800.0000 1900.0000 2000.0000 2100.0000 2200.0000 2300.0000 2400.0000 2500.0000 2600.0000 2700.0000 2800.0000 2900.0000 3000.0000 3100.0000 3200.0000 3300.0000 3400.0000 3500.0000 3600.0000 3700.0000 3800.0000 3900.0000 4000.0000 4100.0000 S11 MAG. 0.452 0.467 0.470 0.460 0.438 0.415 0.397 0.395 0.399 0.404 0.396 0.394 0.385 0.368 0.347 0.335 0.327 0.328 0.327 0.325 0.316 0.295 0.288 0.291 0.303 0.317 0.335 0.349 0.347 0.345 0.341 0.331 0.323 0.311 0.302 0.289 0.266 0.253 0.238 0.238 0.244 ANG. −2.7 −5.7 −7.5 −9.3 −11.5 −14.7 −18.6 −22.4 −25.6 −28.1 −29.0 −28.5 −28.0 −28.8 −29.5 −30.9 −31.5 −31.2 −29.4 −29.4 −28.5 −29.4 −30.8 −34.1 −38.3 −41.1 −41.3 −41.0 −39.4 −43.2 −45.4 −47.9 −49.8 −52.1 −52.6 −54.9 −56.5 −61.5 −65.6 −70.7 −74.0 MAG. 9.078 9.098 9.143 9.237 9.284 9.442 9.670 9.897 10.166 10.496 10.903 11.329 11.895 12.145 12.356 12.670 12.966 13.410 13.722 14.151 14.412 14.747 15.144 15.463 15.264 15.137 14.774 14.176 13.710 12.808 12.313 11.587 11.003 10.638 10.228 9.985 9.543 9.184 8.816 8.488 8.186 S21 ANG. −2.0 −4.9 −6.9 −10.1 −11.9 −14.6 −17.0 −19.7 −22.7 −26.0 −29.0 −32.8 −37.9 −42.4 −47.6 −51.8 −56.4 −61.4 −66.8 −72.3 −78.1 −84.1 −90.3 −97.4 −104.6 −112.6 −119.8 −127.7 −133.7 −139.8 −146.0 −149.3 −154.5 −157.7 −162.0 −166.5 −170.1 −174.5 −177.7 178.2 174.3 MAG. 0.020 0.021 0.021 0.021 0.021 0.022 0.022 0.022 0.023 0.022 0.023 0.025 0.025 0.024 0.025 0.026 0.024 0.026 0.027 0.026 0.028 0.027 0.029 0.029 0.029 0.028 0.029 0.031 0.029 0.029 0.031 0.029 0.031 0.031 0.029 0.030 0.030 0.031 0.030 0.032 0.032 S12 ANG. 4.3 4.2 8.2 9.8 11.4 8.1 11.5 16.3 14.5 13.4 18.0 16.6 17.4 22.0 24.3 20.6 21.4 23.2 27.5 24.6 26.4 26.5 27.5 27.1 27.7 25.5 25.5 25.0 32.9 24.8 28.9 31.6 31.2 29.5 32.5 31.4 39.6 34.1 36.2 38.9 37.0 MAG. 0.338 0.346 0.344 0.335 0.328 0.337 0.350 0.354 0.342 0.331 0.332 0.353 0.376 0.374 0.361 0.356 0.356 0.366 0.367 0.369 0.363 0.361 0.359 0.346 0.323 0.303 0.294 0.299 0.304 0.317 0.325 0.318 0.315 0.307 0.302 0.303 0.301 0.294 0.275 0.270 0.266 S22 ANG. −1.6 −2.1 −1.0 −2.7 −4.8 −7.5 −7.9 −6.8 −6.0 −7.9 −10.8 −13.4 −14.3 −15.0 −16.3 −19.3 −22.0 −23.9 −25.6 −28.5 −31.7 −35.4 −37.1 −39.0 −40.6 −43.1 −43.9 −43.0 −41.3 −44.9 −46.7 −48.7 −52.1 −56.1 −60.0 −63.7 −65.1 −67.5 −68.8 −71.0 −75.1 1.89 1.73 1.72 1.75 1.84 1.73 1.72 1.69 1.56 1.60 1.48 1.33 1.26 1.28 1.28 1.22 1.29 1.17 1.11 1.11 1.05 1.08 1.02 1.01 1.04 1.09 1.07 1.03 1.09 1.15 1.13 1.25 1.27 1.32 1.44 1.47 1.54 1.55 1.71 1.70 1.75 K 12 Data Sheet P15114EJ2V0DS µPC8181TB PACKAGE DIMENSIONS 6-PIN SUPER MINIMOLD (UNIT: mm) 2.1±0.1 1.25±0.1 2.0±0.2 1.3 0.65 0.65 0.1 MIN. 0.9±0.1 0.7 0 to 0.1 0.15+0.1 –0.05 0.2+0.1 –0.05 Data Sheet P15114EJ2V0DS 13 µPC8181TB NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation). All the ground pins must be connected together with wide ground pattern to decrease impedance difference. (3) The bypass capacitor should be attached to the VCC pin. (4) The inductor must be attached between VCC and output pins. The inductance value should be determined in accordance with desired frequency. (5) The DC cut capacitor must be attached to input and output pins. RECOMMENDED SOLDERING CONDITIONS This product should be soldered under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Soldering Method Infrared Reflow Soldering Conditions Package peak temperature: 235°C or below Time: 30 seconds or less (at 210°C) Count: 3, Exposure limit: NoneNote Package peak temperature: 215°C or below Time: 40 seconds or less (at 200°C) Count: 3, Exposure limit: NoneNote Soldering bath temperature: 260°C or below Time: 10 seconds or less Count: 1, Exposure limit: NoneNote Pin temperature: 300°C or below Time: 3 seconds or less (per side of device) Exposure limit: NoneNote Recommended Condition Symbol IR35-00-3 VPS VP15-00-3 Wave Soldering WS60-00-1 Partial Heating – Note After opening the dry pack, keep it in a place below 25°C and 65% RH for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 14 Data Sheet P15114EJ2V0DS µPC8181TB [MEMO] Data Sheet P15114EJ2V0DS 15 µPC8181TB ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES • The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4