PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µ PD160970
8-ch level shift driver IC
DESCRIPTION
The µ PD160970 is a level shift driver IC for LTPS (low-temperature polysilicon) TFT-LCDs featuring a 2-level output function and incorporates eight on-chip level shifters. This IC realizes a 20 V MAX. withstanding voltage due to a high-withstanding-voltage CMOS process and has an output ON-resistance and switching characteristics ideal for TFT driving in LCD panels.
FEATURES
• High withstanding voltage : 20 V (MAX.) • Supports low-voltage input (logic power supply voltage : 3.0 to 3.6 V) • Includes 8 level shifters (among which 2 circuits can switch between normal and inverted output) • Small thin package : 24-pin plastic TSSOP (5.72 mm (225) )
ORDERING INFORMATION
Part Number Package 24-pin plastic TSSOP (5.72 mm (225) )
µ PD160970MA-6A5
.
The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. Not all products and/or types are availabe in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S15857EJ4V0PM00 (4th edition) Date Published January 2003 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
2003
µ PD160970
1. BLOCK DIAGRAM / PIN CONFIGURATION
• 24-pin plastic TSSOP (5.72 mm (225) )
µ PD160970MA-6A5
2 values
VI1
1
L/S
2 values
24
VO1
VI2
2
L/S
23
VO2
VI3
3
22
VEE
VI4A
4
2 values
21
VCC
VI4B
5
L/S
2 values
20
VO3
VDD
6
L/S
2 values
19
VO4
VSS
7
L/S
2 values
18
VO5
VI5B
8
L/S
17
VO6
VI5A
9
16
VCC
VI6
10
2 values
15
VEE
VI7
11
L/S
2 values
14
VO7
VI8
12
L/S
13
VO8
L/S : Level shifter (VDD→VCC, VSS→VEE)
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Preliminary Product Information S15857EJ4V0PM
µ PD160970
2. PIN FUNCTIONS
Pin Name VI1 VI2 VI3 VI4A VI4BNote VDD VSS VI5BNote VI5A VI6 VI7 VI8 Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 − − Input Power supply for logic block Logic ground Logic input Input Logic input VO8 VO7 VEE VCC VO6 VO5 VO4 VO3 VCC VEE VO2 VO1 I/O Function Pin Name Pin Symbol 13 14 15 16 17 18 19 20 21 22 23 24 − − Output Negative power supply for high -withstanding-voltage block Positive power supply for high -withstand-voltage block High-withstanding-voltage output − − Output Output High-withstanding-voltage output Negative power supply for high -withstanding-voltage block Positive power supply for high -withstanding voltage block High-withstanding-voltage output I/O Function
Note Use the VI4B and VI5B pins at the DC level.
3. Relation of logic input and High-withstanding-voltage output
3.1 VI1 to VI3, VI6 to VI8
VIn L H VOn VCC VEE
High-withstanding-voltage output VCC
Logic input VDD VSS VEE
3.2 VI4A/VI4B, VI5A/VI5B
VInA L H L H VInB L (DC) H (DC) VOn VCC VEE VEE VCC
Preliminary Product Information S15857EJ4V0PM
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µ PD160970
4. Usage Cautions
(1) The power-on sequence is VSS → VDD → logic signal → VEE → VCC, and the power-off sequence is the reverse sequence. • VSS and VDD, and VEE and VCC can be powered on simultaneously. • To prevent an abnormal output operation, it is recommended to fix the logic input during the transition phase of VEE and VCC to either ”H” or ”L”.
VCC
VDD VSS
VEE
Logic signal
Remark The term “logic signal” as used above includes not only the rising edge/falling edge of the signal, but also “H” or “L” level input. (2) (3) (4) To ensure the switching characteristics of the VI4A/VI4B and VI5A/VI5B signal input, be sure to make the VI4B and VI5B pins DC input. Also, be sure to fix unused input pins to “H” or “L”. Perform thorough evaluation with the actual device for simultaneous switching of multiple output circuits, bearing in mind the allowable output current during switching. The output transistors in this device are designed for an impedance of several tens of ohms. Therefore, if driving a large load, IC malfunction and IC destruction or degradation may result owing to the influence of an output current of several hundred mAp-p per output. To prevent such malfunction from occurring, a number of countermeasures can be implemented, including the following. Use a large-capacitance decoupling capacitor with superior high-frequency characteristics. Insert in series a damping resistor for limiting the output current between the output pin and the load. Since the optimum values of constants differ depending on the equipment, determine the correct constants based on careful evaluation. (5) (6) Be sure to externally short power-supply pins for which several exist (VCC and VEE). Do not use the device with multiple output pons shorted. This may cause IC malfunction, destruction, or degradation.
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Preliminary Product Information S15857EJ4V0PM
µ PD160970
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter Logic Part Supply Voltage Positive power supply for high -withstanding-voltage block Negative power supply for high -withstanding-voltage block Bias power supply for high -withstanding-voltage block Input Voltage Output Voltage Operating Ambient Temperature Storage Temperature Power Dissipation VDD VCC VEE VCC -VEE VI VO TA Tstg Pd Symbol Rating −0.5 to +4.5 −0.5 to +17.0 −8.0 to +0.5 −0.5 to +25.0 −0.5 to VDD + 0.5 VEE − 0.5 to VCC + 0.5 −10 to +60 −40 to +125 500
Note
Unit V V V V V V °C °C mW
Note W hen a glass epoxy board (100 mm x 100 mm x 1.0 mm, copper-plated area of 15%) is mounted. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = −10 to +60°C, VSS = 0 V)
Parameter Supply Voltage Symbol VDD VCC VEE VCC -VEE Clock Frequency fCLK Conditions MIN. 3.0 9.5 −6.5 14.0 TYP. 3.3 11.5 −5.5 17.0 MAX. 3.6 13.5 −4.5 20.0 200 Unit V V V V kHz
Electrical Characteristics (TA = −10 to +60°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V, VCC = 11.5 V ± 1.0 V, VEE = −5.5 V ± 0.5 V, tr = tf ≤ 5.0 ns)
Parameter Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage Output ON Resistance Static Current Symbol VIL VIH VOL VOH RON IDD ICC Input Leak Current IIL CI Conditions All input pins All input pins IOL = +1.0 mA, All output pins IOH = −1.0 mA, All output pins IO = ±1.0 mA, All output pins VI = VSS no load VDD VCC −1.0 7 10.37 MIN. VSS 0.7 VDD −5.42 11.42 80 0.1 0.1 130 10 10 1.0 TYP.
Note
MAX. 0.2 VDD VDD −4.87
Unit V V V V Ω
µA µA µA
pF
VI = VDD or VSS, All input pins
5
Input Capacitance
Note The TYP. value is a reference value when TA = 25°C, VDD = 3.3 V, VCC = 11.5 V, VEE = −5.5 V. 5
Preliminary Product Information S15857EJ4V0PM
µ PD160970
Switching Characteristics (TA = −10 to +60°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V, VCC = 11.5 V ± 1.0 V, VEE = −5.5 V ± 0.5 V, tr = tf ≤ 5.0 ns)
Parameter Output delay time1 Symbol tPHL1 tPLH1 Output delay time2 tPHL2 tPLH2 Condition All output pins, no load, VO1-VO3, VO6-VO8 All output pins, no load, VO4, VO5 MIN. TYP.
Note
MAX. 140 140 140 140
Unit ns ns ns ns
35 45 40 50
Note The TYP. value is a reference value when TA = 25°C, VDD = 3.3 V, VCC = 11.5 V, VEE = −5.5 V.
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Preliminary Product Information S15857EJ4V0PM
µ PD160970
Switching Characteristics Waveform
tf 90% 50%
tr 90% 50% VDD VSS
Logic input
10%
10%
tPLH1, tPLH2
tPHL1, tPHL2 VCC
50% High-withstanding-voltage output
50%
VEE tPHL2 tPLH2 VCC
50% High-withstanding-voltage output
50%
VEE
Preliminary Product Information S15857EJ4V0PM
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µ PD160970
6. PACKAGE DRAWING
24-PIN PLASTIC TSSOP (5.72 mm (225))
24 13 detail of lead end F G R
P
L S
1
12
E
A A' S
H I J
C D M
M
K B
N
S
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A A' B C D E F G H I J K L M N P R S
MILLIMETERS 6.65 ± 0.10 6.5 ± 0.1 0.575 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 1.0 ± 0.05 6.4 ± 0.1 4.4 ± 0.1 1.0 ± 0.1 0.17 ± 0.025 0.5 0.10 0.08 3 °+ 5 ° −3° 0.25 0.6 ± 0.15 P24MA-50-6A5
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Preliminary Product Information S15857EJ4V0PM
µ PD160970
7. RECOMMENDED MOUNTING CONDITIONS
The µ PD160970 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative.
Recommended Soldering Conditions for Surface Mounting Type
µ PD160970MA-6A5 : 24-pin plastic TSSOP (5.72 mm (225) )
Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature : 235°C, Time : 30 seconds max. (at 210°C or higher), IR35-00-3 Count : Three times or less, Exposure, limit : None, Flux : Rosin flux with low chlorine (0.2 Wt% or below) recommended VPS Package peak temperature : 215°C, Time : 40 seconds max. (at 200°C or higher), VP15-00-3 Count : Three times or less, Exposure, limit : None, Flux : Rosin flux with low chlorine (0.2 Wt% or below) recommended Wave Soldering Package peak temperature : 260°C, Time : 10 seconds max., Preheating temperature : 120°C max., Exposure, limit : Once, Flux : Rosin flux with low chlorine (0.2 Wt% or below) recommended WS60-00-1
Caution Do not use different soldering methods together.
Preliminary Product Information S15857EJ4V0PM
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µ PD160970
[MEMO]
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Preliminary Product Information S15857EJ4V0PM
µ PD160970
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Product Information S15857EJ4V0PM
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