UPD16326GB-3B4

DATA SHEET MOS INTEGRATED CIRCUIT µPD16326 32-BIT FLUORESCENT DISPLAY TUBE DRIVER The µPD16326 is a fluorescent display tube driver using a high breakdown voltage CMOS process. It consists of 32-bit bidirectional shift registers, a latch circuit, and a high breakdown voltage CMOS driver block. The logic block operates on a 5 V power supply designed to be connected directly to a microcontroller (CMOS level input). The driver block has a 130 V and 20 mA high breakdown voltage output, and both the logic block and driver block consist of CMOS, allowing operation with low power consumption. FEATURES • High breakdown voltage CMOS structure • High breakdown voltage, high current output (130 V, 20 mA) • 32-bit bidirectional shift registers on chip • Data control by transfer clock (external) and latch • High-speed data transfer capability (fmax = 8.0 MHz MIN) • Wide operating temperature range (TA = –40 to 85 ˚C) ORDERING INFORMATION Part Number Package 44-pin plastic QFP (4-direction leads) µPD16326GB-3B4 The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Document No. S10948EJ1V0DS00 (1st edition) Date Published July 1996 P Printed in Japan © 1996 µPD16326 BLOCK DIAGRAM CLK A R/L 32-bit bidirectional shift registers B STB BLK 32-bit latch O1 O2 O32 PIN CONFIGURATION (Top View) O10 35 44 43 42 41 40 39 38 37 36 VDD2 VSS2 A BLK STB CLK VSS1 R/L VDD1 B VSS2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 O11 O1 O2 O3 O4 O5 O6 O7 O8 O9 33 32 31 30 29 28 27 26 25 24 23 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O32 O31 O30 O29 O28 O27 O26 O25 O24 Remark Be sure to enter the power to VDD1, logic signal, and VDD2, in that order, and turn off the power in the reverse order. 2 VDD2 O23 µPD16326 PIN DESCRIPTION Pin Symbol STB A B CLK BLK R/L Pin Name Latch strobe input RIGHT data input LEFT data input Clock input Blanking input Shift control input Pin Number 5 3 10 6 4 8 Description H: Data through L: Data retention When R/L = H, A: Input B: Output When R/L = L, A: Output B: Input Shift is executed on a fall. H: O1 to O32: ALL “L” H: Right shift mode A → O1 ... O32 → B L: Left shift mode B → O32 ... O1 → A 130 V, 20 mA 5 V ± 10 % 30 to 125 V Connected to system GND Connected to system GND MAX O1 to O32 VDD1 VDD2 VSS1 VSS2 High breakdown voltage output Logic block power supply Driver block power supply Logic ground Driver ground 13 - 44 9 1, 12 5 2, 11 TRUTH TABLE 1 (SHIFT REGISTER BLOCK) Input R/L H H L L CLK ↓ H or L ↓ H or L OutputNote 2 Output Input A Output Shift Register B OutputNote 1 Output Input Execution of right shift Retained Execution of left shift Retained Notes 1. On a clock fall, the data items of S31 are shifted to S32, and output from B. 2. On a clock fall, the data items of S2 are shifted to S1, and output from A. TRUTH TABLE 2 (LATCH BLOCK) STB L H Operation Retains Sn data immediately before STB becomes L. Outputs shift register data. TRUTH TABLE 3 (DRIVER BLOCK) LnNote × × L H STB × L H H BLK H L L L Driver output state L (all driver outputs: L) Outputs Sn data on STB fall. L H Note Ln: Latch output Remark × = H or L, H = high level, L = Low level 3 µPD16326 ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C, VSS = 0 V) Item Logic block supply voltage Driver block supply voltage Logic block input voltage Driver block output current Package allowable power dissipation Operating ambient temperature Storage temperature Symbol VDD1 VDD2 VI IO PD TA Tstg Rating –0.5 to +7.0 –0.5 to +130 –0.5 to VDD1 + 0.5 20 800Note –40 to +85 –65 to +150 Unit V V V mA mW ˚C ˚C Note When TA ≥ 25 °C, load should be alleviated at a rate of –8.0 mW/°C. (Tj = 125 °C (MAX.)) RECOMMENDED OPERATING RANGE (TA = – 40 to +85 ˚C, VSS = 0 V) Item Logic block supply voltage Driver block supply voltage Input voltage high Input voltage low Driver output current Symbol VDD1 VDD2 VIH VIL IOH IOL MIN. 4.5 30 0.7·VDD1 0 TYP. 5.0 MAX. 5.5 125 VDD1 0.2·VDD1 –10 +2.5 Unit V V V V mA mA ELECTRICAL SPECIFICATIONS (TA = 25 ˚C, VDD1 = 4.5 to 5.5 V, VDD2 = 125 V, VSS = 0 V) Item Output voltage high Output voltage low Output voltage high Symbol VOH1 VOL1 VOH21 VOH22 Output voltage low Input leakage current Input voltage high Input voltage low Static consumption current VOL2 IIL VIH VIL IDD1 IDD1 IDD2 IDD2 Logic, TA = –40 to +85 ˚C Logic, TA = 25 ˚C Driver, TA = –40 to +85 ˚C Driver, TA = 25 ˚C Condition Logic, IOH = –1.0 mA Logic, IOL = 1.0 mA O1 to O40, IOH = –0.5 mA O1 to O40, IOH = –5.0 mA O1 to O40, IOL = 0.5 mA VI = VDD1 or VSS1 0.7·VDD1 0 MIN. 0.9·VDD1 0 121 115 2.5 ± 1.0 VDD1 0.2·VDD1 1 000 100 1 000 100 TYP. MAX. VDD1 0.1·VDD1 Unit V V V V V µA V V µA µA µA µA 4 µPD16326 SWITCHING CHARACTERISTICS (TA = 25 ˚C, VDD1 = 5.0 V, VDD2 = 125 V, VSS = 0 V, logic CL = 15 pF, driver CL = 50 pF, driver RL = 220 kΩ, tr = tf = 10 ns) Item Transmission delay time Symbol tPHL1 tPLH1 tPHL2 tPLH2 Fall time Rise time Maximum clock frequency Input capacitance tTHL tTLH fmax CI O1 to O32 O1 to O32 With cascading, Duty = 50 % 8.0 15 BLK ↓→ O1 to O32 CLK ↓→ A/B Condition MIN. TYP. MAX. 110 110 300 300 600 500 Unit ns ns ns ns ns ns MHz pF TIMING REQUIREMENTS (TA = – 40 to +85 ˚C, VDD1 = 4.5 to 5.5 V, VSS = 0 V, tr = tf = 10 ns) Item Clock pulse width Strobe pulse width Blank pulse width Data setup time Data hold time Clock-strobe time Strobe-clock time Strobe-blank time Symbol PWCLK PWSTB PWBLK tsetup thold tCLK-STB tSTB-CLK tSTB-BLK CLK ↓→ STB ↑ STB ↓→ CLK ↓ STB ↑→ BLK ↓ Condition MIN. 40 80 1 500 15 30 45 45 80 TYP. MAX. Unit ns ns ns ns ns ns ns ns 5 µPD16326 SWITCHING CHARACTERISTIC WAVEFORM (R/L = H) 1/fmax. PWCLK (L) PWCLK (H) VDD1 CLK 50 % 50 % 50 % VSS tsetup A/B (Input) thold VDD1 50 % 50 % VSS tPHL1 B/A (Output) tPLH 1 VOH1 50 % 50 % VOL1 tCLK-STB PWSTB tSTB-CLK VDD1 STB 50 % 50 % VSS tSTB-BLK PWBLK VDD1 BLK 50 % 50 % VSS tPLH2 tTLH 90 % tPHL2 90 % 10 % tTHL VOH2 VOL2 On 10 % 6 µPD16326 PACKAGE DRAWINGS 44 PIN PLASTIC QFP (Unit: mm) A B 33 34 23 22 detail of lead end C D S Q R 44 1 12 11 F G H P N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. J I M K M L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 13.6±0.4 10.0±0.2 10.0±0.2 13.6±0.4 1.0 1.0 0.35±0.10 0.15 0.8 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10 –0.05 0.10 2.7 0.1±0.1 5°±5° 3.0 MAX. INCHES 0.535 +0.017 –0.016 0.394 +0.008 –0.009 0.394 +0.008 –0.009 0.535 +0.017 –0.016 0.039 0.039 0.014 +0.004 –0.005 0.006 0.031 (T.P) 0.071 +0.008 –0.009 0.031 +0.009 –0.008 0.006 +0.004 –0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. P44GB-80-3B4-3 7 µPD16326 RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended below. For soldering methods and conditions other than those recommended, please contact your NEC sales representative. SURFACE MOUNT TYPE For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (C10535E). µPD16326GB-3B4 Recommended Condition Symbol IR35-00-2 Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 ˚C, Duration: 30 sec. MAX. (at 210 ˚C or above), Number of times: Twice, Time limit: None Note Package peak temperature: 215 ˚C, Duration: 40 sec. MAX. (at 200 ˚C or above), Number of times: Twice, Time limit: None Note Solder bath temperature: 260 ˚C MAX., Duration: 10 sec. MAX., Number of times: Once, Time limit: NoneNote Pin partial temperature: 300 ˚C MAX., Duration: 10 sec. MAX., Time limit: NoneNote VPS VP15-00-2 Wave soldering WS60-00-1 Pin partial heating Note For the storage period after dry-pack decapsulation, storage conditions are max. 25 ˚C, 65 % RH. Caution Use of more than one soldering method should be avoided (except in the case of pin partial heating). REFERENCES NEC Semiconductor Device Reliability/Quality Control System (IEI-1212) Quality Grade on NEC Semiconductor Devices (IEI-1209) 8 µPD16326 [MEMO] 9 µPD16326 [MEMO] 10 µPD16326 [MEMO] 11 µPD16326 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2