UPD16337GF-3BA

DATA SHEET MOS INTEGRATED CIRCUIT µPD16337 64-BIT AC-PDP DRIVER The µPD16337 is a high-voltage CMOS driver designed for flat display panels such as PDPs, VFDs and ELs. It consists of a 64-bit bi-directional shift register (16 bit × 4 circuits), 64-bit latch and high-voltage CMOS driver. The logic block is designed to operate at 5-V power supply, enabling direct connection to a microcontroller. In addition, the µPD16337 achieves low power dissipation by employing CMOS structure while having a high withstand voltage output (150 V, 40 mA MAX.) FEATURES • Built in four 16-bit bi-directional shift register circuits • Data control with transfer clock (external) and latch • High-speed data transfer (fmax. = 20 MHz MIN. at cascade connection) • Wide operating temperature range (TA = –40 to +85°C) • High withstand output voltage (150 V, 40 mA MAX.) • 5-V CMOS input interface • High withstand voltage CMOS structure • Capable of reversing all driver outputs by PC pin ORDERING INFORMATION Part Number Package 100-pin plastic QFP µPD16337GF-3BA Document No. S12363EJ1V0DS00 (1st edition) Date Published January 1998 N CP(K) Printed in Japan © 1998 µPD16337 BLOCK DIAGRAM PC BLK LE SR1 A1 CLK R/L B1 A1 CLK R/L B1 S1 S5 . . . . . . . . . . . . . . . . S61 S1 S2 S3 S4 LE L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note O1 SR2 A2 A2 CLK R/L B2 B2 S2 S6 . . . . . . . . . . . . . . . . S62 SR3 A3 A3 CLK R/L B3 B3 S3 S7 . . . . . . . . . . . . . . . . S63 SR4 A4 A4 CLK R/L B4 B4 S4 S8 . . . . . . . . . . . . . . . . S64 S61 S62 S63 S64 S64 SRn: 16-bit shift register Note High withstand voltage CMOS driver, 150 V, ± 40 mA (MAX.) 2 µPD16337 PIN CONFIGURATION (Top View) O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 80 79 78 77 76 75 74 73 72 71 70 69 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC VDD2 NC VSS2 NC O43 O44 O45 O46 O47 O48 O49 O50 O51 O52 O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 NC VDD2 NC 1 2 3 4 5 6 7 8 9 10 11 12 NC VDD2 NC VSS2 NC O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 NC VDD2 NC 68 13 67 14 66 15 100-pin plaxtic QFP 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS2 NC CLK LE B4 B3 B2 B1 VSS1 NC R/L VDD1 A1 A2 A3 A4 Cautions 1. Pin 40 is connected to the lead frame, and therefore must be left open. 2. Ensure that the VDD1, VDD2, VSS1 and VSS2 pins are all used, and that VSS1 and VSS2 are used at the same potential. 3. To prevent latch up breakdown, the power should be turned on in the order VDD1, logic signal, VDD2. It should be turned off in the opposite order. PC BLK NC VSS2 3 µPD16337 PIN DESCRIPTION Symbol PC BLK LE Pin Name Polarity change input Blank input Latch enable input Pin Number 47 48 34 Description PC = L: All driver output invert BLK = H: All output = H or L Automatically executes latch by setting High at rising edge of the clock When R/L = H, A1 to A4: Input B1 to B4: Output When R/L = L, A1 to A4: Output B1 to B4: Input Shift executed on fall Right shift mode when R/L = H SR1: A1 → S1 ··· S61 → B1 (Same direction for SR2·SR4) Left shift mode when R/L = L SR1: B1 → S61 ··· S1 → A1 (Same direction for SR2·SR4) 130 V, 40 mA MAX. 5 V ± 10% 30 to 130 V Connect to system GND Connect to system GND Non-connection Ensure that pin 40 is left open. A1 t o A 4 RIGHT data input/output 43 to 46 B1 t o B 4 LEFT data input/output 38 to 35 CLK R/L Clock input Shift control input 33 41 O1 to O64 High withstand voltage output 54 to 75, 81 to 100, 6 to 27 42 2, 29, 52, 79 39 4, 31, 50, 77 1, 3, 5, 28, 30, 32, 40, 49, 51, 53, 76, 78, 80 VDD1 VDD2 VSS1 VSS2 NC Power supply for logic block Power supply for driver block Logic GND Driver GND Non-connection 4 µPD16337 TRUTH TABLE 1 (Shift Register Block) Input R/L H H L L CLK ↓ H or L ↓ H or L OutputNote 2 Output Input A Output Shift Register B OutputNote 1 Output Input Right shift execution Hold Left shift execution Hold Notes 1. The data of S57, S58, S59, S60 shifts to S61, S62, S63, S64 and is output from B1, B2, B3, B4 at the falling edge of the clock, respectively. 2. The data of S5, S6, S7, S8 shifts to S1, S2, S3, S4 and is output from A1, A2, A3, A4 at the falling edge of the clock, respectively. TRUTH TABLE 2 (Latch Block) LE H CLK ↑ ↓ L × Output State of Latch Block (Ln) Latch Sn data and hold output data Hold latch data Hold latch data TRUTH TABLE 3 (Driver Block) Ln × × × × BLK H H L L PC H L H L Output State of Driver Block H (All driver outputs: H) L (All driver outputs: L) Output latch data (Ln) Output reversed latch data (Ln) ×: H or L, H: High level, L: Low level 5 µPD16337 TIMING CHART (Right shift) CLK A1 (B4) A2 (B3) A3 (B2) A4 (B1) S1 (S64) S2 (S63) S3 (S62) S4 (S61) S5 (S60) S6 (S59) S7 (S58) S8 (S57) LE BLK PC O1 (O64) O2 (O63) O3 (O62) O4 (O61) O5 (O60) O6 (O59) O7 (O58) O8 (O57) Remark Values in parentheses in the above chart are when R/L = L. 6 µPD16337 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS1 = VSS2 = 0 V) Parameter Logic Block Supply Voltage Driver Block Supply Voltage Logic Block Input Voltage Driver Block Output Current Input Current Power Dissipation Operating Ambient Temperature Storage Temperature Symbol VDD1 VDD2 VI IO2 II PD TA Tstg Ratings –0.5 to +7.0 –0.5 to +150 –0.5 to VDD1 + 0.5 40 ±25 1300Note –40 to +85 –65 to +150 Unit V V V mA mA mW °C °C Note Derate at –13 mW/°C at TA = 25°C or higher RECOMMENDED OPERATING CONDITIONS (TA = –40 to +85°C, VSS1 = VSS2 = 0 V) Parameter Logic Block Supply Voltage Driver Block Supply Voltage High-Level Input Voltage Low-Level Input Voltage Driver Output Current Symbol VDD1 VDD2 VIH VIL IOH2 IOL2 MIN. 4.5 30 0.7 VDD1 0 TYP. 5.0 MAX. 5.5 130 VDD1 0.2 VDD1 –30 +30 Unit V V V V mA mA ELECTRICAL SPECIFICATIONS (TA = 25°C, VDD1 = 5.0 V, VDD2 = 130 V, VSS1 = VSS2 = 0 V) Parameter High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage Symbol VOH1 VOL1 VOH21 VOH22 Low-Level Output Voltage VOL21 VOL22 Input Leakage Current High-Level Input Voltage Low-Level Input Voltage Static Current Dissipation IIL VIH VIL IDD1 IDD1 IDD2 IDD2 Logic, TA = –40 to +85°C Logic, TA = 25°C Driver, TA = –40 to +85°C Driver, TA = 25°C Condition Logic, IOH1 = –1.0 mA Logic, IOL1 = 1.0 mA O1 to O64, IOH2 = –10 mA O1 to O64, IOH2 = –30 mA O1 to O64, IOL2 = 10 mA O1 to O64, IOL2 = 30 mA V1 = VDD1 or VSS1 0.7 VDD1 0.2 VDD1 100 10 1000 100 MIN. 0.9 VDD1 0 123 110 5.0 15 ± 1.0 TYP. MAX. VDD1 0.1 VDD1 Unit V V V V V V µA V V µA µA µA µA 7 µPD16337 SWITCHING CHARACTERISTICS (TA = 25°C, VDD1 = 5.0 V, VDD2 = 130 V, VSS1 = VSS2 = 0 V, logic CL = 15 pF, driver CL = 50 pF, tr = tf = 6.0 ns) Parameter Transmission Delay Time Symbol tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 Rise Time Fall Time Maximum Clock Frequency tTLH tTHL fmax. O1 to O64 O1 to O64 When data is read, duty 50% TA = –40 to +85°C VDD1 = 4.5 to 5.5 V When a cascade connection is made with a duty of 50% TA = –40 to +85°C VDD1 = 4.5 to 5.5 V Input Capacitance CI 25 PC → O1 to O64 BLK → O1 to O64 CLK ↑ (LE = H) → O1 to O64 CLK ↓ → A/B Conditions MIN. TYP. MAX. 40 40 180 180 165 165 160 160 200 200 Unit ns ns ns ns ns ns ns ns ns ns MHz 20 MHz 15 pF TIMMING REQUIREMENT (TA = –40 to +85°C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 6.0 ns) Parameter Clock Pulse Width Latch Enable Pulse Width Blank Pulse Width PC Pulse Width Data Setup Time Data Hold Time Latch Enable Time 1 Latch Enable Time 2 Latch Enable Time 3 Latch Enable Time 4 Symbol PWCLK PWLE PWBLK PWPC tsetup thold tLE1 tLE2 tLE3 tLE4 Conditions MIN. 20 30 500 500 10 10 20 10 20 10 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns 8 µPD16337 SWITCHING CHARACTERISTICS WAVEFORM 1/fmax. PWCLK (H) PWCLK (L) VDD1 CLK 50% 50% 50% VSS1 tsetup thold VDD1 An/Bn (Input) 50% 50% VSS1 tPHL1 tPLH1 VOH1 50% 50% VOL1 Bn/An (Output) VDD1 LE 50% 50% VSS1 PWLE tLE1 tLE2 tLE3 tLE4 VDD1 CLK 50% 50% 50% VSS1 tPHL2 90% On VOL2 tPLH2 VOH2 On 10% VOL2 VOH2 9 µPD16337 PWBLK VDD1 BLK 50 % 50% VSS1 tPHL3 90 % On tPLH3 VOH2 10% VOL2 PWPC VDD1 PC 50% 50% VSS1 tPHL4 90% On tPLH4 VOH2 10% VOL2 10 µPD16337 PACKAGE DRAWINGS 100 PIN PLASTIC QFP (14 20) A B 80 81 51 50 detail of lead end CD S Q R 100 1 31 30 F G P H I M J K M N L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.2±0.2 20.0±0.2 14.0±0.2 17.2±0.2 0.8 0.6 0.30±0.10 0.15 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 –0.05 0.10 2.7 0.125±0.075 5 ° ±5 ° 3.0 MAX. INCHES 0.913 +0.009 –0.008 0.787 +0.009 –0.008 0.551 +0.009 –0.008 0.677±0.008 0.031 0.024 0.012 +0.004 –0.005 0.006 0.026 (T.P.) 0.063±0.008 0.031 +0.009 –0.008 0.006 +0.004 –0.003 0.004 0.106 0.005±0.003 5 ° ±5 ° 0.119 MAX. S100GF-65-3BA-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 11 µPD16337 RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended below. For soldering methods and conditions other than those recommended, please contact your NEC sales representative. SURFACE MOUNT TYPE For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (C10535E). µPD16337GF-3BA Recommended Condition Symbol IR30-00-2 Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 230°C, Duration: 30 sec. MAX. (at 210°C or above), Number of times: Twice, Time limit: NoneNote Package peak temperature: 215°C, Duration: 40 sec. MAX. (at 200°C or above), Number of times: Twice, Time limit: NoneNote Pin partial temperature: 300°C MAX., Duration: 10 sec. MAX., Time limit: NoneNote VPS VP15-00-2 Pin partial heating Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH. Caution Use of more than one soldering method should be avoided (except in the case of pin partial heating). REFERENCES NEC Semiconductor Device Reliability/Quality Control System (IEI-1212) Quality Grade on NEC Semiconductor Devices (C11531E) 12 µPD16337 [MEMO] 13 µPD16337 [MEMO] 14 µPD16337 [MEMO] 15 µPD16337 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2