UPD168103AK9-5B4-A

DATA SHEET MOS INTEGRATED CIRCUIT µ PD168103A 5-CHANNEL OPERATIONAL AMPLIFIER, IRIS DRIVER, AND 4-CHANNEL H-BRIDGE DRIVER DESCRIPTION The µ PD168103A is the motor driver IC with IRIS control circuit, operational amplifier and 4-ch H-bridge output. Smooth operation is possible for IRIS control with linear method. The package is 48-pin thin type QFN and then it helps reduce the mounting area and height. The µ PD168103A is suitable for the lens drive of a camcorder, DSC, etc. FEATURES • 5-ch H-bridge circuits employing power MOS FET • Low-voltage driving LVDD = 2.7 to 3.6 V, AVDD = 4.5 to 5.5 V, VM12 = VM34 = VSHUTTER = VIRIS = 2.7 to 5.5 V • Output on-state resistance: 2.0 Ω TYP., 3.0 Ω MAX. (4-ch H-bridge block, sum of top and bottom stage, VM = 5 V) • PWM output (ch1 to ch4) • Output current DC current: ±0.3 A/ch (when each channel is used independently) Peak current: ±0.7 A/ch (when each channel is used independently) • 3-ch general-purpose operational amplifier Input offset voltage: ±5 mV Input voltage range: 0 to AVDD − 1.5 V Output voltage range: 0.2 to AVDD − 0.2 V • 1-ch current sink amplifier Output current: 5 mA • 1-ch 1/2VDD output amplifier • IRIS driver block supporting linear driving • Pre-driver amplifier of the IRIS driver block • Undervoltage lockout circuit Output circuit and amplifier stop at LVDD = 1.7 V TYP. or less. • Overheat protection circuit Operates at 150°C or more and shuts down the output circuit. • Mounted on 48-pin plastic WQFN (7 x 7) APPLICATIONS Lens motor driving for DVC and DSC, etc. ORDERING INFORMATION Part Number Package Note Marking 168103A Packing Type • Tray stuffing • Dry pack µ PD168103AK9-5B4-A 48-pin plastic WQFN (7 x 7) Note Pb-free (This product does not contain Pb in external electrode and other parts.) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17655EJ1V0DS00 (1st edition) Date Published June 2005 NS CP(K) Printed in Japan 2005 µ PD168103A 1. BLOCK DIAGRAM VM12 OUT1A OUT1B PGND12 OUT2A OUT2B 45 42 44 43 47 46 48 VM34 OUT3A OUT3B PGND34 OUT4A OUT4B 16 19 17 18 14 15 13 H-bridge 1 H-bridge 2 H-bridge 3 H-bridge 4 H-bridge Control EN12 IN1 IN2 4 5 6 7 8 9 EN34 IN3 IN4 IRIN1 IRIN2 VSUTTER VIRIS INIRP INIRM OUTIRP OUTIRM 10 RESETB GND LVDD AVDD 3 2 1 12 IRIS Control LVDD Logic power Analog power LVDD UVLO TSD + − Amp. Control 1/2AVDD −+ AVDD + − Amp. ON/OFF control AVDD + − AVDD + − AVDD + − GND AVDD 11 27 31 33 32 30 28 INREF AMP0 34 AMP5 29 PGND5 OUTREF 35 21 OUT4D AMP1 39 40 41 36 37 AMP2 38 24 25 AMP3 26 23 22 AMP4 20 IN1P IN1M OUT1 IN2P IN2M OUT2 IN3P IN3M OUT3 IN4P IN4M OUT4S Cautions 1. P in pin name means plus, and M in pin name means minus. 2. A pull-down resistor (50 to 200 kΩ) is connected to the logic input pins (EN12, EN34, IN1, IN2, IN3, and IN4). A pull-up resistor (50 to 200 kΩ) is connected to the IRIN1 and IRIN2 pins. 2 Data Sheet S17655EJ1V0DS µ PD168103A 2. PIN FUNCTIONS (1/2) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin Name LVDD GND RESETB EN12 IN1 IN2 EN34 IN3 IN4 IRIN1 IRIN2 AVDD OUT4B PGND34 OUT4A VM34 OUT3B PGND34 OUT3A OUT4S OUT4D IN4M IN4P IN3P IN3M OUT3 VSHUTTER OUTIRM PGND5 OUTIRP VIRIS INIRM INIRP INREF I/O − − Input Input Input Input Input Input Input Input Input − Output − Output − Output − Output Output Output Input Input Input Input Output − Output − Output − Input Input Input Logic power supply voltage pin Logic and analog GND pin Reset input pin ch1 and ch2 output control input pin ch1 input pin ch2 input pin ch3 and ch4 output control input pin ch3 input pin ch4 input pin IRIS control logic input pin 1 IRIS control logic input pin 2 Analog power supply voltage pin ch4 output pin B ch3 and ch4 GND pin ch4 output pin A ch3 and ch4 power supply voltage pin ch3 output pin B ch3 and ch4 GND pin ch3 output pin A Amplifier 4 (AMP4) source output pin (source) Amplifier 4 (AMP4) drain output pin (sink) Amplifier 4 (AMP4) minus input pin Amplifier 4 (AMP4) plus input pin Amplifier 3 (AMP3) plus input pin Amplifier 3 (AMP3) minus input pin Amplifier 3 (AMP3) output pin Shutter (ON/OFF) power supply voltage pin IRIS minus output pin IRIS and shutter GND pin IRIS plus output pin IRIS (linear) power supply voltage pin IRIS linear control (AMP5) minus input pin IRIS linear control (AMP5) plus input pin 1/2AVDD amplifier (AMP0) input pin (for capacitor connection) Function Data Sheet S17655EJ1V0DS 3 µ PD168103A (2/2) Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name OUTREF IN2P IN2M OUT2 IN1P IN1M OUT1 OUT1A PGND12 OUT1B VM12 OUT2A PGND12 OUT2B I/O Output Input Input Output Input Input Output Output − Output − Output − Output Function 1/2AVDD amplifier (AMP0) output pin Amplifier 2 (AMP2) plus input pin Amplifier 2 (AMP2) minus input pin Amplifier 2 (AMP2) output pin Amplifier 1 (AMP1) plus input pin Amplifier 1 (AMP1) minus input pin Amplifier 1 (AMP1) output pin ch1 output pin A ch1 and ch2 GND pin ch1 output pin B ch1 and ch2 power supply voltage pin ch2 output pin A ch1 and ch2 GND pin ch2 output pin B 4 Data Sheet S17655EJ1V0DS µ PD168103A 3. FUNCTION OPERATION TABLE 3.1 Reset Function The internal circuit is shut off and the circuit current is kept to 1 µA MAX. when the RESETB pin is made L (reset status). In this status, the output pin goes into a Hi-Z (High impedance) state. Set the RESETB pin H for normal usage. Remark H: High level, L: Low level 3.2 Stepping Motor Driving Block Table 3−1. I/O Truth Table of the Stepping Motor Driving Block EN12, EN34 H IN1, IN2, IN3, IN4 L H OUT1A, OUT2A, OUT3A, OUT4A H L Hi-Z Hi-Z OUT1B, OUT2B, OUT3B, OUT4B L H Hi-Z Hi-Z L L H Data Sheet S17655EJ1V0DS 5 µ PD168103A 3.3 IRIS Motor Driving Block Table 3−2. I/O Truth Table of the IRIS Driving Block IRIN1 IRIN2 Operation Mode Q1 Output State of H-bridge Q2 OFF Q3 OFF Q4 ON (Linear) OFF ON OFF ON OFF OFF ON OFF OFF OFF ON OFF OUTIRP OUTIRM L L Normal operation (Amp. control) ON Linear Linear L H H H L H Shutter IRIS open Output all OFF L H Hi-Z H L Hi-Z Figure 3−1. Description of the Operation Figure of the IRIS Motor Driving Block VIRIS INIRP INIRM + − Q4 VSHUTTER Q2 OUT7A OUT7B Q3 Q1 Normal VIRIS + − Q4 Shutter VSHUTTER INIRP INIRM OUTIRP OUTIRM OUTIRP OUTIRM Open VIRIS VIRIS All OFF VSHUTTER OUTIRP OUTIRM OUTIRP OUTIRM 6 Data Sheet S17655EJ1V0DS µ PD168103A 4. FUNCTIONAL DEPLOYMENT 4.1 Undervoltage Lockout (UVLO) Circuit This function is to forcibly stop the operation of the µ PD168103A to prevent malfunctioning if LVDD drops. When UVLO operates, the driver output and amplifier circuit are the OFF status. The UVLO circuit detects a voltage drop if LVDD drops to 1.7 V TYP. in the non-reset status (RESETB = H). In the reset status (RESETB = L), it detects a voltage drop if LVDD drops to 0.6 V TYP. This circuit may not operate if the LVDD voltage abruptly drops for just a few µs. 4.2 Overheat Protection (TSD) Circuit This function is to forcibly stop the operation of the driver output to protect it from destruction due to overheating if the chip temperature of the µ PD168103A rises. The overheat protection circuit operates when the chip temperature rises to 150°C or more. When overheat is detected, the driver output is stopped. When RESETB = L (the reset status) or when UVLO is detected, the overheat protection circuit does not operate. 4.3 Power Up Sequence The µ PD168103A has a circuit that prevents current from flowing into the VM, VSHUTTER and VIRIS pins (from the next, these are written as the motor power supply pins) when LVDD = 0 V or AVDD = 0 V. Therefore, the current that flows into the motor power supply pins are cut off when LVDD = 0 V. Because the LVDD pin voltage, the AVDD pin voltage and the motor power supply pins voltage are monitored, a current of 1 µA TYP. flows into each one of the motor power supply pins when LVDD is applied. Data Sheet S17655EJ1V0DS 7 µ PD168103A 5. NOTE ON CORRECT USE 5.1 Pin Processing of Unused Circuit The input/output pins of an unused circuit must be processed as specified below. A pull-down or pull-up resistor is connected inside to the logic input pins. Connect the input pins to the GND or LVDD (INIR1 and INIR2) potential when they are not used. A pull-down resistor is not connected to the RESETB pin. Be sure to fix the RESETB pin to the LVDD or GND potential when it is used. 5.2 OUT4S pin Keep the voltage in the OUT4S pin to 2 V or less. If an application circuit like the one shown below is used, the input voltage range of the amplifier is also 2 V or less. IN4P IN4M + − OUT4D OUT4S 5.3 OFFSET SHIFT OF AMP3 In case of large current with H-bridge 3, it cause to small offset shift in AMP3. Please take care to use AMP3, and estimate actual set deeply. 8 Data Sheet S17655EJ1V0DS µ PD168103A 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Power supply voltage Symbol LVDD AVDD VM12, VM34 VSHUTTER, VIRIS Input voltage Note1 Condition Control block Analog block Stepping motor block IRIS block Rating −0.5 to +6.0 −0.5 to +6.0 −0.5 to +6.0 −0.5 to +6.0 −0.5 to LVDD + 0.5 Unit V V V V V V V A/ch A/ch A/ch W °C °C VIN VOUT1 VOUT2 ID1(DC) ID2(DC) Motor block Amplifier block DC (stepping motor) DC (IRIS) PW < 10 ms, Duty Cycle ≤ 20% Output pin voltage 1 Output pin voltage 2 DC output current 6.2 −0.5 to AVDD + 0.5 ±0.3 ±0.2 ±0.7 1.0 150 −55 to +150 Instantaneous output current Power consumption Peak junction temperature Storage temperature Note2 ID(pulse) PT Tch(MAX) Tstg Notes 1. Keep VIN to less than 6 V. 2. The overheat protection circuit operates at Tch > 150°C. When overheat is detected, all the circuits are stopped. The overheat protection circuit does not operate at reset or on detection of ULVO. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Power supply voltage Symbol LVDD AVDD VM12, VM34 VSHUTTER, VIRIS Input voltage DC output current VIN ID1(DC) DC (stepping motor, when 2 chs are driven at same time) ID2(DC) DC (IRIS), maximum current when the shutter operates Amplifier output current Amplifier output sink current Logic input frequency Operating temperature range IOUT_AMP1 IOUT_AMP2 fIN TA −10 AMP1 to AMP3 AMP4 −5 0 +5 +5 100 70 mA/ch mA kHz °C −0.1 +0.1 A/ch Control block Analog block Stepping motor block IRIS block Condition MIN. 2.7 4.5 2.7 2.7 0 −0.2 TYP. MAX. 3.6 5.5 5.5 5.5 VDD +0.2 Unit V V V V V A/ch Caution Design each output current so that the junction temperature does not exceed 150ºC. Data Sheet S17655EJ1V0DS 9 µ PD168103A Electrical Characteristics (Unless otherwise specified, TA = 25°C, LVDD = 3.0 V, AVDD = 5.0 V, VM = VSHUTTER = VIRIS = 5.0 V) Overall and H-bridge block (stepping motor) Parameter LVDD pin current in standby mode AVDD pin current in standby mode VM pin current in standby mode LVDD pin current in during operation High-level input current Low-level input current Input pull-down resistance High-level input voltage Low-level input voltage H-bridge on-state resistance Note 1 Note 2 Symbol ILVDD(STB) IAVDD(STB) IVM(STB) IDD(ACT) IIH IIL RIND VIH VIL Ron Condition RESETB = 0 V RESETB = 0 V RESETB = 0 V RESETB = LVDD VIN = LVDD VIN = 0 V MIN. TYP. MAX. 1.0 1.0 1.0 2.0 60 Unit µA µA µA mA µA µA kΩ V −1.0 50 0.7 x VDD 0.3 x VDD 200 V Ω IM = 0.2 A, sum of upper and lower stages 2.0 3.0 Output leakage current IM(off) VDDS1 ton toff tr tf Per VM pin, All control pins: low level RESETB = H RL = 20 Ω 1.7 0.5 0.1 0.05 0.2 50 1.0 2.5 1.0 0.4 0.4 100 µA V Low-voltage detection voltage Output turn-on time Output turn-off time Output rise time Output fall time µs µs µs ns Notes 1. µ PD168103A has a circuit that prevents current from flowing into the VM pin when LVDD = 0 V. 2. Unlike normal operations, after a reset the detection voltage becomes 0.6 V TYP. Figure 6−1. Switching Characteristic Waveform of the Stepping Motor Driving Block 100% VIN 0% 50% 50% ton toff 100% 90% 50% toff ton 100% 90% 50% 10% −10% −50% −90% tr −100% −50% −90% tf IDR 0% tf 10% −10% tr 10 Data Sheet S17655EJ1V0DS µ PD168103A H-bridge block (IRIS motor) Parameter VIRIS pin current in standby mode VSHUTTER pin current in standby mode High-level input current Low-level input current Input pull-up resistance High-level input voltage Low-level input voltage H-bridge on-state resistance Symbol IVIRIS(STB) IVSHUTTER(STB) IIH IIL RIND VIH VIL Ron1 RL = 50 Ω, sum of upper and lower stages Output turn-on time tonH1 tonH2 Output turn-off time Output rise time Output fall time Control amplifier offset voltage toffH trH tfH VIO AMP5 When linear driving, RL = 50 Ω When full ON, RL = 50 Ω 0.01 0.01 0.01 25 1.0 1.0 60 80 ±5 ±7.5 35 2.0 2.0 2.5 Condition RESETB = 0 V RESETB = 0 V VIN = LVDD VIN = 0 V −60 50 0.7 x VDD 0.3 x VDD 3.5 200 MIN. TYP. MAX. 1.0 1.0 1.0 Unit µA µA µA µA kΩ V V Ω µs µs µs ns ns mV Figure 6−2. Switching Characteristic Waveform of the IRIS Motor Driving Block at IRIN1 = L 100% IRIN2 0% 50% 50% ton toff toff ton Linear operation Linear operation 100% 0% 50% −10% −50% −90% tr −100% −50% −90% tf 50% −10% 100% IIRIS Shutter Data Sheet S17655EJ1V0DS 11 µ PD168103A Operational amplifier block Parameter AVDD pin current in during operation Input offset voltage 1 Input offset voltage 2 Common mode input voltage range 1 Common mode input voltage range 2 High-level output voltage Low-level output voltage Large amplitude voltage gain Slew-rate 1/2 AVDD output voltage accuracy Symbol IADD VIO1 VIO2 VICM1 VICM2 VOH VOL AV SR VO Output open AMP1 to AMP3, AMP5 AMP4 AMP1 to AMP3, AMP5 AMP4 AMP1 to AMP3, when IOUT = +2 mA AMP1 to AMP3, when IOUT = −2 mA AMP1 to AMP3, DC AMP1 to AMP3, AV = 1 dB ,RL ≥ 10 kΩ AMP0, IOUT = ±100 µA 2.4 80 0.5 2.5 2.6 0 0 AVDD − 0.2 0.2 ±3 ±5 Condition MIN. TYP. MAX. 3.0 ±5 ±7 AVDD − 1.5 AVDD − 2.0 Unit mA mV mV V V V V dB V/µs V 12 Data Sheet S17655EJ1V0DS µ PD168103A 7. TYPICAL CHARACTERISTICS (Unless otherwise specified, TA = 25°C, LVDD = 3.0 V, AVDD = VM = VSHUTTER = VIRIS = 5.0 V) PT vs. TA CHARACTERISTIC Ron vs. TA CHARACTERISTIC (H-bridge 1 to 4) Ron - H-bridge On-state Resistance - Ω 1.2 PT - Total Power Dissipation - W 2.5 OUT4B → OUT4A OUT1A → OUT1B OUT4A → OUT4B OUT1B → OUT1A 1 125˚C/W 0.8 0.6 0.4 0.2 0 2 1.5 0 10 20 30 40 50 60 70 80 90 100 TA - Ambient Temperature - 1 -40 -20 0 20 40 60 80 100 TA - Ambient Temperature - Ron vs. TA CHARACTERISTIC (H-bridge IRIS) Ron - H-bridge On-state Resistance - Ω IIH, IIL vs. LVDD CHARACTERISTIC 2.5 IIH, IIL - Input Pin Current - µA 70 OUTIR− → OUTIR+ 60 50 40 30 20 10 0 IIL IIH 2 OUTIR+ → OUTIR− 1.5 1 -40 -20 0 20 40 60 80 100 0 1 2 3 4 5 6 7 TA - Ambient Temperature - LVDD - Power Supply Voltage of Control Block - V VIH, VIL vs. LVDD CHARACTERISTIC UNDERVOLTAGE LOCKOUT CIRCUIT CHARACTERISTIC 5 4 3 2 1 0 0 1 2 3 4 5 6 7 VDDS - Undervoltage Detection Voltage - V VIH, VIL - Input Voltage - V 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 LVDD(L→H) LVDD(H→L) VIH VIL LVDD - Power Supply Voltage of Control Block - V VM - Power Supply Voltage of Motor Block - V Data Sheet S17655EJ1V0DS 13 µ PD168103A Ron vs. VM CHARACTERISTIC Ron - H-bridge On-state Resistance of IRIS Block - Ω Ron - H-bridge On-state Resistance - Ω Ron vs. VIRIS, VSHUTTER CHARACTERISTIC 3.5 3 2.5 2 1.5 1 0.5 IM = 200 mA 0 0 1 2 3 4 5 6 7 4 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 IM = 100 mA Shutter IRIS VM - Power Supply Voltage of Motor Block - V VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V TONH, TOFFH vs. VM CHARACTERISTIC TONH - H-bridge Output Circuit Turn-on Time - µs TOFFH - H-bridge Output Circuit Turn-off Time - µs Tr, Tf vs. VIRIS, VSHUTTER CHARACTERISTIC (when full ON) Tr - IRIS H-bridge Output Circuit Rise Time - µs Tf - IRIS H-bridge Output Circuit Fall Time - µs 1.2 RL = 20 Ω 1 0.8 0.6 0.4 TOFFH 0.2 0 0 1 2 3 4 5 6 7 TONH 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 1 2 3 4 5 6 7 Tf Tr RL = 50 Ω VM - Power Supply Voltage of Motor Block - V VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V Tr, Tf vs. VM CHARACTERISTIC TONH1 - IRIS H-bridge Output Circuit Turn-on Time - µs TOFFH - IRIS H-bridge Output Circuit Turn-off Time - µs TONH1, TOFFH vs. VIRIS, VSHUTTER CHARACTERISTIC (when Linear) Tr - H-bridge Output Circuit Rise Time - µs Tf - H-bridge Output Circuit Fall Time - µs 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 6 7 Tr Tf RL = 20 Ω 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 TOFFH TONH1 RL = 50 Ω VM - Power Supply Voltage of Motor Block - V VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V 14 Data Sheet S17655EJ1V0DS µ PD168103A Tr, Tf vs. VIRIS, VSHUTTER CHARACTERISTIC (when Linear) TONH1 - IRIS H-bridge Output Circuit Turn-on Time - µs TOFFH - IRIS H-bridge Output Circuit Turn-off Time - µs TONH1, TOFFH vs. VIRIS, VSHUTTER CHARACTERISTIC (when full ON) 14 Tr - IRIS H-bridge Output Circuit Rise Time - µs Tf - IRIS H-bridge Output Circuit Fall Time - µs 1.2 RL = 50 Ω 1 TONH1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 TOFFH 12 10 8 6 4 2 0 0 RL = 50 Ω Tr Tf 1 2 3 4 5 6 7 VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V IM vs. VM CHARACTERISTIC IM - VM Pin Current when OFF - µA ILVDD vs. LVDD CHARACTERISTIC 8 ILVDD - LVDD Pin Current - µA 700 RESETB: H EN, IN: L 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 RESETB: H EN, IN: L 7 6 5 4 3 2 1 0 VM - Power Supply Voltage of Motor Block - V LVDD - Power Supply Voltage of Control Block - V Data Sheet S17655EJ1V0DS 15 µ PD168103A 8. STANDARD CONNECTION EXAMPLE AVDD = 4.5 to 5.5 V LVDD = 2.7 to 3.6 V DC/DC Converter Battey VM = 2.7 to 5.5 V 1 to 10 µ F Motor 1 Motor 2 VM12 OUT1A OUT1B PGND12 OUT2A OUT2B VM34 OUT3A OUT3B PGND34 OUT4A OUT4B H-bridge 1 IRIS-CTL H-REF H-GAIN HALL-AD IRIN1 IRIN2 CDS Reset RESETB GND LVDD AVDD Logic power Analog power LVDD INREF CPU EN34 IN3 IN4 EN12 IN1 IN2 H-bridge 2 H-bridge 3 H-bridge 4 H-bridge Control EN34 IN3 IN4 IRIN1 LVDD UVLO TSD + − Amp. Control 1/2LVDD −+ AVDD + − IRIS-CTL IN1P IN1M Amp. ON/OFF control AVDD + − AVDD + − AVDD + − OUT4D GND AVDD IRIN2 VSUTTER VIRIS INIRP INIRM OUTIRP OUTIRM DR+ CPU IRIS Control H-REF AMP0 AMP5 PGND5 OUTREF DR− AMP1 OUT1 IN2P IN2M AMP2 OUT2 IN3P IN3M AMP3 OUT3 IN4P IN4M AMP4 OUT4S Position Detection Circuit AVDD H + − 16 Data Sheet S17655EJ1V0DS µ PD168103A 9. PACKAGE DRAWING 48-PIN PLASTIC WQFN (7x7) HD D D /2 HD /2 4− C0.5 A A2 detail of P part E /2 36 37 25 24 c HE E HE /2 S 48 1 13 12 x4 f SAB A1 terminal section c2 c1 S x4 y S ZE ZD y1 S P B t SAB b1 b ITEM D (UNIT:mm) DIMENSIONS 6.75 6.75 0.20 7.00 7.00 0.20 0.67 + 0.08 − 0.04 0.03 + 0.02 − 0.025 0.64 0.23 ± 0.05 0.20 ± 0.03 0.17 0.14 ∼ 0.16 0.14 ∼ 0.20 0.50 0.40 ± 0.10 0.05 0.08 0.10 0.625 0.625 P48K9-50-5B4-1 A E f HD HE t A A1 A2 0.08MIN. b 0.08MIN. x e M Lp SAB b b1 c c1 c2 e Lp x y y1 ZD ZE NOTES 1 "t" AND "f" EXCLUDES MOLD FLASH 2 ALTHOUGH THERE ARE 4 TERMINALS IN THE CORNER PART OF A PACKAGE, THESE TERMINALS ARE NOT DESIGNED FOR INTERCONNECTION, BUT FOR MANUFACTURING PROCESS OF THE PACKAGE, THEREFOR DO NOT INTEND TO SOLDER THESE 4 TERMINALS, SOLDERABLITY OF THE 4 TERMINALS ARE NOT GUARANTEED. Data Sheet S17655EJ1V0DS 17 µ PD168103A 10. RECOMMENDED SOLDERING CONDITIONS The µ PD168103A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Surface Mount Device Note1 µ PD168103AK9-5B4-A Process Infrared reflow : 48-pin plastic WQFN (7 x 7) Conditions Symbol IR60-103-3 Note2 Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher) , Count: Three times or less, Exposure limit: 3 days (after that, prebake at 125°C for 10 hours) , Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. Products other than in heat-resistant trays (such as those packaged in a magazine, taping, or non-thermal-resistant tray) cannot be baked in their package. Notes 1. Pb-free (This product does not contain Pb in external electrode and other parts.) 2. After opening the dry pack, store it a 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 18 Data Sheet S17655EJ1V0DS µ PD168103A N OTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17655EJ1V0DS 19 µ PD168103A Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) • T he information in this document is current as of June, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. • NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1