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UPD16835

UPD16835

  • 厂商:

    NEC(日电电子)

  • 封装:

  • 描述:

    UPD16835 - MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT - NEC

  • 数据手册
  • 价格&库存
UPD16835 数据手册
DATA SHEET MOS INTEGRATED CIRCUIT µPD16835 MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT The µPD16835 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional driver ICs that use bipolar transistors. Because the µPD16835 controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been reduced. This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. The µPD16835 is housed in a 38-pin shrink SOP to contribute to the miniaturization of the application set. This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders. FEATURES • Four H bridge circuits employing power MOS FETs • Current-controlled 64-step micro step driving • Motor control by serial data (8 bytes × 8 bits) (original oscillation: 4-MHz input) Data is input with the LSB first. EVR reference setting voltage: 100 to 250 mV (@VREF = 250 mV) ... 4-bit data input (10-mV step) Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step) Original oscillation division or internal oscillation selectable Number of pulses in 1 VD: 0 to 252 pulses ... 6 bits + 2-bit data input (4 pulses/step) Step cycle: 0.25 to 8,191.75 µs ... 15-bit data input (0.25-µs step) • 3-V power supply. Minimum operating voltage: 2.7 V (MIN.) • Low current consumption IDD: 3 mA (MAX.), IDD (reset): 100 µA (MAX.), IMO: 1 µA (MAX.) • 38-pin shrink SOP (300 mil) ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter Supply voltage Symbol VDD VM Input voltage Reference voltage H bridge drive currentNote 1 currentNote 1 VIN VREF IM (DC) IM (pulse) PT TCH (MAX) Tstg DC PW ≤ 10 ms, Duty ≤ 5% Condition Rating -0.5 to +6.0 -0.5 to +11.2 -0.5 to VDD + 0.5 500 ± 150 ± 300 1.0 150 -55 to +150 Unit V V V mV mA/phase mA/phase W °C °C Instantaneous H bridge drive Power consumptionNote 2 Peak junction temperature Storage temperature Notes 1. Permissible current per phase with the IC mounted on a PCB. 2. When the IC is mounted on a glass epoxy PCB (10 cm × 10 cm × 1 mm). The information in this document is subject to change without notice. Document No. G11594EJ1V0DS00 (1st edition) Date Published August 1998 J CP(K) Printed in Japan © 1998 µPD16835 RECOMMENDED OPERATING RANGE Parameter Supply voltage VDD VM Input voltage Reference voltage EXP pin input voltage EXP pin input current H bridge drive current H bridge drive current Clock frequency (OSCIN) Clock frequency amplitude Serial clock frequency (SCLK) Video sync signal width LATCH signal wait time SCLK wait time SDATA setup time SDATA hold time Chopping frequency Reset signal pulse width Operating temperature Peak junction temperature VIN VREF VEXPIN IEXPIN IM (DC) IM (pulse)Note 1 fCLKNote 2 VfCLKNote 2 fSCLK PW t t (VD)Note Symbol MIN. 2.7 4.8 0 225 TYP. MAX. 5.5 11 VDD Unit V V V mV V 250 275 VDD 100 µA mA mA MHz V MHz ns ns ns ns ns -100 -200 3.9 0.7VDD 4 +100 +200 4.2 VDD 5.0 3 4 4 250 400 400 80 80 32 100 -10 +70 125 124 (VD-LATCH) Note (SCLK-LATCH) Note tsetupNote 4 tholdNote 4 foscNote 3 fRST TA TCH (MAX) kHz µs °C °C Notes 1. PW ≤ 10 ms, duty ≤ 5% 2. COSC = 33 pF, VREF = 250 mV 3. fCLK = 4 MHz 4. Serial data delay (see the figure below.) VD t (VD-LATCH) LATCH 64 clocks (8 bits × 8 bytes) SCLK t (SCLK-LATCH) t (SCLK-LATCH) Ignored because LATCH is at L level. Ignored because LATCH is at L level. LATCH 50% SDATA D1 50% 50% D2 D3 SCLK 2 t (SCLK-LATCH) tsetup thold µPD16835 ELECTRICAL CHARACTERISTICS DC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, VREF = 250 mV, TA = 25°C, fCLK = 4 MHz, COSC = 33 pF, CFIL = 1,000 pF, EVR = 100 mV (0000)) Parameter Off VM pin current VDD pin current VDD pin current High-level input voltage Low-level input voltage Input hysteresis voltage Monitor output voltage 1 (EXTOUT α, β) Monitor output voltage 2 (EXP 0 to 4: open drain) High-level input current Low-level input current Reset pin high-level input current Reset pin low-level input current Input pull-down resistor H bridge ON resistanceNote 1 Chopping frequency (internal oscillation: COSC = 100 pF) Step frequency VD delayNote 2 Sine wave peak output currentNote 3 FIL pin voltageNote 4 FIL pin step voltageNote 4 VEVR VEVRSTEP Symbol IMO (RESET) IDD IDD (RESET) VIH VIL VH VOMα (H), VOMβ (H) VOMα (L), VOMβ (L) VOEXP (H) VOEXP (L) IIH IIL IIH (RST) IIL (RST) RIND RON fOSC (1) fOSC (2) fSTEP ∆tVD IM L = 25 mH/R = 100 Ω (1 kHz) EVR = 200 mV (1010) RS = 6.8 Ω, fOSC = 64 kHz EVR = 200 mV (1010) Minimum step 370 52 5th byte 5th byte Pull up (VDD) IOEXP = 100 µA VIN = VDD VIN = 0 VRST = VDD VRST = 0 LATCH, SCLK, SDATA, VD IM = 100 mA DATA: 00000 (4th byte) DATA: 11111 (4th byte) Minimum step 100 -1.0 50 3.5 0 124 4 250 150 kHz ns mA 200 5.0 -1.0 1.0 0.9*VDD 0.1*VDD VDD 0.1*VDD 0.06 Condition No load, reset period Output open Reset period LATCH, SCLK, SDATA, VD, RESET, OSCIN 0.7*VDD 0.3*VDD 300 MIN. TYP. MAX. 1.0 3.0 100 Unit µA mA µA V V mV V V V V mA µA µA µA kΩ Ω kHz 400 20 430 mV mV AC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, TA = 25°C, fCLK = 4 MHz) Parameter H bridge output circuit turn on time H bridge output circuit turn off time tONH tOFFH Symbol Condition IM = 100 mANote 5 IM = 100 mANote 5 MIN. TYP. 1.0 1.0 MAX. 2.0 2.0 Unit µs µs Notes 1. Total of ON resistance at top and bottom of output H bridge 2. By OSCIN and VD sync circuit 3. FB pin is monitored. 4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin. 5. 10% to 90% of the pulse peak value without filter capacitor (CFIL) 3 µPD16835 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 EXP2 RESET OSCOUT OSCIN SCLK SDATA LATCH VD EXTβ B2 FBB B1 VM2 A2 FBA A1 VM1 EXTα EXP3 PGND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 4 µPD16835 PIN FUNCTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Name LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 EXP2 PGND EXP3 EXTα VM1 A1 FBA A2 VM2 B1 FBB B2 EXTβ VD LATCH SDATA SCLK OSCIN OSCOUT RESET Control circuit GND pin Chopping capacitor connection pin Function α 1-ch filter capacitor connection pin (1,000 pF TYP.) α 2-ch filter capacitor connection pin (1,000 pF TYP.) β 1-ch filter capacitor connection pin (1,000 pF TYP.) β 2-ch filter capacitor connection pin (1,000 pF TYP.) Reference voltage input pin (250 mV TYP.) Control circuit supply voltage input pin Output circuit supply voltage input pin β 2-ch output pin β 2-ch sense resistor connection pin β 2-ch output pin Output circuit supply voltage connection pin β 1-ch output pin β 1-ch sense resistor connection pin β 1-ch output pin Output monitor pin (open-drain) Output monitor pin (open-drain) Output monitor pin (open-drain) Power circuit GND pin Output monitor pin (open-drain) Logic circuit monitor pin Output circuit supply voltage input pin α 1-ch output pin α 1-ch sense resistor connection pin α 1-ch output pin Output circuit supply voltage input pin α 2-ch output pin α 2-ch sense resistor connection pin α 2-ch output pin Logic circuit monitor pin Video sync signal input pin Latch signal input pin Serial data input pin Serial clock input pin Original oscillation input pin (4 MHz TYP.) Original oscillation output pin Reset signal output pin 5 µPD16835 I/O PIN EQUIVALENT CIRCUIT Pin name Equivalent circuit Pin name Equivalent circuit VDD VDD VDD LATCH SDATA SCLK Pad Pull-down resistor (125 Ω) OSCIN RESET Pad VDD VDD OSCOUT EXTα EXTβ Pad EXP0 EXP1 EXP2 EXP3 Pad VDD VDD VREF Pad FILA FILB FILC FILD Pad Buffer VM A1, A2 B1, B2 C1, C2 D1, D2 Parasitic diodes Pad FB 6 BLOCK DIAGRAM OSCIN 37 RESET VDD VM1 VM2 VM3 VM4 38 8 23 OSCOUT 36 VD 32 VREF 7 SCLK 35 SDATA 34 LATCH 33 EXP0 EXP1 EXP2 EXP3 17 18 19 21 ×2 SERIAL-PARARELLE DECODER 27 9 1/N 13 EVR1 COSC 2 SELECTOR OSC EVR2 EVR1 EVR2 22 31 EXTα EXTβ PULSE GENERATER EXTOUT SELECTOR CURRENT SET α CURRENT SET β + + + + + FILTER VM - + FILTER VM - + FILTER VM - + FILTER VM DGND 1 PGND 20 H BRIDGE α 1 ch H BRIDGE α 2 ch H BRIDGE β 1 ch H BRIDGE β 2 ch µPD16835 25 FBA A1 24 A2 26 3 FBB 29 B1 28 B2 30 4 FBC 15 C1 16 C2 14 5 FBD 11 D1 12 D2 10 6 FILA FILB FILC FILD 7 8 CPU 250 mV EVR : 1010 fOSC : 64 kHz 100 kΩ × 4 OSCOUT VD VREF SCLK SDATA LATCH EXP0 EXP1 EXP2 EXP3 4 MHz OSCIN RESET REGULATOR 3.3 V VDD VM1 VM2 VM3 1/N VM4 EVR1 EVR2 COSC BATTERY 4.8 V-11 V 33 pF + + + + + EXAMPLE OF STANDARD CONNECTION ×2 SERIAL-PARARELLE DECODER PULSE GENERATER EVR1 EVR2 CURRENT SETβ EXTOUT SELECTOR SELECTOR OSC CURRENT SETα EXTα EXTβ FILTER VM - + FILTER VM - + FILTER VM - + FILTER VM DGND PGND H BRIDGE α 1 ch H BRIDGE α 2 ch H BRIDGE β 1 ch H BRIDGE β 2 ch FBA 6.8 Ω × 2 A1 A2 FILA FBB B1 B2 FILB FBC 6.8 Ω C1 C2 FILC FBD D1 D2 FILD 1000 pF 6.8 Ω 1000 pF 1,000 pF × 2 MOTOR 1 MOTOR 2 µPD16835 Initialization RESET VD LATCH Initial DATA I1 EXP: 1 OSCOUT (original oscillation) Start point wait (FF1) Start point wait + start point drive wait (FF2) ENABLE OUTNote 1 Chopping pulse EXP_0-3 PULSE OUT PULSE GATE (FF3) PULSE CHECKNote 2 (FF7) CHECK SUMNote 3 Output by chopping setting of I1 data Output by EXP setting of I1 data Output by EXP setting of S1 data S2DATA output Outputs high level while pulse is being generated Outputs high level for standard data while a pulse output signal exists (LATCH cycle) High level because data is normal. Low level because data is abnormal. No pulse output because data is erroneous Restore to high level because data is normal. Output by EXP setting of S2DATA S4DATA output Pulse error Input at rising edge of RESET Output by I1 data Output by I1 data Output by S2 data setting Output by S5 data setting Standard Dummy data S1 EXP :0 ENABLE: 0 S2 Standard EXP :1 ENABLE: 1 Standard EXP : 1 error DATA Standard S4 EXP :0 ENABLE: 1 Standard S5 EXP :1 ENABLE: 0 TIMING CHART (1) S3 Enable SCLK SDATA 1st byte → 8th byte Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low to high, and at the falling edge of FF2 when the level changes from high to low. D0 D1 D2 D3 D4 D5 D6 D7 µPD16835 2. FF7 is an output signal that is used to check for the presence or absence of a pulse in the standard data, is updated at the falling edge of LATCH and reset once at the rising edge of LATCH. If CHECK SUM is other than “00h”, FF7 goes low, inhibiting pulse output, even if a pulse is generated. 3. CHECK SUM output is updated at the falling edge of LATCH. (LSB) Data is held at rising edge of SCLK. 9 µPD16835 TIMING CHART (2) CLK (PULSE OUT) MOB (CW mode) Current direction: A2 → A1 Current direction: A1 → A2 H bridge α , β 1-ch output status H bridge α , β 2-ch output status Current direction: B2 → B1 Current direction: B2 → B1 Current direction: B1 → B2 (Expanded view) CW mode CLK PULSE OUT Position No. 1 2 3 4 5 6 5 4 3 2 3 CCW H bridge 1-ch output status CW CW CCW 4 CCW mode CW mode Note In CW mode : Position No. is incremented. In CCW mode : Position No. is decremented. CW CW H bridge 2-ch output status CCW CW CW CCW Remarks 1. The current value of the actual wave is approximated to the value shown on the next page. 2. The C1, C2, D1, and D2 pins of β channel correspond to the A1, A2, B1, and B2 pins of α channel. 3. The CW mode is set if the D7 bit of the second and fifth bytes of the standard data is “0”. 4. The CCW mode is set if the D7 bit of the second and fifth bytes of the standard data is “1”. 10 µPD16835 RELATION BETWEEN ROTATION ANGLE, PHASE CURRENT, AND VECTOR QUANTITY (64-DIVISION MICRO STEP) (Values of µPD16835 for reference) Step Rotation angle (θ ) MIN. A phase current TYP. 0 9.8 19.5 29.1 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 MAX. 17.0 26.5 36.1 45.3 54.1 62.6 68.4 75.7 82.3 88.1 93.2 97.4 100.7 103 MIN. 93.2 90.7 87.4 83.2 78.1 72.3 65.7 58.4 48.6 40.1 31.3 22.1 12.4 2.5 B phase current TYP. 100 100 98.1 95.7 92.4 88.2 83.1 77.3 70.7 63.4 55.6 47.1 38.3 29.1 19.5 9.8 0 MAX. 103 100.7 97.4 93.2 88.1 82.3 75.7 68.4 62.6 54.1 45.3 36.1 26.5 17.0 Vector quantity TYP. 100 100.48 100 100.02 100.02 99.99 99.98 99.97 99.98 99.97 99.98 99.99 100.02 100.02 100 100.48 100 θ0 θ1 θ2 θ3 θ4 θ5 θ6 θ7 θ8 θ9 θ 10 θ 11 θ 12 θ 13 θ 14 θ 15 θ 16 0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90 2.5 12.4 22.1 31.3 40.1 48.6 58.4 65.7 72.3 78.1 83.2 87.4 90.7 93.2 - Remark These data do not indicate guaranteed values. 11 µPD16835 STANDARD CHARACTERISTIC CURVES PT vs. TA characteristics 1.4 1.2 Total power dissipation PT (W) IMO (RESET) vs. VM characteristics 1 OFF VM pin current IMO (RESET) (µ A) 0.8 TA = 25°C, no load, after reset 1.0 125°C/W 0.8 0.6 0.4 0.2 0 -10 0 0.6 0.4 0.2 20 40 60 80 100 Ambient temperature TA (°C) 120 0 4 6 8 10 Output circuit supply voltage VM (V) 12 IDD vs. VDD characteristics 5 VDD pin current at reset state IDD (RESET) (µA) IDD (RESET) vs. VDD characteristics 200 TA = 25°C, after reset 150 4 VDD pin current IDD (mA) TA = 25°C, operating, output open 3 100 2 50 1 0 2 3 4 5 Control circuit supply volage VDD (V) 6 0 2 3 4 5 Control circuit supply volage VDD (V) 6 VIH/VDD, VIL/VDD vs. VDD characteristics 1 TA = 25°C Input voltage VIH/VDD, VIL/VDD High-level/low-level input current IIH/IIL (µ A) IIH/IIL vs. VIN characteristics 60 TA = 25°C, IIH: VIN = VDD, IIL: VIN = 0 0.8 40 IIH 0.6 VIH VIL 0.4 20 0.2 0 2 3 IIL 5 4 Input voltage VIN (V) 6 0 2 3 4 5 Control circuit supply volage VDD (V) 6 12 µPD16835 fOSC vs. VDD characteristics 150 TA = 25°C, COSC = 100 pF, DATA: all high Step frequency fSTEP (kHz) fSTEP vs. VDD characteristics 6 TA = 25°C, COSC = 100 pF Chopping frequency fOSC (kHz) 140 5 130 120 4 110 3 100 90 2 3 4 5 Control circuit supply voltage VDD (V) 6 2 2 3 4 5 Control circuit supply voltage VDD (V) 6 VREFVER vs. VDD characteristics 40 EVR variable voltage VREFVER (mV) IM (MAX) vs. EVR characteristics 80 Sine wave peak output current IM (MAX) (mA) TA = 25°C, VREF = 250 mV 70 TA = 25°C, VM = 6 V Rs = 6.8 Ω, fOSC = 64 kHz, L = 25 mH/R = 100 Ω at 1 kHz 30 60 20 50 40 10 30 0 2 5 3 4 Control circuit supply voltage VDD (V) 6 20 50 100 150 200 250 Reference setting voltage EVR (mV) 300 tON, tOFF vs. VM characteristics 500 Turn-on time, turn-off time tON/tOFF (ns) 400 TA = 25°C, IM = 100 mA, CFIL: none 300 tON tOFF 200 100 0 4 10 6 8 Output circuit supply voltage VM (V) 12 13 µPD16835 I/F CIRCUIT DATA CONFIGURATION (fCLK = 4-MHz EXTERNAL CLOCK INPUT) Input data consists of serial data (8 bytes × 8 bits). Input serial data with the LSB first, from the first byte to eighth byte. (1) Initial data Bit D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 or 0 1 or 0 1 or 0 1 or 0 EXP_3 EXP_2 EXP_1 EXP_0 Data Function HEADER DATA2 HEADER DATA1 HEADER DATA0 Z or L Z or L Z or L Z or L Setting DATA selection (2) Standard data Bit D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 or 0 1 or 0 1 or 0 1 or 0 EXP_3 EXP_2 EXP_1 EXP_0 Data Function HEADER DATA2 HEADER DATA1 HEADER DATA0 Z or L Z or L Z or L Z or L Setting DATA selection Z: High impedance, L: Low level (current sink) Bit D7 D6 D5 D4 D3 D2 D1 D0 Setting (1 to 255) ∆t = 256 µs Data Function Setting Start point wait 256 µs to 65.28 ms Z: High impedance, L: Low level (current sink) Bit D7 D6 D5 D4 D3 D2 D1 D0 Setting (0 to 63) ∆n = 4 pulsesNote Data 1 or 0 1 or 0 6-bit data input Function Setting 8-bit data First Point Wait inputNote α ROTATION α ENABLE α Pulse Number α ch CCW/CW α ch ON/OFF α ch Number of pulses in 1 V Note Input other than “0”. Note The number of pulses can be varied in 4-pulse steps. Bit D7 D6 D5 D4 D3 D2 D1 D0 Setting (1 to 255) ∆t = 256 µs Data Function Setting Start point drive wait 256 µs to 65.28 ms Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 15-bit data Low-order 8-bit data input Function Setting 8-bit data First Point inputNote Magnetize Wait α Pulse Width α ch pulse cycle 0.25 to 8,191.75 µs Setting (1 to 32,767) ∆t = 0.25 µs Note Input other than “0”. 14 µPD16835 Bit D7 D6 D5 D4 D3 D2 D1 D0 Setting (8 to 31)Note ∆f = 4 kHz Data 1 or 0 0 0 Function OSCSEL Setting Internal/external Chopping frequency: 32 to 124 kHz Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 15-bit data High-order 8-bit data input Function Current Set α Setting set2/set1 α Pulse Width 5-bit data Chopping input Frequency α ch pulse cycle: 0.25 to 8,191.75 µs Setting (1 to 32,767) ∆t = 0.25 µs Note The frequency is 0 kHz if 0 to 7 is input. EXT_α ENABLE α Note 1 EXT_β ENABLE β Note 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Setting (1 to 63) ∆n = 4 pulsesNote Data 1 or 0 1 or 0 6-bit data input Function Setting Bit D7 D6 D5 D4 D3 D2 D1 D0 0 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Data β ROTATION β ENABLE β Pulse Number β ch CCW/CW β ch ON/OFF β ch Number of pulses in 1 V ROTATION α Note 2 ROTATION β Note 2 Pulse Out α FF7 α FF3 α ChecksumNote 3 ChoppingNote 4 Pulse Out β FF7 β FF3 β FF2 β FF1 β Notes 1. H level: Conducts, L level: Stops 2. H level: Reverse (CCW), L level: Forward (CW) 3. H level: Normal data input, L level: Abnormal data input 4. Not output in internal oscillation mode. 5. Select one of D0 to D6 and input “1”. If two or more of D0 to D6 are selected, they are positively ORed for output. Bit D7 D6 D5 D4 D3 D2 D1 D0 4-bit data α ch input Current Set1 Data Function Setting 4-bit data α ch input Current Set2 Note The number of pulses can be varied in 4-pulse steps. Bit D7 D6 D5 D4 Data 15-bit data Low-order 8-bit data input Function Setting α ch Output current setting 2 EVR: 100 to 250 mV Setting (0 to 15)Note α ch Output current setting 1 EVR: 100 to 250 mV Setting (0 to 15)Note β Pulse Width β ch pulse cycle: 0.25 to 8,191.75 µs Setting (1 to 32,767) ∆t = 0.25 µs D3 D2 D1 D0 Note A voltage of about double EVR is output to the FIL pin. 15 µPD16835 Bit D7 D6 D5 D4 D3 D2 D1 D0 4-bit data β ch input Current Set1 Data Function Setting Bit D7 D6 D5 D4 Data 1 or 0 15-bit data High-order 7-bit data input Function Current Set β Setting set2/set1 4-bit data β ch input Current Set2 β ch Output current setting 2 EVR: 100 to 250 mV Setting (0 to 15)Note β ch Output current setting 1 EVR: 100 to 250 mV Setting (0 to 15)Note β Pulse Width β ch pulse cycle: 0.25 to 8,191.75 µs Setting (1 to 32,767) ∆t = 0.25 µs D3 D2 D1 D0 Note A voltage of about double EVR is output to the FIL pin. Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 Function Checksum Setting ChecksumNote Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 Function Checksum Setting ChecksumNote Note Data is input so that the sum of the first through the eighth bytes is 00h. Note Data is input so that the sum of the first through the eighth bytes is 00h. 16 µPD16835 DATA CONFIGURATION Data can be input in either of two ways. Initial data can be input when the power is first applied, or standard data can be input during normal operation. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the first byte. Therefore, the D7 bit of the eighth byte is the most significant bit (MSB). When inputting initial data, set a start-point wait time that specifies the delay from power application to pulse output, and the start-point drive wait time. At the same time, also set a chopping frequency and a reference voltage (EVR) that determines the output current of each channel. Because the µPD16835 has an EXT pin for monitoring the internal operations, the parameter to be monitored can be selected by initial data. When inputting standard data, input the rotation direction of each channel, the number of pulses, and the data for the pulse cycle. Initial data or standard data is selected by using bits D5 to D7 of the first byte (see Table 1). Table 1. Data Selection Mode (1st byte) D7 1 0 D6 1 0 D5 1 0 Data type Initial data Standard data If the high-order three bits are high, the initial data is selected; if they are low, the standard data is selected. Data other than (0, 0, 0) and (1, 1, 1) must not be input. Input the serial data during start-point wait time. Details of Data Configuration How to input initial data and standard data is described below. (1) Initial data input The first byte specifies the type of data (initial data or standard data) and determines the presence or absence of the EXP pin output. Bits D5 to D7 of this byte specify the type of data as shown in Table 1, while bits D0 to D3 select the EXP output (open drain). Table 2. First Byte Data Configuration Bit Data D7 1 D6 1 D5 1 D4 0 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 The EXP pin goes low (current sink) when the input data is “0”, and high (high-impedance state) when the input data is “1”. Pull this pin up to VDD for use. Input “0” to bit D4. The second byte specifies the delay between data being read and data being output. This delay is called the start-up wait time, and the motor can be driven from that point at which the start-up wait time is “0”. This time is counted at the rising edge of VD. The start-up wait time can be set to 65.28 ms (when a 4-MHz clock is input), and can be fine-tuned by means of 8-bit division (256-µs step: with 4-MHz clock). The start-up wait time is set to 65.28 ms when all the bits of the second byte are set to “1”. Always input data other than “0” to this byte because the start-up wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. Transfer standard data during the start-up wait time. 17 µPD16835 The third byte specifies the delay between the start-point wait time being cleared and the output pulse being generated. This time is called the start-up drive wait time, and the output pulse is generated from the point at which the start-up drive wait time reaches “0”. The start-up drive wait time is counted at the falling edge of the start-up wait time. The start-up drive wait time can be set to 65.28 ms (with 4-MHz clock) and can be fine-tuned by means of 8-bit division (256-µs step: with 4-MHz clock). The start-up drive wait time is set to 65.28 ms when all the bits of the third byte are “1”. Always input data other than “0” to this byte because the start-up drive wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. The fourth byte selects a chopping frequency by using 5-bit data. It also selects whether the chopping frequency is created by dividing the original oscillation (external clock) or whether the internal oscillator is used. The chopping frequency is selected by bits D0 to D4. Bit D7 specifies the method used to create the chopping frequency. When this bit is “0”, the original oscillation (external clock input to OSCIN) is used; when it is “1”, the internal oscillator is used. Bits D5 and D6 are fixed to “0”. The chopping signal is output after the initial data has been input and the first standard data has been latched (see Timing Chart). Table 3. Fourth Byte Data Configuration (Initial data) Bit Data D7 0 or 1 D6 0 D5 0 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 The chopping frequency is set to 0 kHz and to a value in the range of 32 to 124 kHz (in 4-kHz steps), as follows. Although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the loworder 2 bits fixed to 0). Bit Data D7 0 or 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 fOSC = 0 kHz 0 Bit Data D7 0 or 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 1 D0 fOSC = 0 kHz 1 Bit Data D7 0 or 1 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 fOSC = 32 kHz 0 Bit Data D7 0 or 1 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 fOSC = 36 kHz 1 Bit Data D7 0 or 1 D6 0 D5 0 D4 1 D3 1 D2 1 D1 1 D0 fOSC = 124 kHz 1 18 µPD16835 The fifth byte selects a parameter to be output to the EXTOUT pin (logic operation monitor pin). Input data to bits D0 to D6 of this byte. Bit D7 is fixed to “0”. There are two EXTOUT pins. EXTOUT α indicates the operating status of α ch, and EXTOUT β indicates that of β ch. The relationship between each bit and each EXTOUT pin is as shown in Table 4. Table 4. Fifth Byte Data Configuration (Initial data) Bit D7 D6 D5 D4 D3 D2 D1 D0 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Data EXTOUT α Not used ENABLE α ROTATION α PULSEOUT α FF7 α FF3 α CHECKSUM CHOPPING EXTOUT β Not used ENABLE β ROTATION β PULSEOUT β FF7 β FF3 β FF2 β FF1 β The checksum bit is cleared to “0” in the event of an error. Normally, it is “1”. If two or more signals that output signals to EXTOUT α and EXTOUT β are selected, they are positively ORed for output. The CHOPPING signal is not output in internal oscillation mode. The meanings of the symbols listed in Table 4 are as follows: ENABLE: ROTATION: FF7: FF3: FF2: FF1: Output setting (H: Conducts, L: Stops) Rotation direction (H: Reverse (CCW), L: Forward (CW)) Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in standard data.) Pulse gate (output while pulse exists) Outputs H level during start-up wait time + start-up drive wait time Outputs H level during start-up wait time PULSEOUT: Output pulse signal CHECKSUM: Checksum output (H: when normal data is transmitted, L: when abnormal data is transmitted) CHOPPING: Chopping wave output (in original oscillation mode only) 19 µPD16835 The sixth byte sets the peak output current value of α ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within the range of 200 to 500 mV, in units of 20 mV. The µPD16835 can set two values of the EVR reference voltage in advance. This is done by using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT_SET bit in the standard data. If all the bits of the sixth byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR reference voltage of 500 mV is selected. Table 5. Sixth Byte Data Configuration (Initial data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRα2) Bits D0 to D3: Reference voltage 1 (EVRα1) The seventh byte specifies the peak output current value of β ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within a range of 200 to 500 mV, in units of 20 mV. The µPD16835 can set two values of the EVR reference voltage in advance. This is done using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT_SET bit in the standard data. If all the bits of the seventh byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR reference voltage of 500 mV is selected. Table 6. Seventh Byte Data Configuration (Initial data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRβ2) Bits D0 to D3: Reference voltage 1 (EVRβ1) The eighth byte is checksum data. Normally, the sum of the 8-byte data is 00h. If the sum is not 00h because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is kept “L”. 20 µPD16835 (2) Standard data input The first byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is input. Table 7. First Byte Data Configuration Bit Data D7 1 D6 1 D5 1 D4 0 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 The EXP pin goes low (current sink) when the input data is “0”, and high (high-impedance state) when the input data is “1”. Input “0” to bit D4. The second byte specifies the rotation direction of the α channel, enables output of the α channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in 1 cycle of FF2) of the α channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is “0”; it is in the reverse direction (CCW mode) when the bit is “1”. Bit D6 is used to enable the output of the α channel. The α channel enters the high-impedance state when this bit is “0”; it is in conduction mode when the bit is “1”. The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit uses an 8-bit counter with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually generated during start-up wait time + start-up drive wait (FF2) cycle is the number of pulses input × 4. The number of pulses can be set to a value in the range of 0 to 252, in units of four pulses. Table 8. Second Byte Data Configuration (Standard data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Rotation direction ENABLE Number of pulses 21 µPD16835 The third and fourth bytes select the pulse cycle of the α channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SET α). The pulse cycle is specified using 15 bits: bits D0 (least significant bit) to D7 of the third byte, and bits D0 to D6 (most significant bit) of the fourth byte. The pulse cycle can be set to a value in the range of 0.25 to 8,191.75 µs in units of 0.25 µs (with a 4-MHz clock). CURRENT SET α is specified by bit D7 of the fourth byte. When this bit is “0”, reference voltage 1 (EVRα1) is selected; when it is “1”, reference voltage 2 (EVRα2) is selected. For further information, refer to the description of the sixth byte of the initial data. Table 9. Fourth Byte Data Configuration (Standard data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Table 10. Third Byte Data Configuration (Standard data) D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 CURRENT SET α Most significant bit Least significant bit (Reference) Sixth Byte Data Configuration for Initial Data Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRα2) Bits D0 to D3: Reference voltage 1 (EVRα1) The fifth byte specifies the rotation direction of the β channel, enables output of the β channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in one cycle of FF2) of the β channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is “0”; it is in the reverse direction (CCW mode) when the bit is “1”. Bit D6 is used to enable the output of the β channel. The β channel goes into a high-impedance state when this bit is “0”; it is in the conduction mode when the bit is “1”. The number of pulses is set by bits D0 to D5. It is set by six bits in terms of software. However, the actual circuit uses an 8-bit decoder with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually generated during start-up wait time + start-up drive wait (FF2) cycle is the number of pulses input × 4. The number of pulses can be set in a range of 0 to 252 and in units of four pulses. Table 11. Fifth Byte Data Configuration (Standard data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Rotation direction ENABLE Number of pulses 22 µPD16835 The sixth and seventh bytes select the pulse cycle of the β channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SET β). The pulse cycle is specified using 15 bits: bits D0 (least significant bit) to D7 of the sixth byte, and bits D0 to D6 (most significant bit) of the seventh byte. The pulse cycle can be set to a value in the range of 0.25 to 8,191.75 µs in units of 0.25 µs (with a 4-MHz clock). CURRENT SET β is specified by bit D7 of the seventh byte. When this bit is “0”, reference voltage 1 (EVRβ1) is selected; when it is “1”, reference voltage 2 (EVRβ2) is selected. For further information, refer to the description of the seventh byte of the initial data. Table 12. Seventh Byte Data Configuration (Standard data) Bit Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Table 13. Sixth Byte Data Configuration (Standard data) D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 CURRENT SET β Most significant bit Least significant bit (Reference) Seventh Byte Data Configuration for Initial Data Bit Data D7 D6 D5 D4 D3 D2 D1 D0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Bits D4 to D7: Reference voltage 2 (EVRβ2) Bits D0 to D3: Reference voltage 1 (EVRβ1) The eighth byte is checksum data. Normally, the sum of the 8-byte data is 00h. If the sum is not 00h because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is held at “L”. Data Update Timing The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product are set and updated at the following latch timing. Table 14. Data Update Timing ENABLE change Pulse width Number of pulses Rotation direction Current setting ENABLE 1→1 FF2 ↓ FF2 ↓ FF2 ↓ FF2 ↓ FF2 ↓ 0→1 FF2 ↓ FF2 ↓ FF2 ↓ FF1 ↓ FF1 ↓ 1→0 FF2 ↓ FF2 ↓ FF2 ↓ FF2 ↓ FF2 ↓ 0→0 - 23 µPD16835 The timing at which data is to be updated differs, as shown in Table 14, depending on the enabled status. For example, suppose the enable signal is currently “0” (output high-impedance) and “1” (output conduction) is input by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at FF2 (upon the completion of start-up wait), and the current setting and ENABLE signals are updated at FF1 (upon completion of start-up drive wait). VD FF1 Start-up wait FF2 Start-up wait + start-up drive wait Pulse output Pulse width, number of pulses, and rotation direction are updated. Current setting and ENABLE are updated (ENABLE change: 0 to 1). VD (1) LATCH I1 S1 (2) S2 (3) S3 Initial data identification Standard data identification → I1 data is output. FF1, FF2 output (1) Pulse width Rotation direction Number of pulses Internal data retained. Output reset Internal output retained Internal data retained. Output reset Internal output retained Internal output retained Not output Not output Not output (2) (3) Updated to S2 data at FF2 Current setting ENABLE Not output Not output Updated to S2 data at either FF1 or FF2 by enable data of (2) 24 µPD16835 The initial mode of this product is as follows. The IC operation can be initialized as follows: (1) Turns ON VDD. (2) Make RESET input “L”. (3) Input serial initial data. In initial mode, the operating status of the IC is as shown in Table 15. Table 15. Operations in Initial Mode Item Current consumption OSC VD FF1 to FF7 PULSE OUT EXP0 to EXP3 100 µA Oscillation stops. Input of external clock is inhibited. Input inhibited. “L” level “L” level Undefined in the case of (1) above. Previous value is retained in the case of (2) above. Can be updated by serial data in the case of (3) above. Serial operation Can be accessed after initialization in the case of (1) above. Can be accessed after RESET has gone “H” in the case of (2) above. Can be accessed in the case of (3) above. Specifications Step pulse output is inhibited and FF7 is made “L” if the following conditions are satisfied. (1) If the set number of pulses (2nd/5th: standard data) is 00h. (2) If the checksum value is other than 00h. (3) If the start-up wait time is set to 1VD or longer. (4) If the start-up wait time + start-up drive wait time is set to 1VD or longer. (5) If start-up wait is completed earlier than LATCH (↓). (6) If VD is not input. 25 µPD16835 HINTS ON CORRECT USE (1) With this product, input the data for start-up wait and start-up drive wait. Because the standard data are set or updated by these wait times, if the start-up wait time and start-up drive wait time are not input, the data are not updated. (2) The start-up wait time must be longer than LATCH. (3) If the rising of the start-up drive wait time is the same as the falling of the last output pulse, a count error occurs, and the IC may malfunction. (4) Input the initial data in a manner that it does not straddle the video sync signal (VD). If it does, the initial data is not latched. (5) Transmit the standard data during the start-up wait time (FF1). If it is input at any other time, the data may not be transmitted correctly. (6) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to prevent the leakage of noise from the output circuit. 26 µPD16835 PACKAGE 38 PIN PLASTIC SHRINK SOP (300 mil) 38 20 detail of lead end P 1 A 19 F G S H I J C D E M M N S B K L NOTE 1. Controlling dimension millimeter. ITEM A B C D E F G H I J K L M N P MILLIMETERS 12.45+0.26 –0.2 0.51 MAX. 0.65 (T.P.) 0.32+0.08 –0.07 0.125 ± 0.075 2.0 MAX. 1.7 ± 0.1 8.1 ± 0.3 6.1 ± 0.2 1.0 ± 0.2 0.17 +0.08 –0.07 0.5 ± 0.2 0.10 0.10 ° 3 °+7° –3 INCHES 0.490+0.011 –0.008 0.020 MAX. 0.026 (T.P.) 0.013 +0.003 –0.004 0.005 ± 0.003 0.079 MAX. 0.067 ± 0.004 0.319 ± 0.012 0.240 ± 0.008 0.039+0.009 –0.008 0.007+0.003 –0.004 0.020+0.008 –0.009 0.004 0.004 ° 3 °+7° –3 P38GS-65-300B-2 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 27 µPD16835 RECOMMENDED SOLDERING CONDITIONS This product should be soldered under the following conditions. For details of the soldering method and when soldering under conditions other than those given below, contact NEC. • For details of the recommended soldering conditions, refer to the Semiconductor Device Mounting Technology Manual. Soldering method Soldering conditions Symbol indicating recommended soldering Infrared reflow Package peak temperature: 235°C, Time: 30 seconds MAX. (at 210°C MIN.), IR35-00-3 Number of times: 3 MAX., Number of days: NoneNote, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% MAX.) is recommended. Package peak temperature: 215°C, Time: 40 seconds MAX. (at 200°C MIN.), VP-15-00-3 Number of times: 3 MAX., Number of days: NoneNote, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% MAX.) is recommended. Package peak temperature: 260°C, Time: 10 seconds MAX., Preheating temperature: 120°C MAX., Number of times: 1, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% MAX.) is recommended. WS60-00-1 VPS Wave soldering Note Number of days the device can be stored after the dry pack has been opened, at conditions of 25°C, 65% RH. Caution Do not use two or more soldering methods in combination. 28 µPD16835 [MEMO] 29 µPD16835 [MEMO] 30 µPD16835 [MEMO] 31 µPD16835 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5
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