UPD17P068

DATA SHEET MOS INTEGRATED CIRCUIT µ PD17P068 4-BIT SINGLE-CHIP MICROCONTROLLER WITH ON-CHIP HARDWARE FOR TV SYSTEMS T he µPD17P068 is a one-time PROM version of the µ PD17068 that has on-chip mask ROM. The µ PD17P068, which can be programmed only once, is suited for testing during development of µ PD17068 systems and limited production runs. Use this data sheet together with µ PD17068 documents. The µPD17P068 does not provide a level of reliability intended for mass production of the customer's products. Use it only for functional evaluation when experimenting or doing product trial tests. FEATURES • Compatible with the µPD17068 • One-time PROM : 12160 × 16 bits • Operating voltage : VDD = 5 V ± 10 % ORDERING INFORMATION Part Number Package 100-pin plastic QFP (14 × 2 0mm) µ PD17P068GF-3BA The information in this document is subject to change without notice. Document No. U10336EJ1V0DS00 Date Published November 1995 P Printed in Japan © 1995 µPD17P068 FUNCTIONAL OUTLINE Part Number Item µPD17068 Mask ROM µPD17P068 One-time PROM Program memory (ROM) • 12160 × 16 bits Table reference area: 12160 × 16 bits • 6144 × 16 bits • 1007 × 4 bits (including area serving also as VRAM) Data buffer: 4 × 4 bits, general register: 16 × 4 bits • 672 × 4 bits (also used as data memory (RAM)) • 12 × 4 bits • 12 × 4 bits • 12 × 4 bits • 2 µs (when using 8-MHz crystal resonator) • 12 levels (stack manipulation possible) • I/O ports • Input ports • Output ports : 19 :4 : 21 : 192 characters max. per screen (up to 350 characters with program) : 16 × 16-dot mode 15 lines × 24 columns : 14 × 16-dot mode 17 lines × 24 columns : 255 types (user programmable) : 16 × 16 dots and 14 × 16 dots selectable (2 dots can be placed between characters) : 15 colors : Vertical : 16 sizes (specifiable for each line) Horizontal : 24 sizes (specifiable for each character) Character ROM (CROM) Data memory (RAM) Video RAM (VRAM) System register Register file General port register Instruction execution time Stack levels General ports • Number of displayable characters • Display format IDC (Image Display Controller) • Character types • Character format • Color • Character size Serial interface • 2 systems Serial interface 0 (compatible with 2-wire system, 3-wire system and I2C Bus) Serial interface 1 (3-wire system) • 8 bits × 9 channels (PWM output, 12.5 V max.) • 6 bits × 8 channels (successive approximation by software) • 10 channels (maskable interrupt) External interrupt : 3 channels (INT0, INTNC, VSYNC, HSYNC) Internal interrupt : 7 channels (timer 0, 1, serial interface 0, 1, basic timer 2, VRAM pointer, timer 0 overflow) D/A converter A/D converter Interrupt 2 µPD17P068 Part Number Item Timer 0 Timer 1 Basic timer 0 Basic timer 1 Basic timer 2 Watch timer µPD17068 : : : : : : µPD17P068 Timer 10 µs to 204.75 ms (interrupt) 1 µs to 256 ms (interrupt) 1, 5, 100 ms (carry) 125 µs, 1 ms, 5 ms, 100 ms, external (carry) 125 µs, 1 ms, 5 ms, 100 ms, external (interrupt) Date, Hour, Minute, Second (counter) Reset • Power-on reset • Reset with CE pin (CE pin: Low level → High level) • Power interruption detection Supply voltage Package VDD = 5 V ± 10 % 100-pin plastic QFP (14 × 20 mm) 3 µPD17P068 BLOCK DIAGRAM VCO PSC EO OSCIN OSCOUT HSYNC VSYNC RED GREEN BLUE BLANK I (P0B 2) Hsync Counter Instruction Decoder ALU OSC Watch Timer IDC RF PLL RAM 1007 × 4 bits OSC Circuit VRAM (672 × 4 bits) SYSTEM REG. D/A Converter A/D Converter ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 (P0D 0/MD 0/XTOUT) (P0D 1/MD 1/XTIN) (P0D 2/MD 2) (P0D 3/MD 3) (P1C0/D 0) ADC7 (P1C2/D 2) PWM 0 (P2C0) PWM 3 (P2C3) PWM 4 (P2B 0) PWM 7 (P2B 3) PWM 8 (P2A 0) XTIN (P0D1/ADC2) XTOUT (P0D0/ADC1) CKOUT (P1B1) HSCNT (P0B 3) P0A 0-P0A 3 P0B 0-P0B 3 P0C0-P0C3 P0D 0-P0D 3 P1A 0-P1A 3 P1B 0-P1B 3 (D4-D7) P1C0-P1C3 P1D 0-P1D 3 P2A 0 4 4 4 4 4 4 Port 4 4 Timer0 One-time PROM 12160 × 16 bits CROM 6144 × 16 bits Timer1 Basic Timer0 Program Counter Basic Timer1 TMIN (P1B 3) Stack 12 × 14 bits Basic Timer2 SDA (P0A 0) P2B 0-P2B 3 P2C0-P2C 3 P2D 0-P2D 2 4 4 3 CPU Peripheral Serial I/O0 SCL (P0A1) SCK 0 (P0A 2) SO 0 (P0A 3) SI 0 (P0B 0) Main Oscillator Serial I/O1 SCK1 (P2D0) SO 1 (P2D1) SI 1 (P2D2) INT NC (VPP) INT 0 X IN/CLK XOUT VDD CE RLSSTP/P1B 2 GND0, GND1 Reset Interrupt 4 µPD17P068 PIN CONFIGURATION (Top View) (1) Normal operation mode P1D 2 P1D 1 P1D 0 INT 0 NC P1B 3 /TMIN P1B 2 /RLSSTP NC P1B 1 /CKOUT P1B 0 NC NC P1A 3 P1A 2 NC NC NC P1A 1 P1A 0 NC P2A 0 /PWM 8 NC NC P2D 2 /SI 1 P2D 1 /SO 1 P2D 0 /SCK1 NC GND 0 OSCOUT OSC IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P1D3 CE PSC EO VCO GND2 GND1 NC NC NC NC NC NC VDD1 VDD0 XIN XOUT INT NC XT OUT /ADC 1 /P0D 0 XT IN /ADC 2 /P0D 1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P0D 2 /ADC 3 P0D 3 /ADC 4 P1C0 /ADC 5 P1C1 /ADC 6 NC P1C2 /ADC 7 P1C3 NC ADC 0 NC P0C0 NC P0C1 NC P0C2 NC P0C3 NC P2C0 /PWM 0 NC P2C1 /PWM 1 NC P2C2 /PWM 2 NC P2C3 /PWM 3 NC P2B 0 /PWM 4 P2B 1 /PWM 5 P2B 2 /PWM 6 P2B 3 /PWM 7 RED GREEN NC BLUE BLANK HSYNC NC VSYNC P0B 3 /HSCNT NC NC P0B 2 /I P0B 1 NC P0B0 /SI 0 P0A3 /SO 0 P0A2 /SCK0 NC P0A 1 /SCL P0A 0 /SDA µ PD17P068GF-3BA 5 µPD17P068 (2) PROM programming mode (OPEN) (OPEN) (OPEN) (L)   (L)    (OPEN) GND 0 (OPEN) (L) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50    (OPEN)     (L) (OPEN) (L)    (OPEN)    (L)      (L)    (OPEN) Caution Contents in parentheses indicate how to handle unused pins in PROM programming mode. L: Connect to GND via a resistor (470 Ω) separately. OPEN: Leave unconnected. 6 (OPEN) (L)                                       (OPEN)    (L) (OPEN) D7 D6 (OPEN) D5 D4          (OPEN)           1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD1 VDD0 CLK (OPEN) VPP MD 0 MD 1 (L) GND 2 GND 1             µ PD17P068GF-3BA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MD 2 MD 3 D0 D1 (OPEN) D2 D3 (OPEN) µPD17P068 PIN IDENTIFICATIONS ADC 0-ADC 7 BLANK BLUE CE CKOUT CLK D 0-D 7 EO GND 0-GND 2 GREEN HSCNT H SYNC I INT 0, INT NC MD 0-MD 3 NC P0A 0-P0A 3 P0B 0-P0B 3 P0C 0-P0C 3 P0D 0-P0D 3 P1A 0-P1A 3 P1B 0-P1B 3 : A/D converter input : Blanking signal output : Character signal output : Chip enable : Watch timer adjustment output : Address update clock input : Data input/output : Error out : Ground : Character signal output : Horizontal synchronizing signal counter input : Horizontal synchronizing signal input : Character signal output : External interrupt request signal input : Operation mode select : No connection : Port 0A : Port 0B : Port 0C : Port 0D : Port 1A : Port 1B P1C 0-P1C 3 P1D 0-P1D 3 P2A 0 P2B 0-P2B 3 P2C 0-P2C 3 P2D 0-P2D 2 PSC PWM 0-PWM 8 RED RLS STP SCK 0, SCK 1 SCL SDA Sl 0, Sl 1 SO 0, SO1 TMIN VCO V DD0 , V DD1 V PP V SYNC X IN , X OUT XT IN, XT OUT : Port 1C : Port 1D : Port 2A : Port 2B : Port 2C : Port 2D : Pulse swallow control output : Pulse-width modulation output : Character signal output : Clock stop release signal input : Shift clock input/output : Shift clock input/output : Serial data input/output : Serial data input : Serial data output : Event input of basic timer 1 or 2 : Local oscillation input : Positive power supply : Program voltage application : Vertical synchronizing signal input : Main clock oscillation : Watch timer oscillation OSC IN, OSC OUT : LC oscillation for IDC 7 µPD17P068 CONTENTS 1. PIN FUNCTIONS ................................................................................................................................. 9 1.1 1.2 1.3 1.4 1.5 Normal Operation Mode ........................................................................................................................... 9 PROM Programming Mode .................................................................................................................... 13 Pin Equivalent Circuits .......................................................................................................................... 14 Handling of Unused Pins ....................................................................................................................... 19 Notes on Using the CE and INTNC Pins (Only in Normal Operation Mode) ................................... 21 2. WRITE, READ, AND VERIFY OF ONE-TIME PROM (PROGRAM MEMORY) ............................ 22 2.1 2.2 2.3 Operation Modes in Program Memory Write/Read/Verify ................................................................. 23 PROM Write Procedure .......................................................................................................................... 24 PROM Read Procedure .......................................................................................................................... 25 3. 4. ELECTRICAL SPECIFICATIONS .................................................................................................... 26 PACKAGE DRAWING ...................................................................................................................... 31 APPENDIX DEVELOPMENT TOOLS .................................................................................................... 32 8 µPD17P068 1. PIN FUNCTIONS 1.1 Normal Operation Mode (1) Port pins Pin Name P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0  P0C3 P0D0 P0D1 P0D2 P0D3 P1A0  P1A3 P1B0 P1B1 P1B2 P1B3 P1C0  P1C2 P1C3 P1D0  P1D3 P2A0 P2B0  P2B3 P2C0  P2C3 P2D0 P2D1 P2D2 These pins serve as a 4-bit output port. O CMOS push-pull N-ch open-drain This pin serves as a 1-bit output port. O Middle voltage N-ch open-drain These pins serve as a 4-bit output port. O Middle voltage N-ch open-drain These pins serve as a 4-bit output port. These pins serve as a bit-selectable 3-bit input/output port. All these pins are set to input pins when power (VDD) is turned on, when clock is stopped, or when reset signal is input to the CE pin. O Middle voltage Undefined output Undefined output Undefined output PWM8 PWM4  PWM7 PWM0  PWM3 SCK1 I/O CMOS push-pull Input SO1 Sl1 Undefined output 4-bit I/O port. These pins serve as a bit-selectable 4-bit input/output port. I/O CMOS push-pull Input RLSSTP TMIN ADC5  ADC7 — — These pins serve as a 4-bit output port. O N-ch open-drain Middle voltage, high current Undefined output These pins serve as a 4-bit input port. I — Input with pulldown resistor Description 4-bit I/O port. These pins serve as a bit-selectable 4-bit input/output port. All these pins are set to input pins when power (VDD) is turned on, when clock is stopped, or when reset signal is input to the CE pin. 4-bit I/O port. These pins serve as a bit-selectable 4-bit input/output port. All these pins are set to input pins when power (VDD) is turned on, when clock is stopped, or when reset signal is input to the CE pin. These pins serve as a 4-bit output port. The output state of each pin is undefined after power (VDD) is turned on. I/O Output Type When Reset Shared by SDA N-ch open drain SCL I/O CMOS push-pull SO0 Sl0 I/O CMOS push-pull Input — l HSCNT — Input SCK0 O CMOS push-pull Undefined output ADC1/XTOUT ADC2/XTIN ADC3 ADC4 — — CKOUT 4-bit I/O port. These pins serve as 4-bitselectable 4-bit I/O port. I/O CMOS push-pull Input 9 µPD17P068 (2) Non-port pins Pin Name Description This pin outputs signals from the charge pump of the PLL frequency synthesizer. If the frequency divided from the local oscillator (VCO) frequency is higher (lower) than the reference frequency, high (low) level is output from this pin, respectively. When the two frequencies match, this pin is placed in the high-impedance state. This pin outputs pulse swallow control signal. This signal switches division ratio for the dedicated prescaler µPB595. This pin is the input of the local oscillator. The output signal coming from the local oscillator (VCO) in the tuner and divided by the dedicated prescaler µPB595 should be input to this pin, where the µPB595 is a two-module prescaler capable of frequency division up to 1 GHz. This pin is the input of the H sync signal counter. This active-high pin outputs blanking signals to delete video signals. This active-high pin outputs character data that correspond the R signal (one of the RGB signals of IDC). This active-high pin outputs character data that correspond the G signal (one of the RGB signals of IDC). This active-high pin outputs character data that correspond the B signal (one of the RGB signals of IDC). This pin outputs character data that correspond the I signal of IDC. The H sync signals for IDC should be input to this pin in an active-low manner. The V sync signals for IDC should be input to this pin in an active-low manner. These are the input and output pins of the LC oscillation circuit for IDC. Adjust the oscillation frequency to 10 MHz. These are the analog input pins of the 6-bit resolution A/D converter. I/O Output Type When Reset Shared by EO O CMOS 3-state High-impedance — PSC O CMOS push-pull Output — VCO I — Internally pulled down — HSCNT I — Input P0B3 BLANK O CMOS push-pull Low level output — RED O CMOS push-pull Low level output — GREEN O CMOS push-pull Low level output — BLUE O CMOS push-pull Low level output — I O CMOS push-pull Input P0B2 HSYNC I — Input — VSYNC OSC IN OSC OUT ADC 0 ADC 1 ADC 2 ADC 3 ADC 4 ADC 5  ADC 7 I — Input — — — — — — I — Input P0D0/XT OUT P0D 1/XT IN P0D 2 These are the analog input pins of the 6-bit resolution A/D converter. I — Input P0D 3 P1C 0  P1C 2 10 µPD17P068 Pin Name PWM0  PWM3 PWM4  PWM7 PWM8 TMIN XTIN XTOUT CKOUT This pin is the input of basic timer 1 or 2. A 32.768-kHz crystal resonator for watch timer operation should be connected to these pins. This pin outputs the signal to control the watch timer. SCK0 These pins input and output shift clocks. SCK1 Sl0 These pins input serial data. Sl1 SO0 These pins output serial data. SO1 SCL SDA These pins input and output shift clocks. These pins input and output serial data. This pin inputs interrupt request signal from external device. An interrupt request is issued at the rising or falling edge of the input signal applied to this pin. This pin inputs interrupt request signal with noise canceller. Using this pin to input signals with noise such as commands from a remote control unit simplifies programming processes. The interrupt request issuing timing is programmable to either rising or falling edge of the input signal to this pin. I/O I/O N-ch open-drain N-ch open-drain Input Input O CMOS push-pull Input P2D1 P0A1 P0A0 I — Input P2D2 P0A3 I/O CMOS push-pull Input P2D0 P0B0 P0A2 I — Input These are the output pins of the 8-bit resolution D/A converter. O N-ch open-drain Middle-voltage Low-level output or high impedance Description I/O Output Type When Reset Shared by P2C0  P2C3 P2B0  P2B3 P2A0 P1B3 P0D1/ADC2 — — — P0D0/ADC1 O CMOS push-pull Input P1B1 INT0 I — Input — INTNC I — Input — 11 µPD17P068 Pin Name Description This pin selects a device to be activated, or resets this device. (1) Use as input of device selection signal When CE=high, PLL synthesizer and IDC operate. When CE=low, their operation are disabled (stops). (2) Use as reset input When CE changes from low to high, this device is reset in synchronization with the carry FF operation for the internal basic interval timer 0. This pin inputs the clock stop release signal. XIN XOUT An 8-MHz crystal resonator for main clock generation should be connected to these pins. These pins supply positive power voltage for this device. The power supply voltage of 5 V ± 10 % should be applied to these pins when all functions operate. When IDC is disabled, the voltage range from 4.0 to 5.5 V is allowed. When clock is stopped, the applied voltage to these pins may be lowered down to 2.5 V. Because this device internally has the power-on reset circuit, the voltages applied to these pins are changed from 0 to 4.0 V, system reset sequence is started and the program is implemented from address 0H. To assure normal operations of the power-on reset circuit, the rise time from 0 to 4.0 V should be shorter than 500 ms. These pins supply the ground level for this device. This pin should be left unconnected. — — — — I/O Output Type When Reset Shared by CE I — Input — RLSSTP I — Input P1B2 VDD0 — — — — VDD1 GND0  GND2 NC — — — — — — — — 12 µPD17P068 1.2 PROM Programming Mode Pin Name D0  D7 MD0  MD3 CLK Description 8-bit data input/output pins used in program memory write, read, verify modes. Input pins that select an operation mode in program memory write, read, verify modes. Clock input for address update in program memory write, read, verify modes. Programming voltage (+12.5 V) application pin in program memory write, read, verify modes. Positive power supply. +5 V should be applied to these pins in program memory write, read, verify modes. I/O Output Type I/O CMOS push-pull I — I — VPP — — VDD0 VDD1 GND0  GND2 — — Ground pin — — Remark The other pins are not used in the PROM programming mode. How to handle the other pins are described in the section " PIN CONFIGURATION (2) PROM programming mode" . 13 µPD17P068 1.3 Pin Equivalent Circuits (1) P0A (P0A 3/SO 0, P0A 2/SCK 0) P0B (P0B 2/l, P0B 1, P0B 0/Sl 0) P1B (P1B 2/RLS STP , P1B 1/CKOUT, P1B0) P1C (P1C 3, P1C 2/ADC 7, P1C 1/ADC6, P1C 0/ADC5) (Input/output) A/D converter (P1C/ADC only) VDD RESET (other than P1C) Read instruction (P1C only) VDD (2) P2D (P2D 2/Sl 1, P2D 1/SO1, P2D 0/SCK 1) : (Input/output) VDD RESET VDD 14 µPD17P068 (3) P0A (P0A 1/SCL, P0A 0/SDA) : (Input/output) VDD (4) P0C (P0C 3, P0C 2, P0C 1, P0C 0) P1D (P1D 3, P1D 2, P1D 1, P1D 0) RED, GREEN, BLUE, BLANK PSC VDD (Output) (5) P1A (P1A 3, P1A 2, P1A 1, P1A 0) P2A (P2A 0/PWM 8) P2B (P2B 3/PWM 7, P2B 2/PWM 6, P2B 1/PWM 5, P2B 0/PWM 4) P2C (P2C 3/PWM 3, P2C 2/PWM 2, P2C 1/PWM 1, P2C 0/PWM 0) (Output) (6) P0D (P0D 3/ADC 4, P0D 2/ADC 3, P0D 1/ADC 2/XT IN, P0D 0/ADC 1/XT OUT) : (Input) VDD High on-resistance 15 µPD17P068 (7) ADC 0 : ( Input) VDD (8) P0B 3/HSCNT : (Input/output) VDD RESET VDD Port VDD H sync signal counter VDD 16 µPD17P068 (9) P1B 3/TMIN : (Input/output) VDD RESET VDD Port VDD Timer counter VDD (10) HSYNC , V SYNC , CE, INT 0, INT NC : ( Schmitt triggered input) VDD 17 µPD17P068 (11) X IN, OSC IN : X OUT, OSC OUT : High on-resistance VDD VDD XIN, OSCIN XOUT, OSCOUT (12) EO : (Output) VDD (13) VCO : (Input) VDD VDD (Input) 18 µPD17P068 1.4 Handling of Unused Pins The following are recommended for handling unused pins. Table 1-1. Handling of Unused Pins (1/2) (a) Port pins Pin Name P0A0/SDA P0A1/SCL P0A2/SCK0 P0A3/SO0 P0B0/SI0 P0B1 P0B2/I P0B3/HSCNT P0C0-P0C3 P0D0/ADC1/XTOUT P0D1/ADC2/XTIN P0D2/ADC3, P0D3/ADC4 P1A0-P1A3 P1B0 P1B1/CKOUT P1B2/RLSSTP P1B3/TMIN P1C0/ADC5-P1C2/ADC7 P1C3 P1D0-P1D3 P2A0/PWM8 P2B0/PWM4-P2B3/PWM7 P2C0/PWM0-P2C3/PWM3 P2D0/SCK1 P2D1/SO1 P2D2/SI1 Input/output Note 1 Specify a general-purpose input port by software and connect each pin to VDD or GND through a resistor. Note 2 CMOS push-pull output N-ch open-drain output Open Specify low-level output by software, then open. N-ch open-drain output Input/output Note 1 Input/Output Circuit Type Input/output Note 1 Recommended Handling when in Unused State Specify a general-purpose input port by software and connect each pin to VDD or GND through a resistor. Note 2 CMOS push-pull output Input Open Individually connect to GND through a resistor. Note 2 Specify low-level output by software, then open. Specify a general-purpose input port by software and connect each pin to VDD or GND through a resistor. Note 2 Notes 1. Input ports go to input mode when the power supply rises, when the clock stops, and on CE reset. 2. Be careful of the fact that when an external pull-up (connection to VDD through a resistor) or pull-down (connection GND through a resistor) is made, if the pull-up or pull-down is done through a resistor with a high value, because the pin comes near to being in high impedance, the consumed (through) current increases. This also depends on the application circuit, but a typical value for a pull-up or pull-down resistor is a few tens of kΩ. 19 µPD17P068 Table 1-1. Handling of Unused Pins (2/2) (b) Pins other than ports Pin Name ADC0 BLANK BLUE CE EO GREEN HSYNC INT0 INTNC OSCIN OSCOUT PSC RED VCO VSYNC Input/Output Circuit Type Input Output Output Input Output Output Input Input Input Input Output Output Output Input with pull-down resistor Input Recommended Handling when in Unused State Connect to VDD or GND through a resistor. Note Open Open Connect to VDD through a resistor. Note Open Open Connect to VDD or GND through a resistor. Note Connect to VDD or GND through a resistor. Note Connect to VDD or GND through a resistor. Note Connect to VDD through a resistor. Note Open Open Open Open Connect to VDD or GND through a resistor. Note Note Be careful of the fact that when an external pull-up (connection to VDD through a resistor) or pull-down (connection GND through a resistor) is made, if the pull-up or pull-down is done through a resistor with a high value, because the pin comes near to being in high impedance, the consumed (through) current increases. This also depends on the application circuit, but a typical value for a pull-up or pull-down resistor is a few tens of kΩ. 20 µPD17P068 1.5 Notes on Using the CE and INTNC Pins (Only in Normal Operation Mode) In addition to the functions shown in 1.1 N ormal Operation Mode, the CE pin also has the function of setting a test mode (for IC testing) in which the internal operations of the µ PD17P068 are tested. Also, the INT NC p in has the function of the VPP p in for program memory write/verify. When a voltage higher than VDD i s applied to either of these pins, the test or program memory write/verify mode is set. This means that, even during normal operation, the µ PD17P068 may be set in the test mode if noise exceeding VDD i s applied. For example, if the wiring length of the CE or INT NC p in is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low V F b etween V DD and CE/INT NC p in VDD • Connect capacitor between V DD and CE/INTNC p in VDD Diode with low VF CE, INTNC VDD CE, INTNC VDD 21 µPD17P068 2. WRITE, READ, AND VERIFY OF ONE-TIME PROM (PROGRAM MEMORY) T he program memory contained in the µ PD17P068 is the 12160 × 1 6-bit one-time PROM that can electrically be written one time only. This PROM is accessed in 16 bits per word in normal operation mode, and in 8 bits per word in write, read, verify modes. The 16 bits of a word in normal mode are divided into higher 8 bits and lower 8 bits which are assigned to even and odd addresses, respectively. When the PROM is written, read, or verified, set this device into the PROM mode. In this mode, these pins are used as shown in the table below. Notice that no address input pins are provided. Addresses are automatically updated by the clock signal supplied from the CLK pin. Table 2-1. Pins Used in Program Memory Write, Read, and Verify Modes Pin VPP CLK MD0-MD3 D0-D7 VDD0, VDD1 Function Programming voltage (+12.5 V) application Address update clock input Operation mode selection 8-bit data input/output Power supply voltage (+5 V) application To write the internal PROM, use the NEC-specified PROM programming equipment (PROM programmer) and program adapter as listed below. PROM programmer AF-9703 AF-9704 AF-9705 AF-9706 Program adapter Remark AF-9808L (Ando Electric Corporation) (Ando Electric Corporation) (Ando Electric Corporation) (Ando Electric Corporation) (Ando Electric Corporation) For details on these PROM programmer and program adapter, consult with Ando Electric Corporation (03-3733-1151 Tokyo, Japan). 22 µPD17P068 2.1 Operation Modes in Program Memory Write/Read/Verify When +5 V is applied to the V DD p in and +12.5 V is applied to the V PP p in, this device enters the program memory write/read/verify modes. Operation mode is determined by the setting of MD0 t o MD 3 p ins as indicated in the table below. All input pins irrelevant to the program memory write/read/verify operation should be left unconnected or connected to GND via a pull-down resistor of 470 Ω ( Refer to the section "PIN CONFIGURATION (2) PROM programming mode). " Table 2-2. Operation Modes in Program Memory Write/Read/Verify Pin States Operation Mode VPP VDD MD0 H +12.5 V +5 V L L H MD1 L H L X MD2 H H H H MD3 L H H H Program memory address 0 clear Write Read, Verify Program inhibit Remark X : L or H 23 µPD17P068 2.2 PROM Write Procedure Data can be written to the PROM in high speeds by using the following procedures. (1) (2) (3) (4) (5) (6) (7) (8) (9) Set the pins not used for programming as indicated in section " PIN CONFIGURATION (2) PROM programming mode." S et the CLK pin to low level. Supply +5 V to the V DD a nd V PP p ins. Provide a 10- µ s wait state. Program memory address 0 clear mode is entered. Supply +6 V to the V DD p in, and +12.5 V to the V PP p in. Program inhibit mode is entered. Provide write data for 1 ms in write mode. Program inhibit mode is entered. Use the verify mode to test data. If the data has been written, proceed to (10). If not, repeat steps (7) to (9). (10) Provide write data (for additional writing) for 1 ms times the number of repeats performed between steps (7) to (9). (11) Program inhibit mode is entered. (12) Provide four pulses to the CLK pin to increment the address. (13) Repeat steps (7) to (12) until the last address is reached. (14) Program memory address 0 clear mode. (15) Supply +5 V to VDD a nd V PP p ins. (16) Turn off the power for this device. The procedures from (2) to (12) are illustrated in the chart below. Repeat X times                    Write Verify Additional write Address increment VPP VPP VDD GND VDD + 1 VDD VDD GND CLK Hi-Z D0-D7 Data input Hi-Z Data output Hi-Z Data input Hi-Z MD 0 MD 1 MD 2 MD 3 24 µPD17P068 2.3 PROM Read Procedure Data can be read from the PROM by using the following procedures. (1) (2) (3) (4) (5) (6) (7) Set the pins not used for programming as indicated in section " PIN CONFIGURATION (2) PROM programming mode." S et the CLK pin to low level. Supply +5 V to the V DD a nd V PP p ins. Provide a 10- µ s wait state. Program memory address 0 clear mode is entered. Supply +6 V to the V DD p in, and +12.5 V to the VPP p in. Program inhibit mode is entered. Use the verify mode to output data. Provide clock pulses to the CLK pin to output the data of an address. The address is automatically incremented every four clock pulses. Repeat the four-pulse cycles until the last address is reached. (8) (9) Program inhibit mode is entered. Program memory address 0 clear mode. (10) Supply +5 V to the V DD a nd V PP p ins. (11) Turn off the power for this device. The procedures from (2) to (9) are illustrated in the chart below. VPP VPP VDD GND VDD +1 VDD VDD GND CLK Hi-Z D0-D7 Data output Data output Hi-Z MD 0 MD 1 "L" MD 2 MD 3 25 µPD17P068 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 2 5 ˚C) Parameter Supply voltage Input voltage Output voltage High-level output current Low-level output current Symbol VDD VI VO IOH IOL1 IOL2 Output withstand voltage Storage temperature VBDS Tstg Except for P1A, P2B, P2C 1 pin All pins 1 pin (except for P1A) All pins (except for P1A) 1 pin (P1A only) All pins (P1A only) P1A, P2A, P2B, P2C Conditions Ratings −0.3 to +6.0 −0.3 to VDD + 0.3 −0.3 to VDD + 0.3 −12 −20 12 20 17 60 13 −55 to +125 Unit V V V mA mA mA mA mA mA V ˚C Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (T A = 2 5 ˚C) Parameter Supply voltage Symbol VDD1 VDD2 VDD3 Conditions MIN. 4.5 TYP. 5.0 5.0 5.0 MAX. 5.5 5.5 5.5 5.5 12.5 500 5.5 Unit V V V V V ms V P −P Only CPU operates Only watchdog timer operates (CPU stops) Clock stops P1A, P2A, P2B, P2C VDD = 0 → 4.5 V VCO 4.0 2.3 2.3 3 0.7 Data retention voltage Output withstand voltage Supply voltage rise time Input amplitude VDDR VBDS trise VIN 26 µPD17P068 DC Characteristics (Reference characteristics: T A = − 40 to +85 ˚C, V Parameter Supply current Symbol IDD1 Conditions Operation of all functions VDD = 5 V, TA = 25 ˚C, f VCO = 20 MHz VIN = 0.7 VP-P, IDC operation OSCIN = 10 MHz, XIN pin square wave input (fIN = 8 MHz, VIN = VDD) IDD2 CPU and PLL operation VDD = 5 V, TA = 25 ˚C, f VCO = 20 MHz VIN = 0.7 VP-P, XIN pin square wave input (fIN = 8 MHz, VIN = VDD) IDD3 Only CPU operates VDD = 5 V, TA = 25 ˚C, X IN pin square wave input (fIN = 8 MHz, VIN = VDD) IDD4 HALT instruction VDD = 5 V, TA = 25 ˚C, X IN pin square wave input (fIN = 8 MHz, VIN = VDD) Data retention current IDDR1 Main clock stop, watch timer operation VDD = 2.5 V, TA = 25 ˚C Main clock stop, watch timer operation VDD = 5 V, TA = 25 ˚C IDDR2 High-level input voltage VIH1 VIH2 VIH3 Low-level input voltage High-level output current VIL1 VIL2 IOH1 Main clock stop, watch timer operation VDD = 5 V, TA = 25 ˚C P0A, P0B, P1B, P1C, P2D CE, INT0, INTNC, VSYNC, HSYNC P0D P0A, P0B, P0D, P1B, P1C, P2D CE, INT0, INTNC, VSYNC, HSYNC P0A2, P0A3, P0B, P0C, P1B, P1C, P1D, P2D, BLANK, RED, GREEN, BLUE, PSC VOH = VDD − 1 V IOH2 Low-level output current IOL1 IOL11 IOL2 IOL3 IOL4 IOL5 High-level input current High-level output leakage Output off leakage current Internal pull-down resistor IIH ILOH IL RPD1 RPD2 RPD3 EO PSC BLANK, RED, GREEN, BLUE EO P0A0, P0A1 PWM (P2A, P2B, P2C) P1A VCO P1A, P2A, P2B, P2C EO P0D (KEY) P0D (KEY) P0D (KEY) VOH = VDD − 1 V VOL = 1 V VOL = 1 V VOL = 1 V VOL = 1 V VOL = 1 V VOL = 1 V VIH = VDD VO = 12.5 V VO = VDD or 0 V VIH = VDD VIH = VDD = 5 V VIH = VDD = 5 V, TA = 25 ˚C 19 23 29 ± 10−3 41 41 41 1 1 1 1 15 0.1 8.5 6 4.0 1.5 30 0.65 1.3 0.5 ±1 85 72 47 mA mA mA mA mA mA −1 1 −2.5 10 mA mA P0A2, P0A3, P0B, P0C, P1B, P1C, P1D, P2D, −1 −5 0.7VDD 0.8VDD 0.7VDD 0.2 VDD 0.2 VDD V V V V V mA 2 15 15 25 5 10 2.5 4.5 mA 6.5 9 mA 7 12 mA DD = 5 V ± 1 0 %) MIN. TYP. 11 MAX. 23 Unit mA µA µA µA µA µA kΩ kΩ kΩ 27 µPD17P068 AC Characteristics (Reference characteristics: T A = − 40 to +85 ˚C, V Parameter Input frequency 1 Input frequency 2 Input frequency 3 Symbol fVCO fTMR fHS TMIN (P1B3) HSCNT (P0B3) Conditions VCO square wave input VIN = 0.7 VP−P Duty 50 % DD = 5 V ± 1 0 %) MIN. 0.7 45 10 TYP. MAX. 20 65 20 Unit MHz Hz kHz A/D Converter Characteristics (Reference characteristics: TA = − 10 to +50 ˚C, V Parameter A/D conversion absolute accuracy A/D conversion resolution A/D input impedance Symbol ADC0-ADC7 ADC0-ADC7 ADC0-ADC7 1 Conditions MIN. DD = 5 V ± 1 0 %) MAX. ± 1.5 6 Unit LSB bit MΩ TYP. ±1 DC Programming Characteristics (TA = 2 5 ˚C, V Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current Symbol VIH1 VIH2 VIL1 VIL2 ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Except for CLK CLK Except for CLK CLK VIN = VIL or VIH IOH = −1 mA IOL = 1 mA DD = 6 .0 ± 0 .25 V, V PP = 1 2.5 ± 0 .5 V) MIN. 0.7 VDD VDD − 0.5 0 0 VDD − 1.0 1.0 30 30 TYP. MAX. VDD VDD 0.3 VDD 0.4 ±10 Unit V V V V Conditions µA V V mA mA Cautions 1. VPP must not exceed +13.5 V including overshoot. 2. VDD should be applied before VPP and cut after VPP. 28 µPD17P068 AC Programming Characteristics (TA = 2 5 ˚C, V Parameter Address setup time Note (vs. MD0↓) MD1 setup time (vs. MD0↓) Data setup time (vs. MD0↓) Address hold time Note (vs. MD0↑) Data hold time (vs. MD0↑) MD0↑→ data output float delay time VPP setup time (vs. MD3↑) VDD setup time (vs. MD3↑) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD1↑) MD0↓→ data output delay time MD1 hold time (vs. MD0↑) MD1 recovery time (vs. MD0↓) Program counter reset time CLK input high-/low-level width CLK input frequency Initial mode setting time MD3 setup time (vs. MD1↑) MD3 hold time (vs. MD1↓) MD3 setup time (vs. MD0↓) Address data output delay time Address Note → data output hold time MD3 hold time (vs. MD0↑) MD3↓→ data output float delay time Note → DD = 6 .0 ± 2 .5 V, V PP = 1 2.5 ± 0 .5 V) Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 1.0 1.05 21.0 1 2 2 10 0.125 4.19 2 2 2 130 TYP. MAX. Unit Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR µs µs µs µs µs ns µs µs ms ms µs µs µs µs µs µs MHz MD0 = MD1 = VIL tM1H + tM1R ≥ 50 µs µs µs µs µs 2 When program memory is read 2 0 2 2 130 µs ns µs µs Note The internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks comprise one cycle. The internal clock is not connected to a pin. 29 µPD17P068 Program Memory Write Timing VPP VPP VDD tVPS tVDS GND VDD + 1 VDD VDD GND CLK Hi-Z tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM1S tM1H tM1R tM0S tOPW Hi-Z Data output tDV tDF Hi-Z tXH tXL Data input tDS tDH tAH D0-D7 Data input tDS tDH Hi-Z tAS Data input Hi-Z tM3H Program Memory Read Timing tVPS VPP VPP VDD GND VDD + 1 VDD GND CLK tXL Hi-Z D0-D7 tI MD0 tDV Data output tDAD tHAD Data output tM3HR Hi-Z tDFR tXH tVDS VDD MD1 "L" tPCR MD2 tM3SR MD3 30 µPD17P068 4. PACKAGE DRAWING 100 PIN PLASTIC QFP (14 20) A B 80 81 51 50 detail of lead end CD S Q R 100 1 31 30 F G P H I M J K M N L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.2±0.2 20.0±0.2 14.0±0.2 17.2±0.2 0.8 0.6 0.30±0.10 0.15 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 –0.05 0.10 2.7 0.125±0.075 5 ° ±5 ° 3.0 MAX. INCHES 0.913 +0.009 –0.008 0.787 +0.009 –0.008 0.551 +0.009 –0.008 0.677±0.008 0.031 0.024 0.012 +0.004 –0.005 0.006 0.026 (T.P.) 0.063±0.008 0.031 +0.009 –0.008 0.006 +0.004 –0.003 0.004 0.106 0.005±0.003 5 ° ±5 ° 0.119 MAX. S100GF-65-3BA-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 31 µPD17P068 APPENDIX DEVELOPMENT TOOLS The following tools are available to provide µ PD17P068’s program development environment. Hardware Product Description The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators common to the 17K series. The IE-17K and IE-17K-ET should be connected with the host computer (PC-9800 series or IBM PC/ATTM ) through an RS-232-C cable. The EMU-17K should be installed to an extension slot in the host computer (PC-9800 series). Each of the three products function as a dedicated emulator Note 2 In-circuit emulator IE-17K IE-17K-ET Note 1 EMU-17K for each device by connecting it with an individual system evaluation board (SE board). Using SIMPLEHOST ® which features an excellent user-machine interface, makes user’s debugging environment more powerful. If the EMU17K is used, user can monitor the contents of the data memory in real time. This SE board is for the µPD17068, 17P068, and 17008. This board can perform evaluations of user’s system. To debug user’s programs, use it together with an in-circuit emulator. This probe is used when emulating the µPD17P068GF. SE board (SE-17008) Emulation probe (EP-17068GF) Conversion socket (EV-9200GF-100 Note 3 ) PROM programmer AF-9703 Note 4 AF-9704 Note 4 AF-9705 Note 4 AF-9706 Note 4 Program adapter (AF-9808L Note 4 ) This socket converts pin arrangement for the 100-pin plastic QFP (14 × 20 mm) to connect the emulation probe EP-17068GF to the target system. These products write programs to the internal PROM of the µPD17P068. To perform programming, the program adapter AF-9808L is required to connect to the PROM programmer. This adapter is used together with the PROM programmer to program the PROM in the µPD17P068. Notes 1. Inexpensive type: Power supply is required to connect externally. 2. Manufactured by IC Corporation. For details, call 03-3447-3793 Tokyo, Japan. 3. If the EP-17068GF is purchased, one EV-9200GF-100 is attached as a companion product. EV-9200GF100s can separately be purchased in 5-piece units. 4. Manufactured by Ando Electric Corporation. For details, call 03-3733-1151 Tokyo, Japan. 32 µPD17P068 Software Product Description This assembler can be used 17K series assembler (AS17K) for all 17K series devices. To develop program of the PC-9800 Series MS-DOSTM Host Computer OS Media 5 inch 2HD 3.5 inch 2HD 5 inch 2HC IBM PC/AT DOSTM PC 3.5 inch 2HC 5 inch 2HD PC-9800 series MS-DOS Ordering Code µS5A10AS17K µS5A13AS17K µS7B10AS17K µS7B13AS17K µS5A10AS17068 µPD17P068, the device file (AS17068) are also required. This product is the device file for the µPD17P068. This device file is used together with the assembler AS17K. Device file (AS17068) 3.5 inch 2HD µS5A13AS17068 5 inch 2HC µS7B10AS17068 IBM PC/AT PC DOS 3.5 inch 2HC µS7B13AS17068 5 inch 2HD This software is used to develop programs using an in-circuit emulator and the Support software (SIMPLEHOST) host computer. This product runs under WindowsTM system and provides users with an excellent user-machine interface. IBM PC/AT PC DOS Windows PC-9800 Series MS-DOS µS5A10lE17K µS5A13lE17K µS7B10lE17K µS7B13lE17K 3.5 inch 2HD 5 inch 2HC 3.5 inch 2HC Remark T hese products run with the versions of the operation systems shown below. OS MS-DOS PC DOS Windows Version Ver.3.30 to Ver.5.00A Note Ver.3.1 to Ver.5.0 Note Ver.3.0 to Ver.3.1 Note With these products, the task swap function is disabled though the Ver.5.00/5.00A of MS-DOS and Ver.5.0 of the PC DOS support the task swap function. 33 µPD17P068 [MEMO] 34 µPD17P068 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 35 µPD17P068 Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SIMPLEHOST is a registered trademark of NEC Corp. MS-DOS and Windows are trademarks of Microsoft Corp. PC/AT and PC DOS are trademarks of IBM Corp. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 36