UPD17P236M2GT

DATA SHEET MOS INTEGRATED CIRCUIT µPD17P236 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROLLER The µPD17P236 is a model of the µPD17236 with a one-time PROM instead of an internal mask ROM. Since the user can write programs to the µPD17P236, it is ideal for experimental production or small-scale production of the µPD17230, 17231, 17232, 17233, 17234, 17235, or 17236 systems. When reading this document, also read the documents related to the µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236. Detailed functions are described in the following user's manual. Read this manual when designing your system. µPD172×× Series User's Manual: U12795E FEATURES • Pin compatible with µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236 (except PROM programming function) • Carrier generator circuit for infrared remote controller (REM output) • 17K architecture: General-purpose register method • Program memory (one-time PROM): 32 Kbytes (16,384 × 16) • Data memory (RAM): 223 × 4 bits • Low-voltage detection circuit • Input/output of P1A0 pin, clock selection for carrier generation µPD17P236M1 Input/output of P1A0 pin Clock (RfX) selection for carrier generation Output RfX = fX/2 µPD17P236M2 Input µPD17P236M3 Output RfX = fX µPD17P236M4 Input • Supply voltage: VDD = 2.2 to 3.6 V (fX = 4 MHz: high-speed mode, 4 µs) VDD = 3.0 to 3.6 V (fX = 8 MHz: high-speed mode, 2 µs) APPLICATIONS Preset remote controllers, toys, and portable systems The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14776EJ1V0DS00 (1st edition) Date Published June 2000 J CP(K) Printed in Japan © 2000 µPD17P236 ORDERING INFORMATION Part Number Package 28-pin plastic SOP (9.53 mm (375)) 30-pin plastic SSOP (7.62 mm (300)) 28-pin plastic SOP (9.53 mm (375)) 30-pin plastic SSOP (7.62 mm (300)) 28-pin plastic SOP (9.53 mm (375)) 30-pin plastic SSOP (7.62 mm (300)) 28-pin plastic SOP (9.53 mm (375)) 30-pin plastic SSOP (7.62 mm (300)) µPD17P236M1GT µPD17P236M1MC-5A4 µPD17P236M2GT µPD17P236M2MC-5A4 µPD17P236M3GT µPD17P236M3MC-5A4 µPD17P236M4GT µPD17P236M4MC-5A4 PIN CONFIGURATION (TOP VIEW) (1) Normal operation mode • 2 8-pin plastic SOP (9.53 mm (375)) µ PD17P236M1GT, 17P236M2GT, 17P236M3GT, 17P236M4GT P0D 2 P0D 3 INT P0E 0 P0E 1 P0E 2 P0E 3 REM V DD X OUT X IN GND RESET P1A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P0D 1 P0D 0 P0C 3 P0C 2 P0C 1 P0C 0 P0B 3 P0B 2 P0B 1 P0B 0 P0A 3 P0A 2 P0A 1 P0A 0 2 Data Sheet U14776EJ1V0DS00 µPD17P236 • 3 0-pin plastic SSOP (7.62 mm (300)) µ PD17P236M1MC-5A4, 17P236M2MC-5A4, 17P236M3MC-5A4, 17P236M4MC-5A4 P0D2 P0D3 INT P0E0 P0E1 P0E2 P0E3 REM VDD XOUT XIN GND RESET P1A0 IC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IC2 P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0 GND IC1, IC2 INT : Ground : Internally connectedNote 1 : External interrupt request signal input P0A0-P0A3 : Input port (CMOS input) P0B0-P0B3 : Input/output port (CMOS input/N-ch open-drain output) P0C0-P0C3 : Input/output port (CMOS input/N-ch open-drain output) P0D0-P0D3 : Input/output port (CMOS input/N-ch open-drain output) P0E0-P0E3 : Input/output port (CMOS push-pull output) P1A0 REM RESET VDD XIN, XOUT : Input port (CMOS input) or output port (N-ch open-drain output) : Remote controller output (CMOS push-pull output) : Reset input : Power supply : Resonator connection Note 2 Notes 1. This pin cannot be used. Leave open. 2. Input port or output port is selected depending on the product (see 2. FUNCTIONS). PIN Data Sheet U14776EJ1V0DS00 3 µPD17P236 (2) PROM programming mode • 2 8-pin plastic SOP (9.53 mm (375)) µ PD17P236M1GT, 17P236M2GT, 17P236M3GT, 17P236M4GT D2 D3 VPP 1 2 3 4 5 28 27 26 25 24 23 22 21 20 19 18 17 D1 D0 D7 D6 D5 D4 MD3 MD2 MD1 MD0 (L) 6 7 (Open) VDD (Open) CLK GND (L) (Open) 8 9 10 11 12 13 14 (L) 16 15 4 Data Sheet U14776EJ1V0DS00 µPD17P236 • 3 0-pin plastic SSOP (7.62 mm (300)) µ PD17P236M1MC-5A4, 17P236M2MC-5A4, 17P236M3MC-5A4, 17P236M4MC-5A4 D2 D3 VPP 1 2 3 4 5 30 29 28 27 26 25 24 23 22 21 20 19 18 (Open) D1 D0 D7 D6 D5 D4 MD3 MD2 MD1 MD0 (L) 6 7 (Open) VDD (Open) CLK GND (L) (Open) (Open) 8 9 10 11 12 13 14 15 (L) 17 16 Caution Contents in parentheses indicate how to handle unused pins in PROM programming mode. L : Connect to GND via a resistor (470 Ω) separately. Open : Leave unconnected. CLK D0-D7 GND MD0-MD3 VDD VPP : Clock input for PROM : Data input/output for PROM : Ground : Mode select input for PROM : Power supply : Power supply for PROM writing Data Sheet U14776EJ1V0DS00 5 µPD17P236 BLOCK DIAGRAM P0A0 P0A1 P0A2 P0A3 P0A RF RAM 223 × 4 bits Remote Control Divider REM 8-bit timer P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3) P0B SYSTEM REG. Interrupt Controller ALU INT (VPP) P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7) Reset Controller P0C RESET One Time PROM 16,384 × 16 bits P0D0 (D0) P0D1 (D1) P0D2 (D2) P0D3 (D3) P0D Instruction Decoder Program Counter P0E0 P0E1 P0E2 P0E3 Power Supply Circuit CPU Clock VDD GND P0E Stack (5 levels) P1A0 Note Basic Interval/ Watchdog Timer P1A XIN (CLK) OSC XOUT Note Remark Input port or output port is selected depending on the product (see 2. PIN FUNCTIONS). ( ): During PROM programming mode 6 Data Sheet U14776EJ1V0DS00 µPD17P236 CONTENTS 1. DIFFERENCES BETWEEN µPD17236 AND µPD17P236 ........................................................... 8 2. PIN FUNCTIONS ........................................................................................................................... 2.1 2.2 2.3 2.4 2.5 Normal Operation Mode .................................................................................................................... PROM Programming Mode ............................................................................................................... Input/Output Circuits ......................................................................................................................... Processing of Unused Pins .............................................................................................................. Notes on Using the RESET and INT Pins ........................................................................................ 9 9 10 11 12 12 3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................... 3.1 3.2 3.3 Operating Mode When Writing/Verifying Program Memory .......................................................... Program Memory Writing Procedure ............................................................................................... Program Memory Reading Procedure ............................................................................................. 13 13 14 15 4. ELECTRICAL SPECIFICATIONS ................................................................................................. 16 5. PACKAGE DRAWING .................................................................................................................. 23 6. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 25 APPENDIX. DEVELOPMENT TOOLS ................................................................................................ 27 Data Sheet U14776EJ1V0DS00 7 µPD17P236 1. DIFFERENCES BETWEEN µPD17236 AND µPD17P236 µPD17P236 is equipped with PROM to which data can be written by the user instead of the internal mask ROM (program memory) of the µPD17236. Table 1-1 shows the differences between the µPD17236 and µPD17P236. The CPU functions and internal hardware of the µPD17P236, 17230, 17231, 17232, 17233, 17234, 17235, and 17236 are identical. Therefore, the µPD17P236 can be used to evaluate the program developed for the µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236 system. Note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the µPD17P236 are different from those of the µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236. Table 1-1. Differences among µPD17236 and µPD17P236 Product Name Item Program memory µPD17P236 µPD17P236M1, 17P236M2, 17P236M3, 17P236M4 One-time PROM 32 Kbytes (16,384 × 16) (0000H-3FFFH) Mask ROM µPD17236 Data memory Input/output of P1A0 pin 223 × 4 bits • Input (µPD17P236M2, 17P236M4) • Output (µPD17P236M1, 17P236M3) • RfX = fX/2 (µPD17P236M1, 17P236M2) • RfX = fX (µPD17P236M3, 17P236M4) Provided • 2 µs (VDD = 3.0 to 3.6 V) • 4 µs (VDD = 2.2 to 3.6 V) VDD = 2.2 to 3.6 V • 28-pin plastic SOP (9.53 mm (375)) • 30-pin plastic SSOP (7.62 mm (300)) Any (mask option) Clock (RfX ) selection for carrier generation Low-voltage detection circuitNote Instruction execution time Any (mask option) Any (mask option) • 2 µs (VDD = 2.2 to 3.6 V) • 4 µs (VDD = 2.0 to 3.6 V) VDD = 2.0 to 3.6 V Supply voltage Package Note Although the circuit configuration is identical, its electrical characteristics differ depending on the product. 8 Data Sheet U14776EJ1V0DS00 µPD17P236 2. PIN FUNCTIONS 2.1 Normal Operation Mode (1/2) Pin No. 27 28 1 2 (28) (29) (1) (2) Symbol P0D0 P0D1 P0D2 P0D3 Function These pins constitute a 4-bit I/O port which can be set in the input or output mode in 4-bit units (group I/O). In the input mode, these pins serve as CMOS input pins with a pull-up resistor, and can be used as key return input lines of a key matrix. The standby status must be released when at least one of the input lines goes low. In the output mode, these pins are used as N-ch open-drain output pins and can be used as the output lines of a key matrix. External interrupt request signal. This signal releases the standby status if an external interrupt request signal is input to it when the INT pin interrupt enable flag (IP) is set. These pins constitute a 4-bit I/O port that can be set in the input or output mode in 1-bit units. In the output mode, this port functions as a high current CMOS output port. In the input mode, function as CMOS input and can be specified to connect pull-up resistor by program. Outputs transfer signal for infrared remote controller. Active-high output. 9 (9) 10 (10) 11 (11) 12 (12) 13 (13) VDD XOUT XIN GND RESET Power supply Connects ceramic resonator for system clock oscillation Output Format N-ch open-drain At Reset Low-level output 3 (3) INT – Input 4 5 6 7 (4) (5) (6) (7) P0E0 P0E1 P0E2 P0E3 CMOS push-pull Input 8 (8) REM CMOS push-pull – – Low-level output – (Oscillation stops) – Input Ground Turns ON pull down resistor if POC or watchdog timer overflows and if the stack pointer overflows or underflows, and resets the system. Usually, the pull-down resistor is ON. – – 14 (14) P1A0 µPD17P136M1, µPD17P136M3 µPD17P136M2, µPD17P136M4 This pin is 1-bit output port (N-ch open-drain output) and can be used as the output lines of a key matrix. This pin is 1-bit input port (CMOS input). However, it cannot release the STOP mode. N-ch open-drain Highimpedance output Input Input – – 15 16 17 18 19 20 21 22 (16) (17) (18) (19) (20) (21) (22) (23) P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 These pins are CMOS input pins with a 4-bit pull-up resistor. They can be used as the key return input lines of a key matrix. If any one of these pins goes low, the standby status is released. These pins constitute a 4-bit I/O port that can be set in the input or output mode in 1-bit units. In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used as the key return input lines of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used as the output lines of a key matrix. N-ch open-drain Input Remark The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP. Data Sheet U14776EJ1V0DS00 9 µPD17P236 2.1 Normal Operation Mode (2/2) Pin No. 23 24 25 26 (24) (25) (26) (27) Symbol P0C0 P0C1 P0C2 P0C3 Function These pins constitute a 4-bit I/O port that can be set in the input or output mode in 4-bit units (group I/O). In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used as the key return input lines of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used as the output lines of a key matrix. These pins cannot be used. Leave open. Output Format N-ch open-drain At Reset Low-level output (15) (30) IC1 IC2 – – Remark The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP. 2.2 PROM Programming Mode Pin No. 3 Symbol VPP Function Power supply for PROM programming. Apply +12.5 V to this pin as the program voltage when writing/ verifying program memory. 9 VDD Power supply. Apply +6 V to this pin when writing/verifying program memory. 11 12 19 (20)  22 (23) 23 (24)  26 (27) 27 (28) 28 (29) 1 2 CLK GND MD0  MD3 D4  D7 D0 D1 D2 D3 Inputs clock for PROM programming. Ground. Input pins used to select operation mode when PROM is programmed. – – – – – Input – – Output Format – At Reset – Input/output 8-bit data for PROM programming CMOS push-pull Input Remarks 1. The other pins are not used in the PROM programming mode. How to handle the other opins are described in PIN CONFIGURATION (2) PROM programming mode. 2. The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP. 10 Data Sheet U14776EJ1V0DS00 µPD17P236 2.3 Input/Output Circuits The equivalent input/output circuit for each µPD17P236 pin is shown below. (1) P0A V DD (4) P1A • Input mode (µPD17P236M2, 17P236M4) Input buffer Input buffer • Output mode (µPD17P236M1, 17P236M3) (2) P0B, P0C, P0D VDD data Output latch N-ch P-ch (5) RESET Data Output latch VDD Output disable Selector Input buffer N-ch Reset input P-ch Input buffer (3) P0E V DD Schmitt trigger input with hysteresis characteristics N-ch (6) INT Data Pull-up register V DD Data Output latch P-ch Input buffer P-ch Output disable N-ch Schmitt trigger input with hysteresis characteristics Selector Input buffer (7) REM V DD Data P-ch Output disable Data Sheet U14776EJ1V0DS00 N-ch 11 µPD17P236 2.4 Processing of Unused Pins Process the unused pins as follows: Table 2-1. Processing of Unused Pins Pin P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 Input : Individually connect to VDD or GND via resistor. Output : Leave open. Connect to GND. Leave open. Connect to GND. These pins cannot be used. Leave open. Leave open. Recommended Connection P1A0 REM INT IC1, IC2 2.5 Notes on Using the RESET and INT Pins In addition to the functions shown in 2. PIN FUNCTIONS, the RESET pin also has the function of setting a test mode (for IC testing) in which the internal operations of the µPD17P236 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during normal operation, the µPD17P236 may be set in the test mode if noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low VF between VDD and RESET/INT pin VDD • Connect capacitor between VDD and RESET/INT pin VDD Diode with low VF RESET, INT VDD RESET, INT VDD 12 Data Sheet U14776EJ1V0DS00 µPD17P236 3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) The program memory of the µPD17P236 is a one-time PROM of 16,384 × 16 bits. To write or verify this one-time PROM, the pins shown in Table 3-1 are used. Note that no address input pin is used. Instead, the address is updated by using the clock input from the CLK pin. Table 3-1. Pins Used to Write/Verify Program Memory Pin Name VPP VDD CLK MD0-MD 3 D0-D7 Function Supplies voltage when writing/verifying program memory. Apply +12.5 V to this pin. Power supply. Supply +6 V to this pin when writing/verifying program memory. Inputs clock to update address when writing/verifying program memory. By inputting pulse four times to CLK pin, address of program memory is updated. Input to select operation mode when writing/verifying program memory. Inputs/outputs 8-bit data when writing/verifying program memory. 3.1 Operating Mode When Writing/Verifying Program Memory The µPD17P236 is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the µPD17P236 has been in the reset status (VDD = 5 V, RESET = 0 V) for a specific time. In this mode, the operating modes shown in Table 3-2 can be set by setting the MD0 through MD 3 pins. Leave all the pins other than those shown in Table 3-1 unconnected or connect them to GND via pull-down resistor (470 Ω). (See PIN CONFIGURATION (2) PROM programming mode.) Table 3-2. Setting Operation Mode Setting of Operating Mode VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L × MD2 H H H H MD3 L H H H Program memory address 0 clear mode Write mode Verify mode Program inhibit mode Operating Mode ×: don’t care (L or H) Data Sheet U14776EJ1V0DS00 13 µPD17P236 3.2 Program Memory Writing Procedure The program memory is written at high speed in the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the V DD p in. Keep the V PP p in low. Supply 5 V to the V PP p in after waiting for 10 µ s. Set the program memory address 0 clear mode by using the mode setting pins. Supply +6 V to V DD a nd +12.5 V to V PP. Set the program inhibit mode. Write data to the program memory in the 1-ms write mode. Set the program inhibit mode. Set the verify mode. If the data have been written to the program memory, proceed to (10). If not, repeat steps (7) through (9). (10) Additional writing of (number of times of writing in (7) through (9): X) × 1 m s. (11) Set the program inhibit mode. (12) Input a pulse to the CLK pin four times to update the program memory address (+1). (13) Repeat steps (7) through (12) up to the last address. (14) Set the 0 clear mode of the program memory address. (15) Change the voltages on the V DD a nd V PP p ins to 5 V. (16) Turn off power. The following figure illustrates steps (2) through (12) above. Repeated X time Reset VPP VPP VDD GND VDD VDD+1 VDD GND CLK Write Verify Additional write Address increment D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z Data input Hi-Z MD0 MD1 MD2 MD3 14 Data Sheet U14776EJ1V0DS00 µPD17P236 3.3 Program Memory Reading Procedure (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the V DD p in. Keep the V PP p in low. Supply 5 V to the V PP p in after waiting for 10 µ s. Set the program memory address 0 clear mode by using the mode setting pins. Supply +6 V to V DD a nd +12.5 V to V PP. Set the program inhibit mode. Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to the CLK pin four times. Set the program inhibit mode. Set the program memory address 0 clear mode. (10) Change the voltage on the V DD a nd V PP p ins to 5 V. (11) Turn off power. The following figure illustrates steps (2) through (9) above. Reset VPP VPP VDD GND VDD+1 VDD One cycle GND CLK VDD D0-D7 Hi-Z Data output Data output Hi-Z MD0 MD1 "L" MD2 MD3 Data Sheet U14776EJ1V0DS00 15 µPD17P236 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Item Supply voltage PROM power supply Input voltage Output voltage High-level output current Note Symbol VDD VPP VI VO IOH REM pin Conditions Ratings –0.3 to +7.0 –0.3 to +13.5 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 Peak value rms value –36.0 –24.0 –7.5 –5.0 –22.5 –15.0 7.5 5.0 22.5 15.0 30.0 20.0 –40 to +85 –65 to +150 Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA °C °C mW 1 pin (P0E pin) Peak value rms value Total of P0E pins Peak value rms value Low-level output current Note IOL 1 pin (P0B, P0C, P0D, P0E, P1A0, or REM pin) Total of P0B, P0C, P0D, P1A0, REM pins Total of P0E pins Peak value rms value Peak value rms value Peak value rms value Operating temperature Storage temperature Power dissipation TA Tstg Pd T A = 8 5° C 180 Note The rms value should be calculated as follows: [rms value] = [Peak value] × √ Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 16 Data Sheet U14776EJ1V0DS00 µPD17P236 Recommended Operating Ranges (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Item Supply voltage Symbol VDD1 fX = 1 MHz Conditions High-speed mode (Instruction execution time: 16 µs) High-speed mode (Instruction execution time: 4 µs) Ordinary mode (Instruction execution time: 4 µs) High-speed mode (Instruction execution time: 2 µs) 3.0 3.6 V MIN. 2.2 TYP. MAX. 3.6 Unit V VDD2 fX = 4 MHz VDD3 fX = 8 MHz VDD4 Oscillation frequency Operating temperature Low-voltage detector circuit Note fX TA tCY 1.0 –40 4 4.0 +25 8.0 +85 32 MHz °C µs Note Reset if the status of VDD = 2.05 V (TYP.) lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected. Some oscillators stop oscillating before the reset function is effected. fX vs VDD (MHZ) 10 9 8 7 6 5 System clock: fX (MHZ) (Normal mode) 4 3 Operation guaranteed area 2 1 0.4 0 2 2.2 3 3.6 4 Supply voltage: VDD (V) Remark The region indicated by the broken line in the above figure is the guaranteed operating range in the highspeed mode. Data Sheet U14776EJ1V0DS00 17 µPD17P236 System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Resonator Recommended Constants Item Conditions MIN. TYP. MAX. Unit Ceramic resonator X IN X OUT Oscillation frequency Note 1 (fX) 1.0 4.0 8.0 MHz Oscillation stabilization timeNote 2 After VDD reached MIN. in oscillation voltage range 4 ms Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: • Keep wiring length as short as possible. • Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. • Always keep the oscillator capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. • Do not extract signals from the oscillator. External circuit example XIN XOUT R1 C1 C2 Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 18 Data Sheet U14776EJ1V0DS00 µPD17P236 DC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Item High-level input voltage Symbol VIHI1 VIH2 VIH3 Low-level input voltage VIL1 VIL2 VIL3 High-level input leakage current Low-level input leakage current ILIH Conditions P1A0 (input), RESET, INT P0A, P0B, P0C, P0D P0E P1A0 (input), RESET, INT P0A, P0B, P0C, P0D P0E P0A, P0B, P0C, P0D, P0E, P1A0, RESET, INT INT, P1A0 P0E VIH = VDD MIN. 0.8VDD 0.7VDD 0.8VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2VDD 0.3VDD 0.35VDD 3 Unit V V V V V V µA µA µA kΩ kΩ kΩ mA ILIL1 ILIL2 VIL = 0 V VIL = 0 V w/o pull-up resistor 25 100 2.5 VOH = 1.0 V, VDD = 3 V –6 50 200 5 –13 –3 –3 Internal pull-up resistor R1 R2 P0E, RESET (pulled up) P0A, P0B, P0C, P0D RESET (pulled down) REM 100 400 10 –24 Internal pull-down resistor High-level output current R3 IOH1 High-level output voltage Low-level output voltage VOH V OL1 V OL2 P0E, REM P0B, P0C, P0D, P1A0 (output), REM P0E RESET pin pulled down, VDT = V DD IOH = –0.5 mA VDD–0.3 IOL = 0.5 mA IOL = 1.5 mA 0 0 2.05 VDD 0.3 0.3 2.2 V V V V Low-voltage detection voltage Data retention voltage Supply current V DT VDDDR IDD1 RESET = low level or STOP mode Operating mode (high-speed) VDD = 3 V ±10% fX = 1 MHz fX = 4 MHz fX = 8 MHz 1.3 0.55 1.0 1.3 0.5 0.75 0.9 0.4 0.5 0.6 2.0 TA = 25 °C 2.0 3.6 1.1 2.0 2.6 1.0 1.5 1.8 0.8 1.0 1.2 20.0 5.0 V mA mA mA mA mA mA mA mA mA IDD2 Operating mode (low-speed) VDD = 3 V ±10% fX = 1 MHz fX = 4 MHz fX = 8 MHz IDD3 HALT mode VDD = 3 V ±10% fX = 1 MHz fX = 4 MHz fX = 8 MHz IDD4 STOP mode VDD = 3 V ±10% built-in POC µA µA Data Sheet U14776EJ1V0DS00 19 µPD17P236 AC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Item CPU clock cycle time (instruction execution time) INT high/low level width RESET low level lwidth Note Symbol tCY1 tCY2 tINTH, tINTL tRSL VDD = 3.0 to 3.6 V Conditions MIN. 3.8 1.9 20 10 TYP. MAX. 33 33 Unit µs µs µs µs Note The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and SYSCK (RF: address 02H) of the register file. The figure on the right shows the CPU clock cycle time tCY vs. supply voltage VDD characteristics. 10 9 8 7 CPU clock cycle time tCY (µ s) tCY vs VDD 40 33 6 5 4 3 3.8 Operation guaranteed area 2 1.9 1 0 1 2.2 2 3 3.6 4 Supply voltage VDD (V) 20 Data Sheet U14776EJ1V0DS00 µPD17P236 DC Programming Characteristics (TA = 25°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage V IL1 V IL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = V IL, MD1 = VIH Conditions Other than CLK CLK Other than CLK CLK VIN = V IL or V IH IOH = –1 mA IOL = 1.6 mA V DD – 1.0 0.4 30 30 MIN. 0.7V DD V DD – 0.5 0 0 TYP. MAX. VDD VDD 0.3V DD 0.4 10 Unit V V V V µA V V mA mA Cautions 1. Keep VPP to within +13.5 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP. AC Programming Characteristics (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Address setup timeNote (vs. MD0↓) MD1 setup time (vs. MD 0↓) Data setup time (vs. MD0↓) Address hold timeNote (vs. MD 0↑) Data hold time (vs. MD0↑) MD0↑→ data output float delay time VPP setup time (vs. MD 3↑) VDD setup time (vs. MD 3↑) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD 1↑) MD0↓→ data output delay time MD1 hold time (vs. MD0↑) MD1 recovery time (vs. MD0↓) Program counter reset time CLK input high-, low-level width CLK input frequency Initial mode set time MD3 setup time (vs. MD1↑) MD3 hold time (vs. MD1↓) MD3 setup time (vs. MD0↓) AddressNote → data output delay time AddressNote → data output hold time MD3 hold time (vs. MD0↑) MD3↓→ data output float delay time Reset setup time Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tRES When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 TYP. MAX. Unit µs µs µs µs µs 130 ns µs µs 1.0 1.05 21.0 ms ms µs 1 MD0 = MD1 = V IL tM1H+tM1R ≥ 50 µs 2 2 10 0.125 µs µs µs µs µs 4.19 2 2 2 2 2 0 2 2 10 130 MHz µs µs µs µs µs ns µs µs µs Note The internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks compreise one cycle. The internal clock is not connected to a pin. Data Sheet U14776EJ1V0DS00 21 µPD17P236 Program Memory Write Timing tRES tVPS VPP VPP VDD GND VDD+1 VDD GND CLK Hi-Z tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tMOS tOPW tXL Data input tDS tDH Data output tDV tDF Data input tDS tDH tAH tAS Data input tVDS tXH VDD D0-D7 Program Memory Read Timing tRES tVPS VPP VPP VDD GND VDD+1 VDD GND CLK tXL tHAD D0-D7 tI MD0 tDV Data output Data output tM3HR tDFR tDAD tVDS tXH VDD MD1 "L" tPCR MD2 tM3SR MD3 22 Data Sheet U14776EJ1V0DS00 µPD17P236 5. PACKAGE DRAWING 28-PIN PLASTIC SOP (9.53 mm (375)) 28 15 detail of lead end P 1 A H G I J 14 F S C D E M M B K L N S NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 17.9 ± 0.17 0.78 MAX. 1.27 (T.P.) 0.42+ 0.08 − 0.07 0.1 ± 0.1 2.6 ± 0.2 2.50 10.3 ± 0.3 7.2 ± 0.2 1.6 ± 0.2 0.17+ 0.08 − 0.07 0.8 ± 0.2 0.12 0.15 3 °+ 7 ° −3° P28GM-50-375B-5 Data Sheet U14776EJ1V0DS00 23 µPD17P236 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 A 15 E L U H I J S C D M M N S B K NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 9.85 ± 0.15 0.45 MAX. 0.65 (T.P.) 0.24+ 0.08 − 0.07 0.1 ± 0.05 1.3 ± 0.1 1.2 8.1 ± 0.2 6.1 ± 0.2 1.0 ± 0.2 0.17 ± 0.03 0.5 0.13 0.10 3°+5° −3° 0.25 0.6 ± 0.15 S30MC-65-5A4-2 24 Data Sheet U14776EJ1V0DS00 µPD17P236 6. RECOMMENDED SOLDERING CONDITIONS For the µPD17P236 soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For other soldering methods, please consult with NEC personnel. Table 6-1. Soldering Conditions of Surface Mount Type (1) µ PD17P236M1GT: 28-pin plastic SOP (9.35 mm (375)) µ PD17P236M2GT: 28-pin plastic SOP (9.35 mm (375)) µ PD17P236M3GT: 28-pin plastic SOP (9.35 mm (375)) µ PD17P236M4GT: 28-pin plastic SOP (9.35 mm (375)) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Number of times: 2 max. Number of days: 7Note (after that, prebaking is necessary at 125°C for 10 hours) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Package peak temperature: 215°C, Time: 40 seconds max. (200°C min.), Number of days: 7Note (after that, prebaking is necessary at 125°C for 10 hours) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Solder bath temperature: 260°C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120°C max. (package surface temperature) Note Number of days: 7 (after that, prebaking is necessary at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) Symbol IR35-107-2 VPS VP15-107-2 Wave soldering WS60-107-1 Partial heating — Note After opening the dry pack, store it at 25 °C or less and 6.5 % RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U14776EJ1V0DS00 25 µPD17P236 (2) µ PD17P236M1MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M2MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M3MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) µ PD17P236M4MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) Soldering Method Intrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Note Number of times: 2 max. Number of days: 3 (after that, prebaking is necessary at 125°C for 10 hours) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Package peak temperature: 215°C, Time: 40 seconds max. (200°C min.), Note Number of times: 2 max. Number of days: 3 (after that, prebaking is necessary at 125°C for 10 hours) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Solder bath temperature: 260°C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120°C max. (package surface temperature) Note Number of days: 3 (after that, prebaking is necessary at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) Symbol IR35-103-2 VPS VP15-103-2 Wave soldering WS60-103-1 Partial heating — Note After opening the dry pack, store it at 25 °C or less and 6.5 % RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 26 Data Sheet U14776EJ1V0DS00 µPD17P236 APPENDIX. DEVELOPMENT TOOLS To develop the programs for the µPD17P236 subseries, the following development tools are available: Hardware Name In-circuit emulator IE-17K, IE-17K-ETNote 1 Remarks IE-17K and IE-17K-ET are the in-circuit emulators used in common with the 17K series microcontroller. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM compatible machines as the host machine with RS-232C. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOST TM. This is an SE board for µPD17236 subseries. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. EP-17K28GT is an emulation probe for 17K series 28-pin SOP (GM-375B). When used with Note 2 EV9500GT-28 , it connects an SE board to the target system. EP-17K30GS is an emulation probe for 17K series 30-pin SSOP (MC-5A4). When used with EV-9500GT-30Note 3, it connects an SE board to the target system. The EV-9500GT-28 is a conversion adapter for the 28-pin SOP (GM-375B). It is used to connect the EP-17K28GT and target system. The EV-9500GT-30 is a conversion adapter for the 30-pin SSOP (MC-5A4). It is used to ) connect the EP-17K30GS and target system. AF-9706, AF-9708, and AF-9709 are PROM programmers corresponding to µPD17P236. By connecting program adapter PA-17P236 to this PROM programmer, µPD17P236 can be programmed. PA-17P236 are adapters that is used to program µPD17P236, and is used in combination with AF-9706, AF-9708, or AF-9709. SE board (SE-17235) Emulation probe (EP-17K28GT) Emulation probe (EP-17K30GS) Conversion adapter (EV-9500GT-28Note 2) Conversion adapter (EV-9500GT-30 Note 3 PROM programmer Note 4 Note 4 (AF-9706 , AF-9708 , Note 4 AF-9709 ) Program adapter (PA-17P236) Notes 1. Low-cost model: External power supply type 2. Two EV-9500GT-28 are supplied with the EP-17K28GT. Five EV-9500GT-28 are optionally available as a set. 3. Two EV-9500GT-30 are supplied with the EP-17K30GS. Five EV-9500GT-30 are optionally available as a set. 4. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. (Tel: 033733-1166). Data Sheet U14776EJ1V0DS00 27 µPD17P236 Software Name 17K assembler (RA17K) Outline The RA17K is an assembler common to the 17K series products. When developing the program of devices, RA17K is used in combination with a device file (AS17235). Host Machine PC-9800 series IBM PC/AT compatible machine OS Japanese Windows TM Supply 3.5" 2HD Order Code µSAA13RA17K µSAB13RA17K µSBB13RA17K Japanese Windows 3.5" 2HC English Windows Device file (AS17235) The AS17235 is a device file for µPD17230, 17231, 17232, 17233, 17234, 17235, and 17236 and is used in combination with an assembler for the 17K series (RA17K). PC-9800 series IBM PC/AT compatible machine Japanese Windows 3.5" 2HD µSAA13AS17235 µSAB13AS17235 µSBB13AS17235 Japanese Windows 3.5" 2HC English Windows Support software (SIMPLEHOST) SIMPLEHOST is a software package that enables man-machine interface on the Windows when a program is developed by using an in-circuit emulator and a personal computer. PC-9800 series IBM PC/AT compatible machine Japanese Windows 3.5" 2HD µSAA13ID17K µSAB13ID17K µSBB13ID17K Japanese Windows 3.5" 2HC English Windows 28 Data Sheet U14776EJ1V0DS00 µPD17P236 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet U14776EJ1V0DS00 29 µPD17P236 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 30 Data Sheet U14776EJ1V0DS00 µPD17P236 SIMPLEHOST is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. Data Sheet U14776EJ1V0DS00 31 µPD17P236 • The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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