UPD17P709GC-3B9

DATA SHEET MOS INTEGRATED CIRCUIT µPD17P709 4-BIT SINGLE-CHIP MICROCONTROLLER WITH BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS The µPD17P709 is produced by replacing the built-in masked ROM of the µPD17704Note, µPD17705Note, µPD17707, µPD17708, and µPD17709 with a one-time PROM. The µPD17P709 allows programs to be written once, so that the µPD17P709 is suitable for preproduction in µPD17704, µPD17705, µPD17707, µPD17708, or µPD17709 system development or low-volume production. When reading this document, also refer to the publications on the µPD17704, µPD17705, µPD17707, µPD17708, or µPD17709. Note Under development The electrical characteristics (including power supply currents) and PLL analog characteristics of the µPD17P709 differ from those of the µPD17704, µPD17705, µPD17707, µPD17708, and µPD17709. In high-volume application set production, carefully check those differences. FEATURES • • • Compatible with the µPD17704, µPD17705, µPD17707, µPD17708, and µPD17709 Built-in one-time PROM Supply voltage : 32K bytes (16384 × 16 bits) : VDD = 5 V ±10% ORDERING INFORMATION Part number Package 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch) µPD17P709GC-3B9 The information in this document is subject to change without notice. Document No. U10142EJ2V0DS00 (2nd edition) Date Published November 1996 P Printed in Japan The mark shows major revised points. © 1995 µPD17P709 FUNCTION OVERVIEW Item Product (1/2) µPD17705Note 12288 × 16 bits (masked ROM) µPD17704Note 8192 × 16 bits (masked ROM) µPD17707 µPD17708 16384 × 16 bits (masked ROM) µPD17709 µPD17P709 16384 × 16 bits (one-time PROM) Program memory (ROM) General-purpose data memory (RAM) 672 × 4 bits 1120 × 4 bits 1776 × 4 bits Instruction execution time 1.78 µs (with 4.5-MHz crystal) General-purpose ports • I/O ports : 46 • Input ports : 12 • Output ports : 4 • Address stack : 15 levels • Interrupt stack : 4 levels • DBF stack : 4 levels (operated by software) • External : 6 (CE rising edge and INT0 to INT4) • Internal : 6 (timers 0 to 3, serial interfaces 0 and 1) 5 • • • • channels Basic timer (clock: 10, 20, 50, 100 Hz) 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 kHz) 8-bit timer (clock: 1 k, 2 k, 10 k, 100 kHz) 8-bit timer, also used for PWM (clock: 440 Hz, 4.4 kHz) Stack level Interrupt Timers : : : : 1 1 2 1 channel channel channels channel A/D converter D/A converter (PWM) 8 bits × 6 channels (Hardware or software mode can be selected.) 3 channels (8-bit or 9-bit resolution, selected by software.) Output frequency : 4.4 kHz, 440 Hz (8-bit PWM) 2.2 kHz, 220 Hz (9-bit PWM) 2 systems (3 channels) • 3-wire serial I/O • 2-wire serial I/O/I2C bus Serial interface : 2 channels : 1 channel PLL Frequency division system Reference frequency Charge pump Phase comparator • Direct frequency division system (VCOL pin (MF mode) : 0.5 to 3 MHz) • Pulse swallow system (VCOL pin (HF mode) : 10 to 40 MHz) (VCOH pin (VHF mode) : 60 to 130 MHz) Can be set to one of 13 frequencies (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, or 50 kHz). 2 error output pins (EO0 and EO1) Unlock detection is enabled by software. • Intermediate frequency measurement P1C0/FMIFC pin : 10 to 11 MHz in FMIF mode 0.4 to 0.5 MHz in AMIF mode P1C1/AMIFC pin : 0.4 to 0.5 MHz in AMIF mode • External gate width measurement P2A1/FCG1 and P2A0/FCG0 pins Intermediate frequency counter Note Under development 2 µPD17P709 (2/2) Item BEEP output Product µPD17704Note µPD17705Note µPD17707 µPD17708 µPD17709 µPD17P709 2 Output frequency : 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin) 67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin) • Power-on reset (when the power is turned on) • Reset using the RESET pin • Watchdog timer reset Can be set only once at power-on: 65,536 instructions, 131,072 instructions, or non-use can be selected. • Stack pointer overflow/underflow reset Can be set only once at power-on: the interrupt stack or address stack can be selected. • CE reset (CE pin: low → high) A CE reset delay timing can be set. • Power-failure detection function • Clock stop mode (STOP) • Halt mode (HALT) • PLL operation : VDD = 4.5 to 5.5 V • CPU operation : VDD = 3.5 to 5.5 V 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch) Reset Standby Supply voltage Package Note Under development 3 µPD17P709 PIN CONFIGURATION (TOP VIEW) 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch) µPD17P709GC-3B9 (1) Normal operation mode P0B2/SCK1 P0A1/SCK0 RESET P0A3/SDA P0B1/SO1 P0A0/SO0 P0A2/SCL P0B0/SI1 P0B3/SI0 GND0 P2D0 P2D1 P2D2 P0C0 VDD0 CE 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 INT2 P1A3/INT4 P1A2/INT3 P1A1 P1A0/TM0G P3A3 P3A2 P3A1 P3A0 P3B3 P3B2 P3B1 P3B0 P2A2 P2A1/FCG1 P2A0/FCG0 P1B3 P1B2/PWM2 P1B1/PWM1 P1B0/PWM0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P0C2 P0C3 P2C0 P2C1 P2C2 P2C3 P3D0 P3D1 P3D2 P3D3 P3C0 P3C1 P3C2 P3C3 P2B0 P2B1 P2B2 P2B3 INT0 INT1 GND2 P0D3/AD3 P0D2/AD2 P0D1/AD1 XIN P0D0/AD0 P1C3/AD5 P1C2/AD4 P1C1/AMIFC P1C0/FMIFC TEST P1D1/BEEP1 4 P1D0/BEEP0 VDD1 VCOH VCOL GND1 EO0 EO1 P1D3 P1D2 P0C1 REG XOUT µPD17P709 (2) PROM programming mode REGNote (OPEN) GND0 VDD0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 (L) 8 9 10 11 12 13 14 15 16 17 (OPEN) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 (L) (L) D0 D1 D2 D3 D4 D5 D6 D7 GND2 CLK (H) (L) GND1 MD3 MD2 MD1 MD0 VDD1 (L) VPP (L) (L) Note Connect to the same potential as VDD. Caution The parentheses above indicate the handling of the pins not used in PROM programming mode. L H : Connect each pin to GND through a resistor (470 ohms). : Connect each pin to VDD through a resistor (470 ohms). OPEN : Leave each pin open. (OPEN) (L) 5 µPD17P709 PIN NAMES AD0-AD5 AMIFC CE CLK D0-D7 EO0, EO1 FCG0, FCG1 FMIFC GND0-GND2 INT0-INT4 MD0-MD3 PWM0-PWM2 P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P1A0-P1A3 P1B0-P1B3 P1C0-P1C3 P1D0-P1D3 P2A0-P2A2 : A/D converter inputs : AM frequency counter input : Chip enable : Address update clock input : Data I/O : Error outputs : Frequency counter gate inputs : FM frequency counter input : Ground 0 to 2 : External interrupt inputs : Operating mode selection : D/A converter outputs : Port 0A : Port 0B : Port 0C : Port 0D : Port 1A : Port 1B : Port 1C : Port 1D : Port 2A P2B0-P2B3 P2C0-P2C3 P2D0-P2D2 P3A0-P3A3 P3B0-P3B3 P3C0-P3C3 P3D0-P3D3 REG RESET SCL SDA SI0, SI1 SO0, SO1 TEST TM0G VCOH VCOL VDD0, VDD1 VPP XIN, XOUT : Port 2B : Port 2C : Port 2D : Port 3A : Port 3B : Port 3C : Port 3D : CPU regulator : Reset input : 2-wire serial clock I/O : 2-wire serial data I/O : 3-wire serial data input : 3-wire serial data output : Test input : Timer 0 gate input : Local oscillation high input : Local oscillation low input : Power supply : Program voltage application : Main clock oscillation BEEP0, BEEP1 : Beep outputs SCK0, SCK1 : 3-wire serial clock I/O 6 µPD17P709 BLOCK DIAGRAM P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P1A0-P1A3 P1B0-P1B3 P1C0(MD0)P1C3(MD3) P1D0-P1D3 P2A0-P2A2 P2B0-P2B3 P2C0(D0)-P2C3(D3) P2D0-P2D2 P3A0-P3A3 P3B0-P3B3 P3C0-P3C3 P3D0(D4)-P3D3(D7) AD0/P0D0 AD1/P0D1 AD2/P0D2 AD3/P0D3 AD4/P1C2 AD5/P1C3 PWM0/P1B0 PWM1/P1B1 PWM2/P1B2 4 4 RF 4 4 4 4 4 4 Ports 3 4 4 3 4 4 4 4 Program counter 8-bit timer 0 Gate counter 8-bit timer 1 D/A converter 8-bit timer 3 Basic timer GND0-GND2 VCPU Regurator REG 8-bit timer 2 CPU Peripheral XIN(CLK) XOUT CE RESET VDD0,VDD1 Frequency counter One-time PROM 16384 × 16 bits Interrupt control Instruction decoder BEEP ALU Serial interface 1 SYSREG RAM 1776 × 4 bits Serial interface 0 PLL VCOH VCOL EO0 EO1 SO0/P0A0 SCK0/P0A1 SCL/P0A2 SDA/P0A3 SI0/P0B3 SCK1/P0B2 SO1/P0B1 SI1/P0B0 BEEP0/P1D0 BEEP1/P1D1 INT0 INT1 INT2 INT3/P1A2 INT4/P1A3 FCG0/P2A0 FCG1/P2A1 FMIFC/P1C0 AMIFC/P1C1 A/D converter Stack TM0G/P1A0 OSC Reset Remark Pins enclosed in parentheses are used in PROM programming mode. 7 µPD17P709 CONTENTS 1. PIN FUNCTIONS ......................................................................................................................... 1.1 1.2 1.3 1.4 1.5 1.6 NORMAL OPERATION MODE ....................................................................................................... PROM PROGRAMMING MODE ..................................................................................................... EQUIVALENT CIRCUIT OF PINS .................................................................................................. HANDLING UNUSED PINS ............................................................................................................ NOTES ON USE OF THE CE, INT0-INT4, AND RESET PINS (ONLY IN NORMAL OPERATION MODE) ....................................................................................................................... NOTES ON USE OF THE TEST PIN (ONLY IN NORMAL OPERATION MODE) ...................... 9 9 13 14 19 21 21 2. ONE-TIME PROM (PROGRAM MEMORY) WRITE, READ, AND VERIFICATION ................ 2.1 2.2 2.3 OPERATING MODES FOR PROGRAM MEMORY WRITE, READ, AND VERIFICATION ........ PROGRAM MEMORY WRITE PROCEDURE ............................................................................... PROGRAM MEMORY READ PROCEDURE ................................................................................. 22 23 24 25 3. 4. 5. ELECTRICAL CHARACTERISTICS .......................................................................................... PACKAGE DRAWING ................................................................................................................ RECOMMENDED SOLDERING CONDITIONS ....................................................................... 26 31 32 33 APPENDIX DEVELOPMENT TOOLS .............................................................................................. 8 µPD17P709 1. PIN FUNCTIONS 1.1 NORMAL OPERATION MODE Pin No. 1 41 42 2 3 4 5 Symbol INT2 INT1 INT0 P1A3/INT4 P1A2/INT3 P1A1 P1A0/TM0G Function Input for edge-detected vectored. Either a rising edge or falling edge can be selected. Output format — Input for port 1A, external interrupt request signal, and event signal — • • • P1A3-P1A0 • 4-bit input port INT4, INT3 • Edge-detected vectored interrupt TM0G • Gate input for 8-bit timer 0 When reset When the clock is stopped Held Power-on reset Input (P1A3-P1A0) 6 to 9 P3A3 to P3A0 WDT&SP reset Input (P1A3-P1A0) CE reset Held 4-bit I/O port. Input/output can be specified in 4-bit units. When reset Power-on reset Input WDT&SP reset Input CE reset Held When the clock is stopped Held CMOS push-pull 10 to 13 P3B3 to P3B0 4-bit I/O port. Input/output can be specified in 4-bit units. When reset Power-on reset Input WDT&SP reset Input CE reset Held When the clock is stopped Held CMOS push-pull 14 15 16 P2A2 P2A1/FCG1 P2A0/FCG0 Input for port 2A and external gate counter • P2A2-P2A0 • 3-bit I/O port • Input/output can be specified bit by bit. • FCG1, FCG0 • External gate counter input When reset Power-on reset Input (P2A2-P2A0) WDT&SP reset Input (P2A2-P2A0) CE reset Held (P2A2-P2A0) When the clock is stopped Held (P2A2-P2A0) CMOS push-pull 9 µPD17P709 Pin No. 17 18 to 20 Symbol P1B3 P1B2/PWM2 to P1B0/PWM0 Function Output for port 1B and D/A converter • P1B3-P1B0 • 4-bit output port • PWM2-PWM0 • 8-bit or 9-bit D/A converter output When reset Power-on reset Low-level output (P1B3-P1B0) 21 33 75 22 to 25 GND2 GND1 GND0 P0D3/AD3 to P0D0/AD0 Input for port 0D and A/D converter • P0D3-P0D0 • 4-bit input port • A pull-down resistor can be set bit by bit. • AD3-AD0 • Analog input for 8-bit-resolution A/D converter When reset Power-on reset Input with pulldown resistors (P0D3-P0D0) 26 27 28 29 P1C3/AD5 P1C2/AD4 P1C1/AMIFC P1C0/FMIFC WDT&SP reset Input with pulldown resistors (P0D3-P0D0) CE reset Held When the clock is stopped Held — Ground WDT&SP reset Low-level output (P1B3-P1B0) CE reset Held When the clock is stopped Held (P1B3-P1B0) — Output format N-ch open-drain (12-V withstand voltage) Input for port 1C, A/D converter, and IF counter — • • • P1C3-P1C0 • 4-bit input port AD5, AD4 • Analog input for 8-bit-resolution A/D converter FMIFC, AMIFC • Frequency counter input When reset Power-on reset WDT&SP reset Input (P1C3-P1C0) CE reset • P1C3/AD5, P1C2/AD4 Held • P1C1/AMIFC, P1C0/FMIFC Input (P1C1, P1C0) When the clock is stopped • P1C3/AD5, P1C2/AD4 Held • P1C1/AMIFC, P1C0/FMIFC Input (P1C1, P1C0) Input (P1C3-P1C0) 10 µPD17P709 Pin No. 30 79 Symbol VDD1 VDD0 Function Power supply. Apply the same voltage to the VDD1 and VDD0 pins. • When the CPU and peripheral functions are operating: 4.5 to 5.5 V • When only the CPU is operating: 3.5 to 5.5 V • When the clock is stopped: 2.2 to 5.5 V Input for PLL local oscillation (VCO) frequency • VCOH • Active when VHF mode is selected by software. Otherwise, pulled down. • VCOL • Active when HF or MW mode is selected by software. Otherwise, pulled down. Inputs to these pins are to be AC-amplified. Cut, therefore, the DC components in the input signals by using capacitors. 34 35 EO0 EO1 Output from the charge pump of the PLL frequency synthesizer. The result of phase comparison between the divided local oscillation frequency and reference frequency is output. When reset Power-on reset High-impedance output 36 TEST WDT&SP reset CE reset When the clock is stopped CMOS tristate Output format — 31 32 VCOH VCOL — High-impedance High-impedance High-impedance output output output — Test input pin. Be sure to connect it to GND. Output for port 1D and BEEP • P1D3-P1D0 • 4-bit I/O port • Input/output can be specified bit by bit. • BEEP1, BEEP0 • BEEP output When reset Power-on reset Input (P1D3-P1D0) WDT&SP reset Input (P1D3-P1D0) CE reset Held (P1D3-P1D0) When the clock is stopped Held (P1D3-P1D0) 37 38 39 40 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 CMOS push-pull 43 to 46 P2B3 to P2B0 4-bit I/O port. Input/output can be specified bit by bit. When reset Power-on reset Input WDT&SP reset Input CE reset Held When the clock is stopped Held CMOS push-pull 47 to 50 P3C3 to P3C0 4-bit I/O port. Input/output can be specified in 4-bit units. When reset Power-on reset Input WDT&SP reset Input CE reset Held When the clock is stopped Held CMOS push-pull 11 µPD17P709 Pin No. 51 to 54 Symbol P3D3 to P3D0 Function 4-bit I/O port. Input/output can be specified in 4-bit units. When reset Power-on reset Input 55 to 58 P2C3 to P2C0 WDT&SP reset Input CE reset Held When the clock is stopped Held CMOS push-pull Output format CMOS push-pull 4-bit I/O port. Input/output can be specified bit by bit. When reset Power-on reset Input WDT&SP reset Input CE reset Held When the clock is stopped Held 59 to 62 P0C3 to P0C0 4-bit I/O port. Input/output can be specified bit by bit. When reset Power-on reset Input WDT&SP reset Input CE reset Held When the clock is stopped Held CMOS push-pull 63 64 65 66 67 68 69 70 P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 Input/output for P0A or P0B and serial interface • P0A3-P0A0 • 4-bit I/O port • Input/output can be specified bit by bit. • P0B3-P0B0 • 4-bit I/O port • Input/output can be specified bit by bit. • SDA, SCL • Serial data and serial clock I/O when the 2-wire serial I/O or I2C bus of serial interface 0 is selected. • SCK0, SO0, SI0 • Serial clock I/O, serial data output, and serial data input when the 3-wire serial I/O of serial interface 0 is selected. • SCK1, SO1, SI1 • Serial clock I/O, serial data output, and serial data input when the 3-wire serial I/O of serial interface 1 is selected. When reset Power-on reset Input P0A3-P0A0 P0B3-P0B0 WDT&SP reset Input P0A3-P0A0 P0B3-P0B0 CE reset Held P0A3-P0A0 P0B3-P0B0 When the clock is stopped Held P0A3-P0A0 P0B3-P0B0 N-ch open-drain CMOS push-pull 71 to 73 P2D2 to P2D0 3-bit I/O port. Input/output can be specified bit by bit. When reset Power-on reset Input WDT&SP reset Input CE reset Held When the clock is stopped Held CMOS push-pull 12 µPD17P709 Pin No. 74 Symbol REG Function CPU regulator. Use 0.1-µF capacitor to connect it to GND. A crystal is connected to these pins. Output format — 76 77 78 XOUT XIN CE — Input for device operation selection, CE reset, and interrupt signals • Device operation selection When CE is high, the PLL frequency synthesizer can be operated. When CE is low, the PLL frequency synthesizer is automatically disabled by the device. • CE reset Setting CE from low to high resets the device upon the detection of a rising edge of the internal basic timer setting pulse. A reset timing delay can also be specified. • Interrupt A vectored interrupt occurs upon the detection of a falling edge of the input signal. Reset input — 80 RESET — 1.2 PROM PROGRAMMING MODE Pin No. 26 to 29 21 33 75 36 Symbol MD3 to MD0 GND2 GND1 GND0 VPP Function Input for operating mode selection for program memory write, read, or verification Output format — Ground — Pin to which program voltage is applied during program memory write, read, or verification. +12.5 V is applied. Power supply pins. +6 V is applied during program memory write, read, or verification. 8-bit data I/O for program memory write, read, or verification — 30 79 51 to 58 77 VDD1 VDD0 D7 to D0 CLK — CMOS push-pull Clock input for address updating during program memory write, read, or verification — Remark The pins other than those listed above are not used in PROM programming mode. For the handling of the unused pins, see PIN CONFIGURATION, (2) PROM programming mode. 13 µPD17P709 1.3 EQUIVALENT CIRCUIT OF PINS (1) P0A (P0A1/SCK0, P0A0/SO0) P0B (P0B3/SI0, P0B2/SCK1, P0B1/SO1, P0B0/SI1) P0C (P0C3, P0C2, P0C1, P0C0) P1D (P1D3, P1D2, P1D1/BEEP1, P1D0/BEEP0) P2A (P2A2, P2A1/FCG1, P2A0/FCG0) P2B (P2B3, P2B2, P2B1, P2B0) P2C (P2C3, P2C2, P2C1, P2C0) P2D (P2D2, P2D1, P2D0) P3A (P3A3, P3A2, P3A1, P3A0) P3B (P3B3, P3B2, P3B1, P3B0) P3C (P3C3, P3B2, P3C1, P3C0) P3D (P3D3, P3D2, P3D1, P3D0) (I/O) VDD CKSTOPNote VDD Note In this circuit, a current drained by noise does not increase even if the circuit is in the floating state, because of the internal signal being output when the clock stop instruction is executed. 14 µPD17P709 (2) P0A (P0A3/SDA, P0A2/SCL) (I/O) VDD CKSTOPNote Note In this circuit, a current drained by noise does not increase even if the circuit is in the floating state, because of the internal signal being output when the clock stop instruction is executed. (3) P1B (P1B3, P1B2/PWM2, P1B1/PWM1, P1B0/PWM0) (Output) (4) P0D (P0D3/AD3, P0D2/AD2, P0D1/AD1, P0D0/AD0) (Input) A/D converter VDD CKSTOPNote P0DPLD flag High on-state resistor Note In this circuit, a current drained by noise does not increase even if the circuit is in the floating state, because of the internal signal being output when the clock stop instruction is executed. 15 µPD17P709 (5) P1A (P1A1) (Input) VDD (6) P1C (P1C3/AD5, P1C2/AD4) (Input) VDD A/D converter (7) P1C (P1C1/AMIFC, P1C0/FMIFC) (Input) VDD General-purpose port VDD High on-state resistor VDD Frequency counter 16 µPD17P709 (8) CE RESET INT0, INT1, INT2 P1A (P1A3/INT4, P1A2/INT3, P1A0/TM0G) VDD (Schmitt-triggered input) (9) XOUT (Output), XIN (Input) VDD High on-state resistor VDD XIN Internal clock High on-state resistor XOUT (10) EO1, EO0 (Output) VDD DWN UP 17 µPD17P709 (11) VCOH, VCOL (Input) VDD High on-state resistor VDD High on-state resistor 18 µPD17P709 1.4 HANDLING UNUSED PINS The unused pins should be handled as indicated in Table 1-1. Table 1-1 Pin P0D3/AD3-P0D0/AD0 P1C3/AD5 P1C2/AD4 P1C1/AMIFCNote 2 P1C0/FMIFCNote 2 P1A3/INT4 P1A2/INT3 P1A1 P1A0/TM0G P1B3 P1B2/PWM2-P1B0/PWM0 P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 P0C3-P0C0 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 P2A2 P2A1/FCG1 P2A0/FCG0 P2B3-P2B0 P2C3-P2C0 P2D2-P2D0 Port pins N-ch open-drain output I/ONote 3 I/O format Input Handling Unused Pins Recommended handling Connect each pin to GND through a resistor.Note 1 (1/2) Specify as a port and connect each pin to VDD or GND through a resistor.Note 1 Connect each pin to GND through a resistor.Note 1 Specify low output, in the software, and leave open. Specify as a general-purpose input port, in the software, and connect each pin to VDD or GND through a resistor.Note 1 Notes 1. When making an external connection to VDD with a pull-up resistor, or to GND with a pull-down resistor, note the following: If the resistance of the pull-up or pull-down resistor is too high, the pin approaches the high impedance state, thus increasing the through current drawn by the port. In general, pull-up and pull-down resistors should have a resistance of between 20 and 50 kilohms, depending on the application circuit. 2. Do not specify AMIFC or FMIFC. If AMIFC or FMIFC is specified, current drain increases. 3. I/O ports become general-purpose input ports upon power-on reset, reset by the RESET pin, watchdog timer reset, or stack overflow/underflow reset. 19 µPD17P709 (2/2) Pin P3A3-P3A0 Port pins P3B3-P3B0 P3C3-P3C0 P3D3-P3D0 CE Other than port pins EO1 EO0 INT0-INT2 RESET TEST VCOH VCOL Input Input Output Connect to VDD through a resistor.Note 1 Leave each pin open. I/O format I/ONote 2 Recommended handling Specify as a general-purpose input port, in the software, and connect each pin to VDD or GND through a resistor.Note 1 Input Input — Connect each pin to GND through a resistor.Note 1 Connect to VDD through a resistor.Note 1 Connect directly to GND. Disable PLL, in the program, and leave each pin open. Notes 1. When making an external connection to VDD with a pull-up resistor, or to GND with a pull-down resistor, note the following: If the resistance of the pull-up or pull-down resistor is too high, the pin approaches the high impedance state, thus increasing the through current drawn by the port. In general, pull-up and pull-down resistors should have a resistance of between 20 and 50 kilohms, depending on the application circuit. 2. I/O ports become general-purpose input ports upon power-on reset, reset by the RESET pin, watchdog timer reset, or stack overflow/underflow reset. 20 µPD17P709 1.5 NOTES ON USE OF THE CE, INT0-INT4, AND RESET PINS (ONLY IN NORMAL OPERATION MODE) The CE, INT0-INT4, and RESET pins can be used as the test mode selection pin for testing the internal operation of the µPD17P709 (IC test), besides the usage shown in Section 1.1. Applying a voltage exceeding VDD to the CE, INT0-INT4, or RESET pin causes the µPD17P709 to enter test mode. When noise exceeding VDD comes in during normal operation, the device may not operate normally. For example, if the wiring from the CE, INT0-INT4, or RESET pin is too long, noise may be induced on the wiring, causing this mode switching. When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If noise yet arises, use an external part to suppress it as shown below. • Connect a diode with low VF between the pin and VDD. VDD VDD • Connect a capacitor between the pin and VDD. Diode with low VF VDD VDD CE, INT0-INT4, RESET CE, INT0-INT4, RESET 1.6 NOTES ON USE OF THE TEST PIN (ONLY IN NORMAL OPERATION MODE) Applying VDD to the TEST pin causes the µPD17P709 to enter test mode or program memory write/verify mode. Keep the wiring as short as possible and connect the TEST pin directly to the GND pin. When the wiring between the TEST pin and GND pin is too long or external noise enters the TEST pin, a voltage difference may occur between the TEST pin and GND pin. When this happens, your program may malfunction. GND TEST Keep the wiring as short as possible. 21 µPD17P709 2. ONE-TIME PROM (PROGRAM MEMORY) WRITE, READ, AND VERIFICATION The program memory built into the µPD17P709 is a one-time PROM (16384 × 16 bits) that is electrically writable. In normal operation, this PROM is accessed on a 16-bit word basis. During program memory write, read, and verification, the PROM is accessed on an 8-bit word basis. The higher 8 bits of a 16-bit word are located at an evennumbered address, and the lower 8 bits are located at an odd-numbered address. For PROM write, read, and verification, PROM programming mode must be specified, and the pins listed in Table 2-1 are used. In this case, address input is not used. Instead, clock input on the CLK pin is used to update addresses. Table 2-1 Pins Used for Program Memory Write, Read, and Verification Pin VPP CLK MD0-MD3 D0-D7 VDD0, VDD1 Function Used to apply the program voltage (+12.5 V) Used to apply an address update clock Used to select an operating mode Used to input/output 8-bit data Used to apply the power supply voltage (+6 V) For writing to the built-in PROM, a specified PROM programmer and dedicated programmer adapter are to be used. The following PROM programmers and programmer adapters are usable: PROM programmer PG-1500 + PA-17KDZ (adapter for PG-1500) Programmer adapter PA-17P709GC Third-party PROM programmers are also available: For example, AF-9703, AF-9704, AF-9705, and AF-9706 (manufactured by Ando Electric Co., Ltd.) 22 µPD17P709 Fig. 2-1 PA17P709GC and PA-17KDZ PA-17P709GC PA-17KDZ To PG-1500 2.1 OPERATING MODES FOR PROGRAM MEMORY WRITE, READ, AND VERIFICATION The µPD17P709 is placed in program memory write, read, and verify mode when +6 V is applied to the VDD pin, and +12.5 V to the VPP pin. In this mode, one of the operating modes indicated in Table 2-2 is set, depending on the setting of the MD0 to MD3 pins. The input pins that are not used for program memory write, read, and verification are connected to GND through a pull-down resistor (470 ohms). (See PIN CONFIGURATION, (2) PROM programming mode.) Table 2-2 Operating Modes for Program Memory Write, Read, and Verication Operating mode specification VPP +12.5V VDD +6V MD0 MD1 MD2 MD3 H L L H L H L X H H H H L H H H Operating mode Program memory address zero-clear mode Write mode Read/verify mode Program inhibit mode Remark X: L or H 23 µPD17P709 2.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is described below. The procedure allows high-speed write operation. (1) Connect the unused pins to GND through pull-down resistors. The CLK pin must be low. (2) Apply 5 V to the VDD pin. The VPP pin must be low. (3) Apply 5 V to the VPP pin after waiting 10 µs. (4) Specify program memory address zero-clear mode, using the mode setting pins. (5) Apply 6 V to VDD, and 12.5 V to VPP. (6) Program inhibit mode (7) Write data in 1-ms write mode. (8) Program inhibit mode (9) Verify mode. When data has been written normally, proceed to step (10). When data has not been written normally, repeat steps (7) to (9). (10) Perform an additional write operation ((X: Number of write operations performed in steps (7) to (9)) × 1 ms). (11) Program inhibit mode (12) Apply four pulses to the CLK pin to increment the program memory address by 1. (13) Repeat steps (7) to (12) until the last address is reached. (14) Program memory address zero-clear mode (15) Change the voltage applied to the VDD and VPP pins to 5 V. (16) Turn off the power. Steps (2) to (12) are illustrated below. Repeat X times Reset Write Verify Additional write Address increment VDD + 1 VDD VDD GND VPP VDD GND CLK VPP D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z Data input Hi-Z MD0 MD1 MD2 MD3 24 µPD17P709 2.3 PROGRAM MEMORY READ PROCEDURE (1) Connect the unused pins to GND through pull-down resistors. The CLK pin must be low. (2) Apply 5 V to the VDD pin. The VPP pin must be low. (3) Apply 5 V to the VPP pin after waiting 10 µs. (4) Specify program memory address zero-clear mode, using the mode setting pins. (5) Apply 6 V to VDD, and 12.5 V to VPP. (6) Program inhibit mode (7) Verify mode. When a clock pulse signal is applied to the CLK pin, data is output for each address every four clock pulses. (8) Program inhibit mode (9) Program memory address zero-clear mode (10) Change the voltage applied to the VDD and VPP pins to 5 V. (11) Turn off the power. Steps (2) to (9) are illustrated below. Reset VDD + 1 VDD VDD GND VPP VPP VDD GND CLK Hi-Z D0-D7 Data output Data output Hi-Z MD0 MD1 “L” MD2 MD3 25 µPD17P709 3. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Supply voltage PROM program voltage Input voltage Symbol VDD VPP VI At other than CE, INT0-INT4, and RESET pins CE, INT0-INT4, and RESET pins Output voltage High output current VO IOH At other than P1B0-P1B3 At one pin Total for P2A0-P2A2, P3A0-P3A3, and P3B0-P3B3 Total for P0A0-P0A3, P0B0-P0B3, P0C0-P0C3, P1D0-P1D3, P2B0-P2B3, P2C0-P2C3, P2D0-P2D2, P3C0-P3C3, and P3D0-P3D3 Low output current IOL At one pin of P1B0-P1B3 At one pin of other than P1B0-P1B3 Total for P2A0-P2A2, P3A0-P3A3, and P3B0-P3B3 Total for P0A0-P0A3, P0B0-P0B3, P0C0-P0C3, P1D0-P1D3, P2B0-P2B3, P2C0-P2C3, P2D0-P2D2, P3C0-P3C3, and P3D0-P3D3 Total for P1B0-P1B3 Output withstand voltage Total loss Operating ambient temperature Storage temperature VBDS Pt TA P1B0-P1B3 Condition Rating –0.3 to +6.0 –0.3 to +13.5 –0.3 to VDD + 0.3 –0.3 to VDD + 0.6 –0.3 to VDD + 0.3 –8.0 –15.0 Unit V V V V V mA mA –25.0 mA 12.0 8.0 15.0 mA mA mA 25.0 mA 25.0 14.0 200 –40 to +85 mA V mW °C °C Tstg –55 to +125 Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. RECOMMENDED OPERATING RANGES (TA = –40 to +85 °C) Parameter Supply voltage Symbol VDD1 VDD2 Condition While the CPU and PLL are operating While the CPU is operating but the PLL is halted Min. 4.5 3.5 Typ. 5.0 5.0 Max. 5.5 5.5 Unit V V RECOMMENDED OUTPUT WITHSTAND VOLTAGE (TA = –40 to +85 °C) Parameter Output withstand voltage Symbol VBDS P1B0-P1B3 Condition Min. Typ. Max. 12 Unit V 26 µPD17P709 DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V) Parameter Supply current Symbol IDD1 Condition The CPU is operating but the PLL is halted, with a sinusoidal wave applied to the XIN pin. (fIN = 4.5 MHz ±1%, VIN = VDD) The CPU and PLL are halted, with a sinusoidal wave applied to the XIN pin. (fIN = 4.5 MHz ±1%, VIN = VDD) The HALT instruction is used. The crystal oscillator is operating. The crystal oscillator is halted. The timer flip-flop is used for detecting power failure. Data memory contents are held. The crystal oscillator is halted. VDD = 5 V, TA = 25 °C 3.5 2.2 Min. Typ. 1.5 Max. 3.0 Unit mA IDD2 0.7 1.5 mA Data hold voltage VDDR1 VDDR2 5.5 5.5 V V VDDR3 Data hold current IDDR1 IDDR2 High input voltage VIH1 2.0 2.0 2.0 5.5 4.0 30.0 VDD V µA µA V 0.7VDD P0A0, P0B1, P0C0-P0C3, P1A0, P1A1, P1C0-P1C3, P1D0-P1D3, P2A2, P2B0-P2B3, P2C0-P2C3, P2D0-P2D2, P3A0-P3A3, P3B0-P3B3, P3C0-P3C3, P3D0-P3D3 P0A1-P0A3, P0B0, P0B2, P0B3, P2A0, P2A1, CE, INT0-INT4, RESET P0D0-P0D3 P0A0, P0B1, P0C0-P0C3, P1A0, P1A1,P1C0-P1C3, P1D0-P1D3, P2A2, P2B0-P2B3, P2C0-P2C3, P2D0-P2D2, P3A0-P3A3, P3B0-P3B3, P3C0-P3C3, P3D0-P3D3 P0A1-P0A3, P0B0, P0B2, P0B3, P2A0, P2A1, CE, INT0-INT4, RESET P0D0-P0D3 P0A0-P0A3, P0B0-P0B3, P0C0-P0C3, P1D0-P1D3, P2A0-P2A2, P2B0-P2B3, P2C0-P2C3, P2D0-P2D2, P3A0-P3A3, P3B0-P3B3, P3C0-P3C3, P3D0-P3D3 VOH = VDD – 1 V EO0, EO1 VDD = 4.5 to 5.5 V, VOH = VDD – 1 V 0.8VDD VIH2 VDD V VIH3 Low input voltage VIL1 0.55VDD 0 VDD 0.3VDD V V VIL2 0 0.2VDD V VIL3 High output current IOH1 0 –1.0 0.15VDD V mA IOH2 Low output current IOL1 –3.0 1.0 mA mA P0A0-P0A3, P0B0-P0B3, P0C0-P0C3, P1D0-P1D3, P2A0-P2A2, P2B0-P2B3, P2C0-P2C3, P2D0-P2D2, P3A0-P3A3, P3B0-P3B3, P3C0-P3C3, P3D0-P3D3 VOL = 1 V EO0, EO1 P1B0-P1B3 P0D0-P0D3 are pulled down. P1B0-P1B3 EO0, EO1 Input pin VDD = 4.5 to 5.5 V, VOL = 1 V VOL = 1 V VIN = VDD VIN = 12 V VIN = VDD, VIN = 0 V VIN = VDD IOL2 IOL3 High input current Output-off leakage current High input leakage current Low input leakage current IIH ILO1 ILO2 ILIH 3.0 7.0 5.0 150 1.0 ± 1.0 1.0 mA mA µA µA µA µA µA ILIL Input pin VIN = 0 V –1.0 27 µPD17P709 AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 5 V ±10%) Parameter Operating frequency Symbol fIN1 Condition VCOL pin in MF mode Sinusoidal wave applied to the VIN pin = 0.15Vp-p Sinusoidal wave applied to the VIN pin = 0.20Vp-p fIN2 VCOL pin in HF mode, with a sinusoidal wave applied to the VIN pin = 0.1Vp-pNote VCOH pin in VHF mode, with a sinusoidal wave applied to the VIN pin = 0.1Vp-pNote AMIFC pin, with a sinusoidal wave applied to the VIN pin = 0.15Vp-p FMIFC pin in FMIF count mode, with a sinusoidal wave applied to the VIN pin = 0.20Vp-p FMIFC pin in AMIF count mode, with a sinusoidal wave applied to the VIN pin = 0.15Vp-p External clock External clock Min. 0.8 Typ. Max. 3 Unit MHz 0.5 3 MHz 10 40 MHz fIN3 60 130 MHz fIN4 0.4 0.5 MHz fIN5 10 11 MHz fIN6 SIO0 input frequency fIN7 SIO1 input frequency fIN8 0.4 0.5 MHz 1 0.7 MHz MHz Note The condition of sinusoidal wave input VIN = 0.1Vp-p is the rated value when the µPD17P709 alone is operating. Where influence of noise must be taken into consideration, operation under input amplitude condition of VIN = 0.15Vp-p is recommended. A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = 5 V ±10%) Parameter Total error in A/D conversion Total error in A/D conversion Symbol 8 bits TA = 0 to 85 °C Condition Min. Typ. Max. ±3.0 ±2.5 Unit LSB 8 bits LSB REFERENCE CHARACTERISTICS (TA = +25 °C, VDD = 5.0 V) Parameter Supply current Symbol IDD3 Condition The CPU and PLL are operating, with a sinusoidal wave applied to the VCOH pin. (fIN = 130 MHz, VIN = 0.3Vp-p) Min. Typ. 6.0 Max. 12.0 Unit mA 28 µPD17P709 DC PROGRAMMING CHARACTERISTICS (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.5 V) Parameter Input high voltage Symbol VIH1 VIH2 Input low voltage VIL1 VIL2 Input leakage current Output high voltage Output low voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Condition Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = –1 mA IOL = 1 mA VDD – 1.0 1.0 30 30 Min. 0.7VDD VDD – 0.5 0 0 Typ. Max. VDD VDD 0.2VDD 0.4 10 Unit V V V V µA V V mA mA Cautions 1. VPP must be under +13.5 V including overshoot. 2. VDD must be applied before VPP on and must be off after VPP off. AC PROGRAMMING CHARACTERISTICS (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.5 V) Parameter MD1 setup time (referred to MD0↓) Data setup time (referred to MD0↓) Address hold timeNote 2 (referred to MD0↑) Data hold time (referred to MD0↑) Data output float delay from MD0↑ VPP setup time (referred to MD3↑) VDD setup time (referred to MD3↑) Initial program pulse width Additional program pulse width MD0 setup time (referred to MD1↑) Data output delay from MD0↓ MD1 hold time (referred to MD0↑) MD1 recovery time (referred to MD0↓) Program counter reset time CLK input high, low level range CLK input frequency Initial mode set time MD3 setup time (referred to MD1↑) MD3 hold time (referred to MD1↓) MD3 setup time (referred to MD0↓) Data output delay from address incrementNote 2 MD3 hold time (referred to MD0↑) Data output float delay from MD3↓ Reset setup time Symbol Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR — — — — — — — tACC tOH — — — 10 When reading program memory 2 2 2 2 2 0 2 2 130 MD0 = MD1 = VIL tM1H + tM1R ≥ 50 µs 2 2 10 0.125 4.19 Condition Min. 2 2 2 2 2 0 2 2 0.95 0.95 2 1 1.0 1.05 21.0 130 Typ. Max. Unit Address setup timeNote 2 (referred to MD0↓) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH,tXL fX tI tM3S tM3H tM3SR tDAD µs µs µs µs µs ns µs µs ms ms µs µs µs µs µs µs MHz µs µs µs µs µs ns Data output hold time from address incrementNote 2 tHAD tM3HR tDFR tRES µs µs µs Notes 1. Symbols used for the µPD27C256 (The µPD27C256 is used only for maintenance.) 2. The internal address signal is incremented by 1 on the falling edge of the third clock (CLK) pulse, with four CLK pulses treated as one cycle. Internal addresses are not connected to pins. 29 µPD17P709 Write program memory timing tRES tVPS VPP VPP VDD tVDS tXH GND VDD + 1 VDD VDD GND CLK tXL D0-D7 tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM1S tM1H tM3H tM1R tM0S tOPW Data input tDS tDH Data output tDV tDF Data input tDS tDH tAH tAS Data input Remark The dashed line indicates high-impedance. Read program memory timing tRES tVPS VPP VPP VDD GND VDD VDD + 1 VDD GND CLK tXL Hi-Z D0-D7 tI MD0 tDV tM3HR Data output Data output tDFR tDAD tHAD Hi-Z tXH tVDS MD1 L tPCR MD2 tM3SR MD3 30 µPD17P709 4. PACKAGE DRAWING 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end CD S Q R 80 1 21 20 F G H P I M J K M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.2 ± 0.4 14.0 ± 0.2 14.0 ± 0.2 17.2 ± 0.4 0.825 0.825 0.30 ± 0.10 0.13 0.65 (T.P.) 1.6 ± 0.2 0.8 ± 0.2 0.15 +0.10 –0.05 0.10 2.7 0.1 ± 0.1 5°±5° 3.0 MAX. INCHES 0.677 ± 0.016 0.551 +0.009 –0.008 0.551 +0.009 –0.008 0.677 ± 0.016 0.032 0.032 0.012 +0.004 –0.005 0.005 0.026 (T.P.) 0.063 ± 0.008 0.031 +0.009 –0.008 0.006 +0.004 –0.003 0.004 0.106 0.004 ± 0.004 5°±5° 0.119 MAX. S80GC-65-3B9-4 31 µPD17P709 5. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µPD17P709. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 5-1 Soldering Conditions for Surface-Mount Devices µPD17P709GC-3B9: 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch) Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 °C Reflow time: 30 seconds or less (at 210 °C or more) Maximum allowable number of reflow processes: 2 VPS Peak package's surface temperature: 215 °C Reflow time: 40 seconds or less (at 200 °C or more) Maximum allowable number of reflow processes: 2 Wave soldering Solder temperature: 260 °C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature: 120 °C max. (measured on the package surface) Partial heating method Terminal temperature: 300 °C or less Heat time: 3 seconds or less (for one side of a device) — WS60-00-1 VP15-00-2 Recommended conditions IR35-00-2 Caution Do not apply more than a single process at once, except for “Partial heating method.” 32 µPD17P709 APPENDIX DEVELOPMENT TOOLS The following support tools are available for developing programs for the µPD17P709. Hardware Name In-circuit emulator IE-17K IE-17K-ETNote 1 EMU-17KNote 2 Description The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K series. The IE-17K and IE-17K-ET are connected to the host machine (PC-9800 series or IBM PC/ ATTM) through the RS-232C interface. The EMU-17K is inserted into the extension slot of the host machine (PC-9800 series). Use the system evaluation board (SE board) corresponding to each product together with one of these in-circuit emulators. SIMPLEHOSTTM, a man machine interface, implements an advanced debug environment. The EMU-17K also enables user to check the contents of the data memory in real time. The SE-17709 is an SE board for the µPD17709 sub-series. It is used alone for evaluating the system. It is also used for debugging, in combination with an in-circuit emulator. The EP-17K80GC is an emulation probe for the µPD17P709GC. When used with the EV9200GC-80Note 3, this emulation probe connects the SE board to the target system. The EV-9200GC-80 is a conversion socket for the 80-pin plastic QFP (14 × 14 mm). It is used to connect the EP-17K80GC to the target system. The PG-1500 is a PROM programmer for the µPD17P709. Use this PROM programmer with the PA-17KDZ (adapter for the PG-1500) and PA17P709GC programmer adapter, to program the µPD17P709. The PA-17P709GC is a socket unit for the µPD17P709. It is used with the PG-1500. SE board (SE-17709) Emulation probe (EP-17K80GC) Conversion socket (EV-9200GC-80Note 3) PROM Programmer (PG-1500) Programmer adapter (PA-17P709GC) Notes 1. Low-end model, operating on an external power supply 2. The EMU-17K is a product of I.C Corporation. Contact I.C Corporation (Tokyo, 03-3733-1163) for details. 3. The EP-17K80GC is supplied together with one EV-9200GC-80. A set of five EV-9200GC-80s is also available. Remark Third-party PROM programmers are also available: For example, AF-9703, AF-9704, AF-9705, and AF9706 (manufactured by Ando Electric Co., Ltd.). These PROM programmers can be used with the PA17P709GC programmer adapter. For details, contact Ando Electric Co., Ltd. (Tokyo, 03-3733-1151). 33 µPD17P709 Software Host machine Distribution media Name 17K series assembler (AS17K) Description AS17K is an assembler applicable to the 17K series. In developing µPD17P709 programs, AS17K is used in combination with a device file (AS17704). OS Part number PC-9800 MS-DOSTM series 5.25-inch, µS5A10AS17K 2HD 3.5-inch, 2HD µS5A13AS17K IBM PC/AT PC DOSTM 5.25-inch, µS7B10AS17K 2HC 3.5-inch, 2HC µS7B13AS17K Device file (AS17704) AS17704 has a device file for the µPD17P709 . It is used together with the assembler (AS17K), which is applicable to the 17K series. PC-9800 MS-DOS series 5.25-inch, µS5A10AS17704 2HD 3.5-inch, 2HD µS5A13AS17704 IBM PC/AT PC DOS 5.25-inch, µS7B10AS17704 2HC 3.5-inch, 2HC µS7B13AS17704 Support software (SIMPLEHOST) SIMPLEHOST, running under WindowsTM, provides a man machine interface in developing programs by using a personal computer and incircuit emulator. PC-9800 MS-DOS series Windows 5.25-inch, µS5A10IE17K 2HD 3.5-inch, 2HD µS5A13IE17K IBM PC/AT PC DOS 5.25-inch, µS7B10IE17K 2HC 3.5-inch, 2HC µS7B13IE17K Remark The following table lists the versions of the operating systems described in the above table. OS MS-DOS PC DOS Windows Versions Ver. 3.30 to Ver.5.00ANote Ver. 3.1 to Ver. 5.0Note Ver. 3.0 to Ver. 3.1 Note MS-DOS versions 5.00 and 5.00A and PC DOS Ver. 5.0 are provided with a task swap function. in these software packages. This function, however, cannot be used 34 µPD17P709 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 35 µPD17P709 [MEMO] Caution This product contains an I2C bus interface circuit. When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can guarantee the following only when the customer informs NEC of the use of the interface: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 36 µPD17P709 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • • • • • Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements • In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 37 µPD17P709 SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5