UPD23C16300GZ-XXX-MJH

DATA SHEET MOS INTEGRATED CIRCUIT µPD23C16300 16M-BIT MASK-PROGRAMMABLE ROM 2M-WORD BY 8-BIT (BYTE MODE) / 1M-WORD BY 16-BIT (WORD MODE) Description The µPD23C16300 is a 16,777,216 bits mask-programmable ROM. The word organization is selectable (BYTE mode : 2,097,152 words by 8 bits, WORD mode : 1,048,576 words by 16 bits). The active levels of OE (Output Enable Input) can be selected with mask-option. The µPD23C16300 is packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA. Features • Pin compatible with NOR Flash Memory • W ord organization 2,097,152 words by 8 bits (BYTE mode) 1,048,576 words by 16 bits (WORD mode) • Operating supply voltage : VCC = 2.7 V to 3.6 V Operating supply voltage VCC 3.0 V ± 0.3 V 3.3 V ± 0.3 V Access time ns (MAX.) 90 85 Power supply current (Active mode) mA (MAX.) 30 Standby current (CMOS level input) µA (MAX.) 30 Ordering Information Part Number Package 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) 48-pin TAPE FBGA (8 x 6) µPD23C16300GZ-xxx-MJH µPD23C16300F9-xxx-BC3 (xxx : ROM code suffix No.) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M15705EJ2V0DS00 (2nd edition) Date Published February 2003 NS CP(K) Printed in Japan The mark shows major revised points. 2001 µPD23C16300 Pin Configurations /xxx indicates active low signal. 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) [ µPD23C16300GZ-xxx-MJH ] Marking Side A15 A14 A13 A12 A11 A10 A9 A8 A19 NC NC NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 WORD, /BYTE GND O15, A−1 O7 O14 O6 O13 O5 O12 O4 VCC O11 O3 O10 O2 O9 O1 O8 O0 /OE or OE or DC GND /CE A0 A0 to A19 : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE /CE /OE or OE VCC GND NC DC Note : Mode select : Chip Enable : Output Enable : Supply voltage : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the 1-pin index mark. 2 Data Sheet M15705EJ2V0DS µPD23C16300 48-pin TAPE FBGA (8 x 6) [ µPD23C16300F9-xxx-BC3 ] Top View Bottom View 6 5 4 3 2 1 A B C D E F G H H G F E D C B A A 6 A13 B A12 C A14 D A15 E A16 F WORD, /BYTE G O15, A–1 O13 VCC O11 O9 /OE or OE H GND 6 H GND G O15, A–1 F WORD, /BYTE O14 O12 O10 O8 /CE E A16 D A15 C A14 B A12 A A13 5 4 3 2 1 A9 NC NC A7 A3 A8 NC NC A17 A4 A10 NC A18 A6 A2 A11 A19 NC A5 A1 O7 O5 O2 O0 A0 O14 O12 O10 O8 /CE O6 O4 O3 O1 GND 5 4 3 2 1 O6 O4 O3 O1 GND O13 VCC O11 O9 /OE or OE O7 O5 O2 O0 A0 A11 A19 NC A5 A1 A10 NC A18 A6 A2 A8 NC NC A17 A4 A9 NC NC A7 A3 A0 to A19 : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE /CE /OE or OE VCC GND NC DC Note : Mode select : Chip Enable : Output Enable : Supply voltage : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the index mark. Data Sheet M15705EJ2V0DS 3 µPD23C16300 Input / Output Pin Functions Pin name WORD, /BYTE Input / Output Input Function The pin for switching WORD mode and BYTE mode. High level : WORD mode (1M-word by 16-bit) Low level : BYTE mode (2M-word by 8-bit) A0 to A19 (Address inputs) Input Address input pins. A0 to A19 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) A0 to A19 are used as 20 bits address signals. BYTE mode (2M-word by 8-bit) A0 to A19 are used as the upper 20 bits of total 21 bits of address signal. (The least significant bit (A−1) is combined to O15.) O0 to O7, O8 to O14 (Data outputs) Output Data output pins. O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) The lower 15 bits of 16 bits data outputs to O0 to O14. (The most significant bit (O15) combined to A−1.) BYTE mode (2M-word by 8-bit) 8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance. O15, A−1 (Data output 15, LSB Address input) Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) The most significant output data bus (O15). BYTE mode (2M-word by 8-bit) The least significant address bus (A−1). /CE (Chip Enable) Input Chip activating signal. When the OE is active, output states are following. High level : High-Z Low level : Data out /OE or OE or DC (Output Enable, Don't care) VCC GND NC − − − Input Output enable signal. The active level of OE is mask option. The active level of OE can be selected from high active, low active and Don’t care at order. Supply voltage Ground Not internally connected. (The signal can be connected.) 4 Data Sheet M15705EJ2V0DS µPD23C16300 Block Diagram O8 O0 O1 O9 O2 O10 O11 O3 O12 O4 O5 O13 O6 O14 O15, A 1 O7 A0 A1 A2 A3 A4 A5 A6 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 Address Input Buffer Y-Decoder Output Buffer Logic/Input WORD, /BYTE /OE or OE or DC Y-Selector A7 Memory Cell Matrix X-Decoder Input Buffer 1,048,576 words by 16 bits / 2,097,152 words by 8 bits /CE Data Sheet M15705EJ2V0DS 5 µPD23C16300 Mask Option The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected from among " 0 " " 1 " " x " shown in the table below. Option 0 1 x /OE or OE or DC /OE OE DC OE active level L H Don’t care Operation modes for each option are shown in the tables below. Operation mode (Option : 0) /CE L /OE L H H H or L Standby Mode Active Output state Data out High-Z High-Z Operation mode (Option : 1) /CE L OE L H H H or L Standby Mode Active Output state High-Z Data out High-Z Operation mode (Option : x) /CE L H DC H or L H or L Mode Active Standby Output state Data out High-Z Remark L : Low level input H : High level input 6 Data Sheet M15705EJ2V0DS µPD23C16300 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VCC VI VO TA Tstg Condition Rating –0.3 to +4.6 –0.3 to VCC+0.3 –0.3 to VCC+0.3 –10 to +70 –65 to +150 Unit V V V °C °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (TA = 25 °C) Parameter Input capacitance Output capacitance Symbol CI CO f = 1 MHz Test condition MIN. TYP. MAX. 10 12 Unit pF pF DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter High level input voltage Low level input voltage Symbol VIH VIL VCC = 3.0 V ± 0.3 V VCC = 3.3 V ± 0.3 V High level output voltage Low level output voltage Input leakage current Output leakage current Power supply current Standby current VOH VOL ILI ILO ICC1 ICC3 IOH = –100 µA IOL = 2.1 mA VI = 0 V to VCC VO = 0 V to VCC, Chip deselected /CE = VIL (Active mode), IO = 0 mA /CE = VCC – 0.2 V (Standby mode) –10 –10 Test conditions MIN. 2.0 –0.3 –0.3 2.4 0.4 +10 +10 30 30 TYP. MAX. VCC + 0.3 +0.5 +0.8 V V Unit V V µA µA mA µA Data Sheet M15705EJ2V0DS 7 µPD23C16300 AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V MIN. Address access time Address skew time Chip enable access time Output enable access time Output hold time Output disable time WORD, /BYTE access time tACC tSKEW tCE tOE tOH tDF tWB 0 0 25 90 Note TYP. MAX. 90 10 90 25 0 0 25 85 VCC = 3.3 V ± 0.3 V MIN. TYP. MAX. 85 10 85 25 ns ns ns ns ns ns ns Unit Note tSKEW indicates the following three types of time depending on the condition. 1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the next address is determined. 2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the /CE high level input point. 3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is switched from high level to low level following address determination, or when the address is changed after /CE is switched from low level to high level. Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. AC Test Conditions Input waveform (Rise / Fall time ≤ 5 ns) 1.4 V Test points 1.4 V Output waveform 1.4 V Test points 1.4 V Output load 1TTL + 100 pF 8 Data Sheet M15705EJ2V0DS µPD23C16300 Cautions on power application To ensure normal operation, always apply power using /CE following the procedure shown below. 1) Input a high level to /CE during and after power application. 2) Hold the high level input to /CE for 200 ns or longer (wait time). 3) Start normal operation after the wait time has elapsed. Power Application Timing Chart 1 (When /CE is made high at power application) Wait time /CE (Input) 200 ns or longer Normal operation VCC Power Application Timing Chart 2 (When /CE is made high after power application) Wait time /CE (Input) 200 ns or longer Normal operation VCC Caution Other signals can be either high or low during the wait time. Data Sheet M15705EJ2V0DS 9 µPD23C16300 Read Cycle Timing Chart tSKEW A0 to A19, (Input) A−1 Note1 tACC tACC tSKEW tSKEW tACC /CE (Input) tCE tDF Note2 tDF Note2 /OE or OE (Input) tOE O0 to O7, (Input) O8 to O15 Note3 High-Z tOH High-Z tOH tOH Data out Data out Data out Notes 1. During WORD mode, A–1 is O15. 2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. 3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1. WORD, /BYTE Switch Timing Chart A–1 (Input) High-Z High-Z WORD, /BYTE (Input) tOH tACC tOH tWB O0 to O7 (Output) Data Out Data Out Data Out tDF High-Z O8 to O15 (Output) Data Out Data Out Remark Chip Enable (/CE) and Output Enable (/OE or OE) : Active. 10 Data Sheet M15705EJ2V0DS µPD23C16300 Package Drawings 48-PIN PLASTIC TSOP (I) (12x20) detail of lead end 1 48 F G R Q 24 25 E P I J A L S S K N S C B D MM NOTES 1) Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2) "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) ITEM A B C D E F G I J K L M N P Q R S MILLIMETERS 12.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 1.0 ± 0.05 18.4 ± 0.1 0.8 ± 0.2 0.145 ± 0.05 0.5 0.10 0.10 20.0 ± 0.2 3 °+ 5 ° −3° 0.25 0.60 ± 0.15 S48GZ-50-MJH-1 Data Sheet M15705EJ2V0DS 11 µPD23C16300 48-PIN TAPE FBGA(8x6) wSB ZD ZE B E A D 6 5 4 3 2 1 HGFEDCBA INDEX MARK wSA INDEX MARK A y1 S A2 S y S e A1 M φb φx S AB ITEM D E w e A A1 A2 b x y y1 ZD ZE MILLIMETERS 6.0 ± 0.1 8.0 ± 0.1 0.2 0.80 0.97 ± 0.10 0.27 ± 0.05 0.70 0.45 ± 0.05 0.08 0.1 0.2 1.00 1.20 P48F9-80-BC3 12 Data Sheet M15705EJ2V0DS µPD23C16300 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD23C16300. Types of Surface Mount Device µPD23C16300GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) µPD23C16300F9-BC3 : 48-pin TAPE FBGA (8 x 6) Data Sheet M15705EJ2V0DS 13 µPD23C16300 Revision History Edition/ Date This edition Page Previous edition Preliminary Data Sheet → Data Sheet AC Characteristics Address skew time (tSKEW ) Note p.9 p.10 p.12 – p.9 p.11 Addition Modification Modification Package Drawings Cautions on power application Read Cycle Timing Chart Preliminary version → Standard version Type of revision Location Description (Previous edition → This edition) 2nd edition/ Throughout Throughout Modification Feb. 2003 p.8 p.8 Addition 14 Data Sheet M15705EJ2V0DS µPD23C16300 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS FOR CMOS Note: Input levels of CMOS devices must be fixed. CMOS devices behave differently than Bipolar or NMOS devices. If the input of a CMOS device stays in an area that is between V IL ( MAX.) and V IH ( MIN.) due to the effects of noise or some other irregularity, malfunction may result. Therefore, not only the input waveform is fixed, but also the waveform changes, it is important to use the CMOS device under AC test conditions. For unused input pins in particular, CMOS devices should not be operated in a state where nothing is connected, so input levels of CMOS devices must be fixed to high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M15705EJ2V0DS 15 µPD23C16300 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of February, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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