UPD2845GR-E2

DATA SHEET DATA SHEET CMOS DIGITAL INTEGRATED CIRCUITS PPD2845GR 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM DESCRIPTION PPD2845GR is a PLL synthesizer LSI for pager system. This LSI is manufactured using low voltage CMOS process and therefore realized the low power consumption PLL operated on 1 V, 1.3 mA. This LSI is packaged in 16 pin plastic SSOP suitable for high-density surface mounting. So, this product contributes to produce a long-lifebattery and physically-small pager system. FEATURES • Operating frequency : · Input frequency : fin = 10 MHz to 94 MHz · Reference oscillating frequency : fx’tal = 12.8 MHz • Low Supply voltage : · PLL block : V DD1 = 1.00 V to 1.15 V @ fin = 10 MHz to 70 MHz VDD1 = 1.05 V to 1.15 V @ fin = 10 MHz to 94 MHz · Charge pump block: VDD2 = 3.0 V ± 300 mV • Low power consumption • IDD = 1.3 mA TYP. @ fin = 70 MHz, fx’tal = 12.8 MHz • Equipped with power-save function • Serial data can be received in power-save mode. • Packaged in 16 pin plastic SSOP suitable for high-density surface mounting. ORDERING INFORMATION PART NUMBER PACKAGE 16 pin plastic SSOP (225 mil) 16 pin plastic SSOP (225 mil) SUPPLYING FORM Embossed tape 12 mm wide. QTY 2.5 k/reel Pin 1 is in tape pull-out direction. Embossed tape 12 mm wide. QTY 2.5 k/reel Pin 1 is in tape roll-in direction. PPD2845GR-E1 PPD2845GR-E2 * To order evaluation samples, please contact your local NEC sales office (Order number : PPD2845GR). PIN ASSIGNMENT (Top View) VDD1 FIN GND FR RESET EO EOP EON XI XO LE CLK DATA PS NC VDD2 Caution Electro-static sensitive devices Document No. P12150EJ2V0DS00 (2nd edition) (Previous No. IC-3291) Date Published February 1997 N Pi di J © 1994 PPD2845GR INTERNAL BLOCK DIAGRAM XI XO LE CLK DATA PS NC VDD2 16 15 14 13 12 gate FR 11 10 9 IN AMP 1/2 PRESCALER DATA CLK LE 5 BIT reference divider 13 BIT latch 13 BIT Shift register 23 BIT latch 18 BIT 32/33 PRESCALER gate FV divider 13 BIT timer Phase comparator Phase detector error out Pch open drain Nch open drain TEST CIRCUIT 1 2 3 4 5 6 7 8 VDD1 FIN GND FR RESET EO EOP EON 2 PPD2845GR PIN EXPLANATION PIN No. 1 2 3 4 PIN NAME VDD1 FIN GND FR I/O • I • O EXPLANATION FOR FUNCTION Supply voltage to PLL block Frequency Input Ground Test pin for monitor. Normally used as PLL, output L should be selected by test bit and this pin should be opened. (Refer to setting for reference counter on 11 page) Test pin for monitor reset. (Refer to RESET on 12 page) Normally used as PLL, this pin should be grounded. Internal charge pump output. In the case of passive filter, this output should be used. Input signal phase fp vs. reference signal fr fp > fr : Low output fp < fr : High output fp = fr : High-impedance Outputs for external charge pump. In the case of active filter, this outputs should be used. EOP : PCH open drain EON : NCH open drain EON EOP 5 RESET I 6 EO O 7 8 EOP EON O O 9 10 11 12 13 14 15 16 VDD2 NC PS DATA CLK LE XO XI • • I I I I O I Supply voltage to charge pump. Non Connection. Control bias input for power-save (Refer to Power-save on 12 page). Data input for divided ratio. Clock input for shift register. Latch enable input. X’tal oscillator connection pin. 3 PPD2845GR ABSOLUTE MAXIMUM RATINGS (UNLESS OTHERWISE SPECIFIED, T A = +25 °C) Supply Voltage Input Voltage Output Voltage Output Current Operating Ambient Temperature Storage Temperature VDD1 VDD2 VI1 VI2 VO1 VO2 IO TA Tstg ð0.3 to 2.0 ð0.3 to 6.0 ð0.3 to VDD1 +0.3 (Except for DATA, CLK, LE, PS pin) ð0.3 to 6.0 (DATA, CLK, LE, PS) ð0.3 to VDD1 +0.3 (XO, FR) ð0.3 to VDD2 +0.3 (EO, EOP, EON) 10 ð10 to +50 ð55 to +125 V V V V V V mA °C °C RECOMMENDED OPERATING RANGE PARAMETER Supply Voltage VDD2 Operating Ambient Temperature TA 2.85 ð10 3.0 +25 3.15 +50 V °C SYMBOL VDD1 MIN. 1.0 TYP. 1.05 MAX. 1.1 UNIT V 4 PPD2845GR ELECTRICAL CHARACTERISTICS DC PERFORMANCE (Unless otherwise specified, VDD1 = 1.00 V to 1.15 V, VDD2 = 2.70 to 3.30 V, TA = ð10 to +50 °C) PARAMETER Supply Voltage SYMBOL VDD1 VDD2 Circuit Current IDD1 MIN. 1.00 2.70 TYP. 1.05 3.0 1.3 MAX. 1.15 3.30 2.2 UNIT V V mA CONDITIONS PLL Operation P/D Charge pump block fin = 70 MHz, 0.2 VP-P. fx’tal = 12.8 MHz X’tal OSC IN. VDD1 = 1.0 V to 1.1 V VDD2 = 2.85 V to 3.15 V No Input Signal, VDD1 = 1.1 V EO, EOP pin. VDD2 = 2.85 V VOH = VDD2 ð0.5 V XO pin. VOH = VDD1 ð0.5 V FR pin. VOH = VDD1 ð0.5 V EO, EON pin. VDD2 = 2.85 V VOL = 0.5 V XO pin. VOL = 0.5 V FR pin. VOL = 0.5 V FIN, XI pin. VIH = VDD1 1.0 V FIN, XI pin. VIL = 0 V, VDD1 1.0 V DATA, CLK, LE, PS pin. VIH1 = 3.85 V DATA, CLK, LE, PS pin. DATA, CLK, LE, PS pin. RESET pin. RESET pin. EO, EOP, EON pin. VDD1 = 1.0 V to 1.1 V VDD2 = 2.85 V to 3.15 V Data Retain Current High Level Output Current1 High Level Output Current2 High Level Output Current3 Low Level Output Current1 Low Level Output Current2 Low Level Output Current3 High Level Input Current1 Low Level Input Current1 *2 *1 IDR IOH1 IOH2 IOH3 IOL1 IOL2 IOL3 IIH1 IIL1 IIH2 VIH1 VIL1 VIH2 VIL2 IL 0.8 u VDD1 0 0.8 u VDD1 0 ð1.0 ð0.5 ð0.1 1.0 0.4 0.4 0.4 ð0.4 1.0 10 PA mA mA mA mA mA mA *1 *1 *2 *2 *2 PA PA 1.0 4.0 0.2 u VDD1 VDD1 0.2 u VDD1 10 ð4 *1 *2 High Level Input Current2 PA V V V V High Level Input Voltage1 Low Level Input Voltage1 High Level Input Voltage2 Low Level Input Voltage2 Output Leak Current r1.0 PA *1 Current from IC *2 Current into IC AC PERFORMANCE (Unless otherwise specified, VDD1 = 1.00 V to 1.15 V, VDD2 = 2.70 to 3.30 V, TA = ð10 to +50 qC) PARAMETER Input frequency 1 Input frequency 2 Reference Oscillating Frequency SYMBOL fin1 fin2 fx’tal MIN. 10 10 12.8 TYP. MAX. 70 94 UNIT MHz MHz MHz CONDITIONS FIN pin, Vin = 0.2 VP-P FIN pin, Vin = 0.2 VP-P, VDD1 = 1.05 V to 1.15 V XI, XO pin 5 PPD2845GR TEST CIRCUIT DC measurement relay RL1 C1 16 C2 D1 14 BS3 GND 13 12 11 EOP EON NC 10 VDD2 BS1 15 X’tal BS2 2 GND 4 5 6 7 8 VDD1 FIN GND FR RESET EO XI XO LE CLK DATA PS µ PD2845GR relay RL1 Diode D1 Capacitor C1,C2 X’tal : SRR-204 : 1S945 : 18 pF : 12.8 MHz AC measurement VDD1 1µ F VDD2 100 pF VDD1 1µ F BNC1 1 000 pF GND BNC2 FR RESET SW3 EO EOP EON PS SW2 NC VDD2 LE CLK DATA 50 Ω FIN XO 10 pF XI X’tal 12.8 MHz 10 pF SW 1 µPD2845GR BNC1 BNC2 SW1 SW2 SW3 : Frequency input : Frequency output : switch for voltage on/off : Desired for PS mode : Low : Desired for reset mode : High 100 pF 6 PPD2845GR APPLICATION CIRCUIT EXAMPLES Passive filter application example (using internal charge pump) VDD1 1µF VDD2 VCO out 1µF VCO 1 000 pF GND FR RESET EO EOP EON LE CLK DATA PS NC VDD2 100 pF VDD1 FIN XI X’tal XO 10 pF 12.8 MHz controller 10 pF passive filter µPD2845GR VDD1 VDD2 X’tal : 1.0 to 1.1 V : 2.85 to 3.15 V : 12.8 MHz 100 pF Active filter application example (using external charge pump) EO FIN (2 pin) EOP VCO LPF PMOS NMOS EON 7 PPD2845GR INPUT TIMING OF SERIAL DATA DATA latch CLK read LE This logic circuit is controlled by a 3-wire serial bus interface with DATA (12 pin), CLK (13 pin) and LE (14 pin). On the control setting, Binary-coded serial data is input to DATA pin. This data is read into the shift register at the rising edge of the CLK signal input to the CLK pin. When the LE signal is at the low level, DATA CLK are received into the LSI to be latched at the rising edge of the LE signal. While the LE signal is at the high level, neither DATA nor CLK signals can be received. CAUTION At the initial VCC supplied time, serial data must be input, because the IC output is unstable on the non-data input stage. [Refer to ‘Power-save (pin 11)’ on 12 page] 8 PPD2845GR INPUT SIGNAL DIVIDER INPUT SIGNAL DIVIDER obtain the frequency: fp input to phase comparator. This circuit divides input frequency: fin to obtain fp. This block consists of prescaler, 5 bit swallow counter, 13 bit main counter and divide-ratio control circuit. Setting numbers • Main counter • Swallow counter • Prescaler Total divide ratio NT = S(P+1) + P(MðS) = PM+S = 32 M+S (M t S) ?NT = 1 024 to 262 143 Relation between fp and fin fp = fin/(32 M+S) (ex) At fp = 5 kHz fin = 70 MHz NT = 70 M/5 k = 14 000 Therefore 14 000 32 = 437 • • • 16 n M Reference Counter Reference Counter obtain the frequency: fr input to phase comparater. and prescaler of divide-by-2. Setting number • 13 bit programmable reference counter Total reference counter block divide ratio RT = 2 u R ?RT = 4 to 16 382 Relation between fr and fX’tal fr = (fX’tal/2)/R (ex) fr = 5 kHz fX’tal = 12.8 MHz R = (12.8 MHz/2)/5 kHz = 1 280 R = 2 to 8 191 This circuit divides the reference oscillating frequency: fX’tal of X’tal or TCXO to obtain fr. This block consists of 13 bit programmable reference counter n S M = 32 to 8 191 S = 0 to 31 P = 32, P+1 = 33 9 PPD2845GR Data format of shift register Foundaly constraction of shift register LE LSB MSB DATA A D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 CLK last bit first bit (1) Setting for data selection bit Data selection bit: last A bit can govern the latch selection. Data selection bit’s construction and function A 1 Function Setting for swallow and main counter’s divide ratio. Setting for charge pump output selection. Setting for reference counter’s divide ratio. 0 “0” = Low, “1” = High (2) Setting for swallow/main counter’s data and charge pump output selection Bit constraction of setting for swallow/main counter and charge pump output selection A D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 A 2 0 2 1 2 2 2 3 2 4 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 A = 1 charge no pump assigned output selection swallow counter : S (5 bits 0 to 31) main counter : M (13 bits 32 to 8 191) CAUTION D19, D20 are not assigned for setting but CLK signals must be input because of the bit construction. • SWALLOW COUNTER DATA S = (D14 u 24) + (D15 u 23) + (D16 u 22) + (D17 u 21) + (D18 u 20) • MAIN COUNTER DATA M = (D1 u 212) + (D2 u 211) + (D3 u 210) + (D4 u 29) + (D5 u 28) + (D6 u 27) + (D7 u 26) + (D8 u 25) + (D9 u 24) + (D10 u 23) + (D11 u 22) + (D12 u 21) + (D13 u 20) 10 PPD2845GR NT = 32M + S = 32 u {(D1 u 212) + (D2 u 211) + (D3 u 210) + (D4 u 29) + (D5 u 28) + (D6 u 27) + (D7 u 26) + (D8 u 25) + (D9 u 24) + (D10 u 23) + (D11 u 22) + (D12 u 21) + (D13 u 20)} + {(D14 u 24) + (D15 u 23) + (D16 u 22) + (D17 u 21) + (D18 u 20)} 17 16 15 14 13 12 11 10 9 ?NT = (D1 u 2 ) + (D2 u 2 ) + (D3 u 2 ) + (D4 u 2 ) + (D5 u 2 ) + (D6 u 2 ) + (D7 u 2 ) + (D8 u 2 ) + (D9 u 2 ) + (D10 u 28) + (D11 u 27) + (D12 u 26) + (D13 u 25) + (D14 u 24) + (D15 u 23) + (D16 u 22) + (D17 u 21) + (D18 u 20) Thus, total divide ratio of input signal divider ‘NT’ can be transferred to binary-code in order to setting data ‘D1 to D18’ input. (D1 should be top digit and D18 should be bottom digit.) • Charge pump output selection data D22 D21 EO Pin (To use internal charge pump) Hi- Impedance Hi-Impedance OUTPUT OUTPUT EOP, EO Pin (To use external charge pump) OFF OUTPUT OFF OUTPUT 0 0 1 1 0 1 0 1 “0” = Low, “1” = High (3) Setting for reference counter A D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 A 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 0 1 A=0 reference counter : R (13 bits 2 to 8 191) TEST BIT (FR pin) no assigned CAUTION D1 to D7 are not assigned for setting but CLK signals must be input because of the bit construction. RT = 2 u R 12 11 10 9 8 7 6 5 ?RT = 2 u {(D10 u 2 ) + (D11 u 2 ) + (D12 u 2 ) + (D13 u 2 ) + (D14 u 2 ) + (D15 u 2 ) + (D16 u 2 ) + (D17 u 2 ) + (D18 u 24) + (D19 u 23) + (D20 u 22) + (D21 u 21) + (D22 u 20)} *TEST BIT: for IC tester (FR pin) use or not use (PLL operation). for normally PLL operation, input D9 = 0, D8 = 1 (FR pin = output L). 11 PPD2845GR Power-save and RESET Power-save (PIN 11) Power-save-mode can be selected by input data to PS pin. H; operation mode L; power-save-mode On the power-save-mode, reference oscillator and prescaler turn off and error-outs (EO, EOP, EON) output Hiimpedance but shift register data is remained. Serial data can be received in power-save-mode. Note: Power-save usage for initial VCC supplying To prevent unstable mode at initial VCC supplying, Power-save-mode must be selected. After counter data setting, normal operation mode can be selected. RESET (PIN 5) Reset-mode can be selected by input data to RESET pin. H; reset-mode L(GND or Open); Normal operation. On the reset-mode, reference oscillator/prescalers turn off and error-outs (EO, EOP, EON) output Hi-impedance. Shift-register data is initialized. This reset-mode should be used at LSI testing, normally use as PLL, RESET pin should be opened or grounded. Supplementary explanation: When RESET pin bias is switched from H to L, initial divide ratios can be set automatically as follows • Input signal divider: NT = 10372 • 13 bit programmable reference counter: R = 1 280 (RT = 2 560) These divide ratios make PLL loop without controller on condition as follows fin = 51.86 MHz fx’tal = 12.8 MHz fp = fr = 5.0 kHz 12 PPD2845GR PHASE COMPARATOR PHASE COMPARATOR compares the phase between divided input frequency (fp) and reference frequency (fr). This circuit make the change pump output signals according to following detection. *3 To use internal charge pump (passive filter type) *4 To use external charge pump (active filter type) VCO should be used as type of ‘higher voltagehigher frequency’. detection fr > fp fr = fp fr < fp EO H *3 EOP H *4 EON *4 OFF OFF L Hi-Impedance L OFF OFF EON EO EOP EOP is Pch open drain, EON is Nch open drain. EO is output pin of internal charge pump. SYSTEM APPLICATION EXAMPLE Pager block diagram of direct conversion type LPF ∫ PLL ×5 π/2 DET DECODER DRIVER BZ µ PD2845GR CLOCK DRIVER LCD LPF ∫ 13 PPD2845GR PACKAGE DIMENSIONS 16 PIN PLASTIC SHRINK SOP (225 mil) 16 9 detail of lead end 1 A 8 P H I F G J E C N D M M B K L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 5.50 MAX. 0.475 MAX. 0.65 (T.P.) 0.20±0.10 0.125±0.075 1.8 MAX. 1.44 6.2±0.3 4.4±0.2 0.9±0.2 0.15 +0.10 –0.05 0.5±0.2 0.10 0.10 5 ° ±5 ° INCHES 0.217 MAX. 0.019 MAX. 0.026 (T.P.) 0.008±0.004 0.005±0.003 0.071 MAX. 0.057 0.244±0.012 +0.009 0.173 –0.008 0.035 +0.009 –0.008 0.006 +0.004 –0.002 0.020 +0.008 –0.009 0.004 0.004 5 ° ±5 ° P16GM-65-225B-2 14 PPD2845GR NOTE ON CORRECT USE (1) Observe precautions for handling because of electrostatic sensitive devides. (2) Form a ground pattern as wide as possible to minimize ground impedance. (3) Connect a bypass capacitor (e. g. 1 000 pF) to the VDD pin. (4) The DC cut capacitor must be each attached to FIN, XI and XO pin. (5) External R, C values of loop filter should be determined according to the VCO specification. (6) While VCO signal is not input to F IN pin, power-save-mode must be set. (7) After initially VCC, VDD are supplied, serial data should be input immediately. (Before serial data input, LSI operation is unstable or undesired.) RECOMMENDED SOLDERING CONDITIONS This product should be soldered in the following recommended conditions. Other soldering method and conditions than the recommended conditions are to be consulted with our sales representatives. PPD2845GR Soldering process Infrared ray reflow Soldering conditions Peak package’s surface temperature: 235 °C or below, Reflow time: 30 seconds or below (210 °C or higher), Number of reflow process: 2, Exposure limit*: None Peak package’s surface temperature: 215 °C or below, Reflow time: 40 seconds or below (200 °C or higher), Number of reflow process: 2, Exposure limit*: None Terminal temperature: 300 °C or below, Flow time: 3 seconds or below, Exposure limit*: None Symbol IR35-00-2 VPS VP15-00-2 Partial heating method *: Exposure limit before soldering after dry-package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Note Apply only a single process at once, except for “Partial heating method”. For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 15 PPD2845GR No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5