DATA SHEET
µPD30500, 30500A, 30500B
VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR
MOS INTEGRATED CIRCUIT
DESCRIPTION
The µPD30500 (VR5000), µPD30500A (VR5000A), and µPD30500BNote (VR5000B) are a high-performance, 64bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by MIPSTM Technologies Inc. The instructions of the VR5000, VR5000A, and VR5000B are compatible with those of the VR3000TM Series and VR4000TM Series and higher, and completely compatible with those of the VR10000TM. applications can be used as they are. Note Under development Therefore, present
Detailed functions are described in the following manual. Be sure to read the manual when designing your system. • VR5000, VR5000A, VR5000B User’s Manual (U11761E)
FEATURES
• Employs 64-bit MIPS-based RISC architecture • High-speed processing • 2-way super scalar 5-stage pipeline • 5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (µPD30500) 6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (µPD30500A) 8 SPECint95, 8 SPECfp95, 423 MIPS (µPD30500B) • High-speed translation buffer mechanism (TLB) (48 entries) • Address space Physical: 36 bits, Virtual: 40 bits • Floating-point unit (FPU) • Sum-of-products operation instruction supported • Primary cache memory (instruction/data: 32 Kbytes each) • Secondary cache controller • Maximum operating frequency Internal: 200 MHz (µPD30500), 250 MHz (µPD30500A), 300 MHz (µPD30500B) External: 100 MHz • Selectable external/internal multiple rate from twice to eight times • Instruction set compatible with VR3000 and VR4000 Series and higher (conforms to MIPS I, II, III, and IV) • Supply voltage: 3.3 V ±5% (µPD30500) Core: 2.5 V ±5%, I/O: 3.3 V ±5% (µPD30500A) Core: 1.8 V ±0.1 V, I/O: 3.3 V ±5% (µPD30500B) Unless otherwise specified, the VR5000 (µPD30500) is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12031EJ4V0DS00 (4th edition) Date Published May 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
1997,1999 © © MIPS Technologies Inc. 1997
µPD30500, 30500A, 30500B
APPLICATIONS
• High-performance embedded systems • Multimedia systems • Entry-class computers • Image processing systems
ORDERING INFORMATION
Part number Package 223-pin ceramic PGA (48 × 48) 223-pin ceramic PGA (48 × 48) 223-pin ceramic PGA (48 × 48) 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) Maximum operating frequency (MHz) 150 180 200 150 180 200 250 300
µPD30500RJ-150 µPD30500RJ-180 µPD30500RJ-200 µPD30500S2-150 µPD30500S2-180 µPD30500S2-200 µPD30500AS2-250 µPD30500BS2-300Note
Note Under development
MAIN DIFFERENCES BETWEEN VR5000, VR5000A, AND VR5000B
Parameter Maximum internal operating frequency Internal multiplication ratio for clock interface input Supply voltage VR5000 150/180/200 MHz 2, 3, 4, 5, 6, 7, 8 3.3 V ±5% VR5000A 250 MHz 2, 2.5Note 2, 3, 4, 5, 6, 7, 8 Core: 1.8 V ±0.1 V I/O: 3.3 V ±5% VR5000BNote 1 300 MHz
Core: 2.5 V ±5% I/O: 3.3 V ±5%
Package
• 223-pin ceramic PGA • 272-pin plastic BGA (C/D advanced type)
• 272-pin plastic BGA (C/D advanced type)
Notes 1. Under development 2. Selectable only when SysClock = 100 MHz
2
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
PIN CONFIGURATION
• 223-pin ceramic PGA (48 × 48)
µPD30500RJ-150 µPD30500RJ-180 µPD30500RJ-200
Bottom View 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VU T RPNML K J HGF EDCB A
Top View
ABCDEFGH J K LMNPRTUV Index mark
Data Sheet U12031EJ4V0DS00
3
µPD30500, 30500A, 30500B
No. A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 Name VDD GND VDD GND GND VDD GND VDD GND VDD GND VDD GND GND VDD GND GND GND GND VDD SysADC4 SysADC0 SysAD18 SysAD20 SysAD54 SysAD26 SysAD58 SysAD30 SysAD46 SysAD12 SysAD40 SysAD6 GND VDD VDD VDD VDD ValidOut NMI No. C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E15 E16 E17 Name SysADC6 SysAD16 SysAD50 SysAD22 SysAD24 SysAD28 SysAD62 SysAD44 SysAD10 SysAD38 SysAD4 SysAD34 SysAD2 GND GND Int3 Int5 Release VDD SysADC2 SysAD48 SysAD52 SysAD56 SysAD60 SysAD14 SysAD42 SysAD8 SysAD36 ColdReset SysAD0 ScTOE VDD GND Int0 Int2 Int4 SysAD32 ScDCE1 ScCWE1 No. E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 H15 H16 H17 H18 J1 J2 J3 J4 J15 J16 J17 J18 K1 K2 K3 K4 K15 K16 Name VDD VDD Reserved ScValid Int1 ScDCE0 ScCWE0 ScTDE GND GND Reserved Reserved Reserved ScCLR ScTCE Modeln VDD VDD Reserved Reserved Reserved VDDOk No. K17 K18 L1 L2 L3 L4 L15 L16 L17 L18 M1 M2 M3 M4 M15 M16 M17 M18 N1 N2 N3 N4 Name GNDP GND GND SysCmd8 SysCmd7 SysCmd5 ScLine12 ScLine14 ScLine15 VDD VDD SysCmd6 SysCmd4 SysCmd1 ScLine8 ScLine10 ScLine13 GND GND SysCmd3 SysCmd2 SysADC7 ScLine5 ScLine7 ScLine11 VDD VDD SysCmd0 SysCmdP SysADC1 ScLine2 ScLine4 ScLine9 GND VDD SysADC5 SysADC3 BigEndian SysAD49 No. R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 Name SysAD51 SysAD55 SysAD27 SysAD31 SysAD43 SysAD39 SysAD35 SysAD1 ScWord1 ScLine0 ScLine3 ScLine6 GND GND SysAD15 SysAD47 SysAD17 SysAD19 SysAD23 SysAD57 SysAD29 VDD SysAD45 SysAD41 SysAD7 SysAD5 SysAD33 Reset ScLine1 VDD VDD VDD VDD GND SysAD21 SysAD53 SysAD25 SysAD59 SysAD61 No. U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Name SysAD63 SysAD13 SysAD11 SysAD9 SysAD37 SysAD3 ScWord0 VDD GND GND GND GND VDD GND GND VDD GND VDD GND VDD GND VDD GND VDD GND GND VDD GND
ModeClock N15 SysClock GND GND WrRdy Validln ExtRqst Reserved Reserved Reserved VDD VDD ScMatch RdRdy ScDOE Reserved VDDP N16 N17 N18 P1 P2 P3 P4 P15 P16 P17 P18 R1 R2 R3 R4 R5
4
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
• 272-pin plastic BGA (C/D advanced type) (29 × 29)
µPD30500S2-150 µPD30500S2-180 µPD30500S2-200 µPD30500AS2-250 µPD30500BS2-300Note
Bottom View 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AA Y W V U T R P N M L K J H G F E D C B A
Top View
A B C D E F G H J K L M N P R T U V W Y AA
Note
Under development
Data Sheet U12031EJ4V0DS00
5
µPD30500, 30500A, 30500B
(1) µPD30500
No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 C1 C2 C3 C4 Name GND VDD GND SysAD32 GND ScCWE1 GND VDDOk GND SysClock GND ScLine15 GND ScLine12 GND ScLine7 GND ScLine2 GND VDD GND VDD VDD VDD SysAD2 SysAD0 ScTOE ScCLR ScTDE No. C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 Name ScDCE1 ScDCE0 ScCWE0 ScTCE Modeln Reserved GNDP Reserved ScLine13 ScLine11 ScLine8 ScLine5 ScLine4 ScLine0 Reset VDD GND VDD VDD VDD GND VDD GND VDD VDD GND VDD VDDP VDD GND VDD VDD GND VDD GND VDD VDD VDD GND SysAD36 SysAD4 VDD VDD ScWord1 ScWord0 GND No. F1 F2 F3 F4 F18 F19 F20 F21 G1 G2 G3 G4 G18 G19 G20 G21 H1 H2 H3 H4 H18 H19 H20 H21 J1 J2 J3 J4 J18 J19 J20 J21 K1 K2 K3 K4 K18 K19 K20 K21 L1 L2 L3 L4 L18 L19 Name SysAD8 SysAD38 SysAD6 GND GND SysAD1 SysAD33 SysAD3 GND SysAD10 SysAD40 VDD VDD SysAD35 SysAD5 GND SysAD42 SysAD44 SysAD12 VDD VDD SysAD7 SysAD39 SysAD37 GND SysAD46 SysAD14 GND GND SysAD9 SysAD41 GND SysAD60 SysAD30 SysAD62 VDD VDD SysAD11 SysAD43 SysAD13 GND SysAD58 SysAD28 VDD VDD SysAD45 No. L20 L21 M1 M2 M3 M4 M18 M19 M20 M21 N1 N2 N3 N4 N18 N19 N20 N21 P1 P2 P3 P4 P18 P19 P20 P21 R1 R2 R3 R4 R18 R19 R20 R21 T1 T2 T3 T4 T18 T19 T20 T21 U1 U2 U3 U4 Name SysAD63 GND SysAD26 SysAD56 SysAD24 VDD VDD SysAD29 SysAD61 SysAD31 GND SysAD54 SysAD22 GND GND SysAD27 SysAD59 GND SysAD50 SysAD52 SysAD20 VDD VDD SysAD25 SysAD57 SysAD55 GND SysAD18 SysAD48 VDD VDD SysAD53 SysAD23 GND SysAD16 SysADC0 SysADC2 GND GND SysAD19 SysAD51 SysAD21 GND SysADC4 SysADC6 VDD No. U18 U19 U20 U21 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 Name VDD SysAD17 SysAD49 GND VDD VDD VDD GND NMI GND VDD VDD GND VDD VDD VDD GND VDD VDD GND VDD GND VDD VDD VDD GND VDD VDD VDD Int5 Int4 Int1 Reserved Reserved Reserved Validln ScDOE SysCmd7 SysCmd4 SysCmd1 SysADC7 SysADC5 SysAD47 BigEndian VDD GND No. Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 Name VDD VDD VDD Release Int3 Int2 ScValid Reserved Reserved Reserved ExtRqst RdRdy SysCmd8 SysCmd5 SysCmd3 SysCmd0 SysCmdP SysADC1 SysAD15 VDD VDD GND VDD GND ValidOut GND Int0 GND Reserved GND WrRdy GND ScMatch GND SysCmd6 GND SysCmd2 GND SysADC3 GND VDD GND
ModeClock D13 Reserved Reserved NC ScLine14 ScLine10 ScLine9 ScLine6 ScLine3 ScLine1 VDD VDD VDD GND VDD ColdReset SysAD34 D14 D15 D16 D17 D18 D19 D20 D21 E1 E2 E3 E4 E18 E19 E20 E21
6
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
(2) µPD30500A, 30500B
No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 C1 C2 C3 C4 Name GND VDDIO GND SysAD32 GND ScCWE1 GND VDDOk GND SysClock GND ScLine15 GND ScLine12 GND ScLine7 GND ScLine2 GND VDDIO GND VDDIO VDDIO VDDIO SysAD2 SysAD0 ScTOE ScCLR ScTDE No. C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 Name ScDCE1 ScDCE0 ScCWE0 ScTCE Modeln NC GNDP GND ScLine13 ScLine11 ScLine8 ScLine5 ScLine4 ScLine0 Reset VDDIO GND VDD VDD VDD GND VDD GND VDDIO VDD GND VDDIO VDDP VDD GND VDDIO VDD GND VDDIO GND VDD VDD VDD GND SysAD36 SysAD4 VDD VDD ScWord1 ScWord0 GND No. F1 F2 F3 F4 F18 F19 F20 F21 G1 G2 G3 G4 G18 G19 G20 G21 H1 H2 H3 H4 H18 H19 H20 H21 J1 J2 J3 J4 J18 J19 J20 J21 K1 K2 K3 K4 K18 K19 K20 K21 L1 L2 L3 L4 L18 L19 Name SysAD8 SysAD38 SysAD6 GND GND SysAD1 SysAD33 SysAD3 GND SysAD10 SysAD40 VDDIO VDDIO SysAD35 SysAD5 GND SysAD42 SysAD44 SysAD12 VDD VDD SysAD7 SysAD39 SysAD37 GND SysAD46 SysAD14 GND GND SysAD9 SysAD41 GND SysAD60 SysAD30 SysAD62 VDDIO VDDIO SysAD11 SysAD43 SysAD13 GND SysAD58 SysAD28 VDD VDD SysAD45 No. L20 L21 M1 M2 M3 M4 M18 M19 M20 M21 N1 N2 N3 N4 N18 N19 N20 N21 P1 P2 P3 P4 P18 P19 P20 P21 R1 R2 R3 R4 R18 R19 R20 R21 T1 T2 T3 T4 T18 T19 T20 T21 U1 U2 U3 U4 Name SysAD63 GND SysAD26 SysAD56 SysAD24 VDDIO VDDIO SysAD29 SysAD61 SysAD31 GND SysAD54 SysAD22 GND GND SysAD27 SysAD59 GND SysAD50 SysAD52 SysAD20 VDD VDD SysAD25 SysAD57 SysAD55 GND SysAD18 SysAD48 VDDIO VDDIO SysAD53 SysAD23 GND SysAD16 SysADC0 SysADC2 GND GND SysAD19 SysAD51 SysAD21 GND SysADC4 SysADC6 VDD No. U18 U19 U20 U21 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 Name VDD SysAD17 SysAD49 GND VDD VDD VDD GND NMI GND VDD VDDIO GND VDD VDDIO VDD GND VDDIO VDD GND VDDIO GND VDD VDD VDD GND VDDIO VDDIO VDDIO Int5 Int4 Int1 GND GND VDD Validln ScDOE SysCmd7 SysCmd4 SysCmd1 SysADC7 SysADC5 SysAD47 BigEndian VDDIO GND No. Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 Name VDDIO VDDIO VDDIO Release Int3 Int2 ScValid GND GND GND ExtRqst RdRdy SysCmd8 SysCmd5 SysCmd3 SysCmd0 SysCmdP SysADC1 SysAD15 VDDIO VDDIO GND VDDIO GND ValidOut GND Int0 GND GND GND WrRdy GND ScMatch GND SysCmd6 GND SysCmd2 GND SysADC3 GND VDDIO GND
ModeClock D13 GND GND GND ScLine14 ScLine10 ScLine9 ScLine6 ScLine3 ScLine1 VDDIO VDDIO VDDIO GND VDDIO ColdReset SysAD34 D14 D15 D16 D17 D18 D19 D20 D21 E1 E2 E3 E4 E18 E19 E20 E21
Data Sheet U12031EJ4V0DS00
7
µPD30500, 30500A, 30500B
PIN NAMES
BigEndian: ColdReset: ExtRqst: GND: GNDP: Int (0:5): ModeClock: Modeln: NC: NMI: RdRdy: Release: Reset: ScCLR: ScCWE (0:1): ScDCE (0:1): ScDOE: ScLine (0:15): ScMatch: ScTCE: ScTDE: ScTOE: ScValid: ScWord (0:1): SysAD (0:63): SysADC (0:7): SysClock: SysCmd (0:8): SysCmdP: Validln: ValidOut: VDD: VDD: VDDIO: VDDOk: VDDP: WrRdy: Endian Mode Select Cold Reset External Request Ground Quiet GND for PLL Interrupt Request Boot Mode Clock Boot Mode Data In No Connection Non-maskable Interrupt Request Read Ready Release Interface Reset Secondary Cache Block Clear Secondary Cache Write Enable Data RAM Chip Enable Data RAM Output Enable Secondary Cache Line Index Secondary Cache Tag Match Secondary Cache Tag RAM Chip Enable Secondary Cache Tag RAM Data Enable Secondary Cache Tag RAM Output Enable Secondary Cache Valid Secondary Cache Word Index System Address/Data Bus System Address/Data Check Bus System Clock System Command/Data Identifier System Command/Data Identifier Bus Parity Valid Input Valid Output Power Supply (µPD30500) Power Supply for Processor Core (µPD30500A, 30500B) Power Supply for Processor I/O (µPD30500A, 30500B only) VDD is OK Quiet VDD for PLL Write Ready
8
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
INTERNAL BLOCK DIAGRAM
Data, address
Control
SysClock
System interface
Clock generator
Instruction cache
Data cache
CP0
TLB
Instruction address
Execution unit
Floating-point unit
Pipeline control
Data Sheet U12031EJ4V0DS00
9
µPD30500, 30500A, 30500B
CONTENTS 1. 2. PIN FUNCTIONS ................................................................................................................................ 11 ELECTRICAL SPECIFICATIONS ...................................................................................................... 13
2.1 2.2 2.3 2.4 2.5
µPD30500 .................................................................................................................................................... 13 µPD30500A .................................................................................................................................................. 16 µPD30500B (Preliminary) .......................................................................................................................... 19
Test Condition ............................................................................................................................................ 22 Timing Chart ............................................................................................................................................... 22
3. 4.
PACKAGE DRAWING ........................................................................................................................ 27 RECOMMENDED SOLDERING CONDITIONS ................................................................................. 29
APPENDIX DIFFERENCES BETWEEN THE VR5000 AND VR4310TM .................................................... 30
10
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
1. PIN FUNCTIONS
Pin Name SysAD (0:63) I/O I/O Function System address/data bus. 64-bit bus for communication between processor, secondary cache and external agent. System address/data check bus. 8-bit bus including check bits for the SysAD bus. System command/data ID bus. 9-bit bus for communication of commands and data identifiers between processor and external agent. System command/data ID bus parity. 1-bit even number parity bit for the SysCmd bus. Valid in. Signal indicating that external agent has transmitted valid address or data onto SysAD bus and valid command or data identifier onto SysCmd bus. Valid out. Signal indicating that processor has transmitted valid address or data onto SysAD bus and valid command or data identifier onto SysCmd bus. External request. Signal used by external agent to request for its use by system interface. Release Output Interface release. Signal indicating that the processor has released the system interface to the slave state. Write ready. Signal indicating that the external agent can accept a processor write request. Read ready. Signal indicating that external agent can accept a processor read request. Secondary cache block clear. Clears all the valid bits of the tag RAM. Secondary cache write enable. Write enable signal for the secondary cache RAM. ScDCE (0:1) Output Data RAM chip select. Chip select signal for secondary cache RAM. Data RAM output enable. Data output enable signal from the external agent. Secondary cache line index. Cache line index output of the secondary cache. Secondary cache tag match. Tag match signal from secondary cache tag RAM. Secondary cache tag RAM chip select. Chip select signal of the secondary cache tag RAM. Secondary cache tag RAM data enable. Data enable signal from the secondary cache tag RAM. Secondary cache tag RAM output enable. Output enable signal from the secondary cache tag RAM. Secondary cache word index. Signal indicating that the double word of the secondary cache index is correct. Secondary cache valid. Signal indicating that the data of the secondary cache is valid.
SysADC (0:7)
I/O
SysCmd (0:8)
I/O
SysCmdP
I/O
ValidIn
Input
ValidOut
Output
ExtRqst
Input
WrRdy
Output
RdRdy
Input
ScCLR
Output
ScCWE (0:1)
Output
ScDOE
Input
ScLine (0:15)
Output
ScMatch
Input
ScTCE
Output
ScTDE
Output
ScTOE
Output
ScWord (0:1)
I/O
ScValid
I/O
Data Sheet U12031EJ4V0DS00
11
µPD30500, 30500A, 30500B
Pin Name Int (0:5) I/O Input Function Interrupt. General-purpose processor interrupt requests whose input statuses can be confirmed by bits 15 through 10 of cause register. Non-maskable interrupt. Interrupt request that cannot be masked. Cold reset. Signal initializing the internal status of the processor. Inactivate this signal in synchronization with SysClock. Reset. Signal generating a reset exception, without initializing the internal status of the processor. Inactivate this signal in synchronization with SysClock. System clock. Clock input signal to processor. Endian mode setting. This signal sets the endian mode of the system interface. When setting the endian mode with this signal, specify little endian with the data from the ModeIn pin that is input at reset. To set the endian mode with the data from the ModeIn pin, fix this signal to 0. BigEndian 1 1 0 0 ModeClock Output Bit 8 of boot mode 1 0 1 0 Mode — Big endian Big endian Little endian
NMI
Input
ColdReset
Input
Reset
Input
SysClock
Input
BigEndian
Input
Boot mode clock. Successive boot mode data clock output resulting from dividing SysClock by 256. Boot mode data input. Input of initialization bit stream. VDD and VDDIONote1 are valid. Signal indicating that the voltage supplied to the VR5000 is reached to the rated levelNote2 for 100 ms or more, and that that status is stabilized. When VDDOk is asserted active, the VR5000 starts an initialization sequence. PLL VDD. Power supply for internal PLL. PLL GND. Ground for internal PLL. • VR5000 Positive power supply pin (3.3 V) • VR5000A Power supply pin for core (2.5 V) • VR5000B Power supply pin for core (1.8 V) Power supply pin for I/O (3.3 V) Ground pin.
Modeln
Input
VDDOk
Input
VDDP
–
GNDP
–
VDD
–
VDDIONote1 GND
– –
Notes 1. VDDIO is only for VR5000A and VR5000B. 2. VR5000: VDD = 3.135 V VR5000A: VDD = 2.375 V, VDDIO = 3.135 V VR5000B: VDD = 1.7 V, VDDIO = 3.135 V
12
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
2. ELECTRICAL SPECIFICATIONS
2.1
µPD30500
Absolute Maximum Ratings
Parameter Supply voltage Input voltageNote Symbol VDD VI Pulse of less than 10 ns Operating case temperature TC PGA package BGA package Storage temperature Tstg PGA package BGA package Condition Rating –0.5 to +4.0 –0.5 to VDD + 0.3 –1.5 to VDD + 0.3 0 to +70 0 to +85 –65 to +150 –40 to +125 Unit V V V °C °C °C °C
Note
The upper limit of the input voltage (VDD + 0.3) is +4.0 V. Do not short circuit two or more outputs at the same time. The quality of the product may be degraded if the absolute maximum rating of even one of the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore, specify the values which if exceeded may physically damage the product. Use the product never exceeding these ratings. The specifications and conditions shown in the following DC Characteristics and AC Characteristics are the range within which the product can normally operate and the quality can be guaranteed.
Cautions 1. 2.
DC Characteristics (TC = 0 to +70°C (PGA Package), TC = 0 to +85°C (BGA Package), VDD = 3.3 V ±5%)
Parameter High-level output voltage Low-level output voltage High-level input Low-level input voltageNote 1 voltageNote 1 Symbol VOH VOL VIH VIL Pulse of less than 10 ns High-level input voltageNote 2 VIHC VILC Pulse of less than 10 ns Supply current IDD Normal operation 150 MHz 180 MHz 200 MHz Standby Input leakage current Input/output leakage current ILI ILIO –5 –5 Condition VDD = MIN., IOH = –4 mA VDD = MIN., IOL = 4 mA 2.0 –0.5 –1.5 0.8 × VDD –0.5 –1.5 MIN. 2.4 0.4 VDD + 0.3 +0.8 +0.8 VDD + 0.3 0.2 × VDD 0.2 × VDD 2.16 2.54 2.8 0.25 +5 +5 MAX. Unit V V V V V V V V A A A A
Low-level input voltageNote 2
µA µA
Notes 1. Not applied to the SysClock pin. 2. Applied to the SysClock pin only. Remark The operating supply current is almost proportional to the operating clock frequency.
Data Sheet U12031EJ4V0DS00
13
µPD30500, 30500A, 30500B
Capacitance
Parameter Input capacitance Output capacitance Symbol CIn Cout Condition MIN. MAX. 5 7 Unit pF pF
AC Characteristics (TC = 0 to +70°C (PGA Package), TC = 0 to +85°C (BGA Package), VDD = 3.3 V ±5%) Clock parameter
Parameter System clock high-level width System clock low-level width System clock frequencyNotes 1, 2 Symbol tCH tCL 150 MHz 180 MHz 200 MHz System clock cycle tCP 150 MHz 180 MHz 200 MHz System clock jitter tji System clock frequency > 66 MHz System clock frequency ≤ 66 MHz System clock rise time System clock fall time Mode clock cycle tCR tCF tMOC 256 × tCP Condition MIN. 3.0 3.0 20 20 20 13.3 11.1 10 75 90 100 50 50 50 ±125 ±250 2.0 2.0 MAX. Unit ns ns MHz MHz MHz ns ns ns ps ps ns ns ns
Notes 1. The operation of the VR5000 is guaranteed only when the PLL is operating 2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.
14
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
System Interface Parameter
Parameter Data output hold time Symbol tDM Condition Modebit (14 : 13) = 10 Modebit (14 : 13) = 11 Modebit (14 : 13) = 00 Modebit (14 : 13) = 01 Data output delay time Data input setup time Data input hold time tDO tDS tDH 1.6 0.5 MIN. 1.0 1.1 1.3 1.3 5.0 MAX. Unit ns ns ns ns ns ns ns
Boot Mode Interface Parameter
Parameter More data setup time Mode data hold time Symbol tMDS tMDH Condition MIN. tCP × 0.35 tCP × 0.35 MAX. Unit ns ns
Load Coefficient
Parameter Load coefficient Symbol CLD Condition MIN. MAX. 1.5 Unit ns/25 pF
Data Sheet U12031EJ4V0DS00
15
µPD30500, 30500A, 30500B
2.2 µPD30500A Absolute Maximum Ratings
Parameter Supply voltage Symbol VDDIO VDD Input voltageNote VI Pulse of less than 10 ns Operating case temperature Storage temperature TC Tstg Condition Rating –0.5 to +4.0 –0.3 to +3.3 –0.5 to VDDIO + 0.3 –1.5 to VDDIO + 0.3 0 to +85 –40 to +125 Unit V V V V °C °C
Note
The upper limit of the input voltage (VDDIO + 0.3) is +4.0 V. Do not short circuit two or more outputs at the same time. The quality of the product may be degraded if the absolute maximum rating of even one of the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore, specify the values which if exceeded may physically damage the product. Use the product never exceeding these ratings. The specifications and conditions shown in the following DC Characteristics and AC Characteristics are the range within which the product can normally operate and the quality can be guaranteed.
Cautions 1. 2.
DC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 2.5 V ±5%)
Parameter High-level output voltage Low-level output voltage High-level input Low-level input voltageNote 1 voltageNote 1 Symbol VOH VOL VIH VIL Pulse of less than 10 ns High-level input voltageNote 2 VIHC VILC Pulse of less than 10 ns Supply current IDD IDDIO System clock frequency = 50 MHZ System clock frequency = 67 MHZ System clock frequency = 83 MHZ System clock frequency = 100 MHZ Input leakage current Input/output leakage current ILI ILIO –5 –5 Condition VDDIO = MIN., IOH = –4 mA VDDIO = MIN., IOL = 4 mA 2.0 –0.5 –1.5 MIN. 2.4 0.4 VDDIO + 0.3 +0.8 +0.8 MAX. Unit V V V V V V V V A A A A A
0.8 × VDDIO VDDIO + 0.3 –0.5 –1.5 0.2 × VDDIO 0.2 × VDDIO 1.8 0.7 0.85 0.95 1.15 +5 +5
Low-level input voltageNote 2
µA µA
Notes 1. Not applied to the SysClock pin. 2. Applied to the SysClock pin only.
16
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
Power Application Sequence Two kinds of power sources are provided with the VR5000A. The sequence of the power application order is not fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while the other remains off.
Parameter Power application delay Symbol tDP Condition MIN. 0 MAX. 1 Unit sec
Capacitance
Parameter Input capacitance Output capacitance Symbol CIn Cout Condition MIN. MAX. 5 7 Unit pF pF
AC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 2.5 V ±5%) Clock parameter
Parameter System clock high-level width System clock low-level width System clock frequencyNotes 1, 2 tCP tji System clock frequency > 66 MHz System clock frequency ≤ 66 MHz System clock rise time System clock fall time Mode clock cycle tCR tCF tMOC 256 × tCP Symbol tCH tCL Condition MIN. 3.0 3.0 20 10 100 50 ±125 ±250 2.0 2.0 MAX. Unit ns ns MHz ns ps ps ns ns ns
System clock cycle System clock jitter
Notes 1. The operation of the VR5000A is guaranteed only when the PLL is operating 2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.
Data Sheet U12031EJ4V0DS00
17
µPD30500, 30500A, 30500B
System Interface Parameter
Parameter Data output hold time Symbol tDM Condition Modebit (14 : 13) = 10 Modebit (14 : 13) = 11 Modebit (14 : 13) = 00 Modebit (14 : 13) = 01 Data output delay time tDO PClock/SysClock division ratio = 2, 3, 4, 5, 6, 7, 8, PClock/SysClock division ratio = 2.5 Data input setup time Data input hold time tDS tDH 1.6 0.5 7.0 ns ns ns MIN. 1.3 1.4 1.5 1.5 5.0 MAX. Unit ns ns ns ns ns
Boot Mode Interface Parameter
Parameter Mode data setup time Mode data hold time Symbol tMDS tMDH Condition MIN. tCP × 0.35 tCP × 0.35 MAX. Unit ns ns
Load Coefficient
Parameter Load coefficient Symbol CLD Condition MIN. MAX. 1.5 Unit ns/25 pF
18
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
2.3 µPD30500B (Preliminary) Absolute Maximum Ratings
Parameter Supply voltage Symbol VDDIO VDD Input voltageNote VI Pulse of less than 10 ns Operating case temperature Storage temperature TC Tstg Condition Rating –0.5 to +4.0 –0.3 to +2.5 –0.5 to VDDIO + 0.3 –1.5 to VDDIO + 0.3 0 to +85 –40 to +125 Unit V V V V °C °C
Note
The upper limit of the input voltage (VDDIO + 0.3) is +4.0 V. Do not short circuit two or more outputs at the same time. The quality of the product may be degraded if the absolute maximum rating of even one of the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore, specify the values which if exceeded may physically damage the product. Use the product never exceeding these ratings. The specifications and conditions shown in the following DC Characteristics and AC Characteristics are the range within which the product can normally operate and the quality can be guaranteed.
Cautions 1. 2.
DC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 1.8 V ±0.1 V)
Parameter High-level output voltage Low-level output voltage High-level input Low-level input voltageNote 1 voltageNote 1 Symbol VOH VOL VIH VIL Pulse of less than 10 ns High-level input voltageNote 2 VIHC VILC Pulse of less than 10 ns Input leakage current Input/output leakage current ILI ILIO Condition VDDIO = MIN., IOH = –4 mA VDDIO = MIN., IOL = 4 mA 2.0 –0.5 –1.5 MIN. 2.4 0.4 VDDIO + 0.3 +0.8 +0.8 MAX. Unit V V V V V V V V
0.8 × VDDIO VDDIO + 0.3 –0.5 –1.5 –5 –5 0.2 × VDDIO 0.2 × VDDIO +5 +5
Low-level input voltageNote 2
µA µA
Notes 1. Not applied to the SysClock pin. 2. Applied to the SysClock pin only. Power Application Sequence Two kinds of power sources are provided with the VR5000B. The sequence of the power application order is not fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while the other remains off.
Parameter Power application delay Symbol tDP Condition MIN. 0 MAX. 1 Unit se
Data Sheet U12031EJ4V0DS00
19
µPD30500, 30500A, 30500B
Capacitance
Parameter Input capacitance Output capacitance Symbol CIn Cout Condition MIN. MAX. 5 7 Unit pF pF
AC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 1.8 V ±0.1 V) Clock parameter
Parameter System clock high-level width System clock low-level width System clock frequencyNotes 1, 2 tCP tji System clock frequency > 66 MHz System clock frequency ≤ 66 MHz System clock rise time System clock fall time Mode clock cycle tCR tCF tMOC 256 × tCP Symbol tCH tCL Condition MIN. 3.0 3.0 20 10 100 50 ±125 ±250 2.0 2.0 MAX. Unit ns ns MHz ns ps ps ns ns ns
System clock cycle System clock jitter
Notes 1. The operation of the VR5000B is guaranteed only when the PLL is operating 2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.
20
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
System Interface Parameter
Parameter Data output hold time Symbol tDM Condition Modebit (14 : 13) = 10 Modebit (14 : 13) = 11 Modebit (14 : 13) = 00 Modebit (14 : 13) = 01 Data output delay time Data input setup time Data input hold time tDO tDS tDH 1.6 0.5 MIN. 1.3 1.4 1.5 1.5 5.0 MAX. Unit ns ns ns ns ns ns ns
Boot Mode Interface Parameter
Parameter Mode data setup time Mode data hold time Symbol tMDS tMDH Condition MIN. tCP × 0.35 tCP × 0.35 MAX. Unit ns ns
Load Coefficient
Parameter Load coefficient Symbol CLD Condition MIN. MAX. 1.5 Unit ns/25 pF
Data Sheet U12031EJ4V0DS00
21
µPD30500, 30500A, 30500B
2.4 Test Condition Test point
SysClock
50%
tDO tDM All output pins 50%
Load Conditions
All output pins
DUT CL = 50 pF
2.5 Timing Chart Clock timing
tCP
tCH
80% SysClock 50% 20%
tCL
tCR
tCF
22
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
Mode clock timing
tMOC
ModeClock
50%
Clock jitter
tji
tji
SysClock
50%
System interface edge timing
SysClock tDO tDH tDM SysAD (0 : 63), SysADC (0 : 7), SysCmd (0 : 8), SysCmdP, ScLine (0 : 15), ScWord (0 : 1), ScTCE, ScValid Output Output tDS Input
tDO tDM ValidOut, Release, ScCLR, ScCWE (0 : 1), ScDCE (0 : 1), ScTDE, ScTOE Output Output
tDS tDH ValidIn, ExtRqst, RdRdy, WrRdy, ScDOE, ScMatch, Int (0 : 5), NMI Input
Data Sheet U12031EJ4V0DS00
23
µPD30500, 30500A, 30500B
Boot mode interface edge timing
ModeClock
tMDS tMDH ModeIn Input
Clocking relations
Cycle
1
2
3
4
SysClock (Input)
PClock (Output) tDO tDM SysAD Driven (Output) Data Data Data Data
SysAD Received (Input) tDS
Data
Data
Data
Data
tDH
Power application sequence (VR5000A, VR5000B only)
tDP
tDP
VDD
0.5VDD
VDDIO
0.5VDDIO
24
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
Reset Timing Power-on reset timing
VDD
Note 1
VDDI/ONote 2
3.135 V
SysClock ≥ 100 ms ≥ 64 K SysClock 256 SysClock
VDDOk
ModeClock tMDS ModeIn bit0 tMDH bit1 bit255 tDS ColdReset
Undefined
tDS Reset
≥ 64 SysClock
Notes 1. 3.135 V (VR5000), 2.375 V (VR5000A), 1.7 V (VR5000B) 2. VR5000A, VR5000B only
Cold reset timing
VDD
H
VDDIONote
H
SysClock ≥ 64 SysClock VDDOk 256 SysClock ≥ 64 K SysClock
ModeClock tMDS ModeIn bit0 tMDH bit1 bit255 tDS ColdReset
Undefined
≥ 64 SysClock tDS
Reset
Note
VR5000A, VR5000B only
Data Sheet U12031EJ4V0DS00
25
µPD30500, 30500A, 30500B
Warm reset timing
VDD
H
VDDIONote
H
SysClock ≥ 64 SysClock VDDOk H
ColdReset
H tDS tDS
Reset
Note
VR5000A, VR5000B only
26
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
3. PACKAGE DRAWING
223 PIN CERAMIC PGA
A
< Bottom View >
D
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 T S RQP NM L K J HG F E DC B A
Index Mark
J I
K L H G
F
E
φM
M
NOTE Each lead centerline is located within φ 0.254(φ 0.010 inch) of its true position (T.P.) at maximum material condition.
ITEM A D E F G H
MILLIMETERS 47.24 ± 0.25 47.24 ± 0.25 2.03 2.54(T.P.) 3.30 ± 0.2 0.50 MIN.
INCHES 1.860 ± 0.010
1.860 ± 0.010 0.080 0.100(T.P.) 0.130 ± 0.008 0.019 MIN. 0.111 0.157 MAX. 0.050 ± 0.008
φ 0.018 ± 0.002
I
J K L
2.82
3.98 MAX.
φ 1.27 ± 0.2 φ 0.46 ± 0.05
M
0.254
0.010
X223RJ-100A-1
Data Sheet U12031EJ4V0DS00
27
µPD30500, 30500A, 30500B
272-PIN PLASTIC BGA (C/D advanced type) (29x29)
B
A
A
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AA Y W V U T R P N M L K J H G F E D C B A
D
Index area Y
Z J H G
detail of A part
S
A K L S
M M
F
E
φM φP
SAB S
N
ITEM A D E F G H J K L M N P Y Z
MILLIMETERS 29.00 ± 0.20 29.00 ± 0.20 1.80 1.27 (T.P.) 0.60 ± 0.10 0.90 1.50 ± 0.20 0.15 φ 0.75 ± 0.15 0.30 0.25 MIN. 0.10 C1.5 C0.5 S272S2-127-C6-3
28
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
4. RECOMMENDED SOLDERING CONDITIONS
Soldering this product under the following soldering conditions is recommended. For the details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and recommended other than those recommended, consult NEC. (1) Soldering Conditions of Surface Mount Type
µPD30500S2-150: µPD30500S2-180: µPD30500S2-200: µPD30500AS2-250: µPD30500BS2-300Note 1:
272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29)
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Time: 30 sec max. (210°C min.), Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is necessary at 125°C for 10 hours) Package peak temperature: 215°C, Time: 25 to 40 sec max. (200°C min.), Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is necessary at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 sec max. (per device side)
Recommended Conditions Symbol IR35-103-3
VPS
VP15-103-3
Partial heating
—
Notes 1. Under development 2. Number of days in storage after the dry pack has been opened. The storage conditions are at 25°C, 65% RH MAX. Caution Do not use two or more soldering methods in combination (except partial heating). (2) Soldering Conditions of Insertion Type
µPD30500RJ-150: 223-pin ceramic PGA (48 × 48) µPD30500RJ-180: 223-pin ceramic PGA (48 × 48) µPD30500RJ-200: 223-pin ceramic PGA (48 × 48)
Soldering Method Wave soldering (Pin only) Partial heating Soldering Conditions Solder bath temperature: 260°C max., Time: 10 sec max. Pin temperature: 300°C max., Time: 3 sec max. (per pin)
Caution Wave soldering is only for the lead part in order that jet solder cannot contact with the chip directly.
Data Sheet U12031EJ4V0DS00
29
µPD30500, 30500A, 30500B
APPENDIX DIFFERENCES BETWEEN THE VR5000 AND VR4310TM
Item Operating frequency Internal External Pipeline VR5000 200 MHz MAX. 100 MHz MAX. 2-way super scalar 5-stage pipeline Primary instruction cache Primary data cache Secondary cache interface Data protection System bus Write data transfer rate 32 Kbytes 32 Kbytes Provided Byte parity 9 types (DDDD/DDxDDx/ DDxxDDxx/DxDxDxDx/ DDxxxDDxxx/DDxxxxDDxxxx/ DxxDxxDxxDxx/ DDxxxxxxDDxxxxxx/DxxxDxxx) ModeIn (dedicated serial pin) Access ends VR4310 167 MHz MAX. 83.3 MHz MAX. 5-stage pipeline
Cache
16 Kbytes 8 Kbytes None None 2 types (D/Dxx)
Initialization pin at reset Status after last data write
DivMode (0:2) Last data retained when transfer rate is set MIPS I, II, III instruction sets Provided Provided 1.5, 2, 2.5, 3, 4, 5, 6
Integer operation unit JTAG interface SyncOut-SyncIn bus Clock interface
Corresponding instruction
MIPS I, II, III, IV instruction sets None None
Multiplication ratio of input to internal Division ratio of internal to bus Clock output
2, 3, 4, 5, 6, 7, 8
2, 3, 4, 5, 6, 7, 8
1.5, 2, 2.5, 3, 4, 5, 6
None Standby mode (pipline does not operate)
TClock Not provided
Power management mode
PRId register
Imp = 0x23
Imp = 0x0B
30
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
[MEMO]
Data Sheet U12031EJ4V0DS00
31
µPD30500, 30500A, 30500B
[MEMO]
32
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
[MEMO]
Data Sheet U12031EJ4V0DS00
33
µPD30500, 30500A, 30500B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Note that this document is not designated as ‘preliminary’, while some of the related documents are preliminary versions. V R3000, V R 4000, V R4310, V R5000, V R 5000A, V R5000B, V R10000, and V R S eries are trademarks of NEC Corporation. MIPS is a trademark of MIPS Technologies Inc.
34
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12031EJ4V0DS00
35
µPD30500, 30500A, 30500B
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
• The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8
工商网监
湘ICP备2023018690号
