UPD30550

DATA SHEET PRELIMINARY PRODUCT INFORMATION DATA SHEET MOS INTEGRATED CIRCUIT µPD30550 VR5500TM 64-/32-BIT MICROPROCESSOR DESCRIPTION The µPD30550 (VR5500) is a member of the VR SeriesTM of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPSTM. The VR5500 allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using protocols compatible with the VR5000 SeriesTM and VR5432TM. Detailed function descriptions are provided in the • VR5500 User’s Manual (U16044E) user’s manual. Be sure to read the manual before designing. FEATURES • MIPS 64-bit RISC architecture • High-speed operation processing • Two-way superscaler super pipeline • 300 MHz product: 400 MHz product: (48 entries) • Address space • Physical: • Virtual: 36 bits (64-bit bus selected) 32 bits (32-bit bus selected) 40 bits (in 64-bit mode) 31 bits (in 32-bit mode) • On-chip floating-point unit (FPU) • Supports sum-of-products instructions • On-chip primary cache memory (instruction/data: 32 KB each) • 2-way set associative • Supports line lock feature 603 MIPS 804 MIPS • 64-/32-bit address/data multiplexed bus • Bus width selectable during reset • Bus protocol compatibility with existing products retained • Maximum operating frequency • 300 MHz product: Internal 300 MHz, external 133 MHz 400 MHz product: Internal 400 MHz, external 133 MHz • External/internal multiplication factor selectable from ×2 to ×5.5 by increments of .5 • Conforms to MIPS I, II, III, IV and MIPS64 instruction sets. Instruction set extensions supported include product-sum operation instruction, rotate instruction, register scan instruction, and instruction for low power mode. • Hardware debug functions supported are N-Wire and JTAG. • Supply voltage Core block: I/O block: 1.5 V ±5% (300 MHz product) 1.6 to 1.7 V (400 MHz product) 3.3 V ±5%, 2.5 V ±5% • High-speed translation lookaside buffer (TLB) The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15700EJ1V0DS01 (2nd edition) Date Published September 2002 N CP(K) Printed in USA © 2002 2001 µPD30550 APPLICATIONS • Set-topboxes • RAID • High-end embedded devices, etc. ORDERING INFORMATION Part Number Package 272-pin plastic BGA (C/D advanced type) (29 × 29) 272-pin plastic BGA (C/D advanced type) (29 × 29) Maximum Operating Frequency (MHz) 300 400 µPD30550F2-300-NN1 µPD30550F2-400-NN1 PIN CONFIGURATION • 272-pin plastic BGA (C/D advanced type) (29 × 29) µPD30550F2-300-NN1 µPD30550F2-400-NN1 Bottom view 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AA Y W V U T R P N M L K J H G F E D C B A Top view A B C D E F G H J K L M N P R T U V W Y AA 2 Data Sheet U15700EJ1V0DS µPD30550 (1/2) No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 VSS VSS VDDIO VDDIO Reset# PReq# ValidIn# ValidOut# VSS SysADC7 SysADC3 SysADC1 SysADC4 SysAD62 SysAD30 SysAD28 SysAD59 VDDIO VDDIO VSS VSS VSS VSS VDDIO VDDIO ColdReset# Release# ExtRqst# BusMode SysID2 VDD SysADC6 VSS SysADC0 VDD SysAD61 VSS Pin Name No. B17 B18 B19 B20 B21 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Pin Name SysAD27 VDDIO VDDIO VSS VSS VDDIO VDDIO VSS VSS VSS VDD WrRdy# VSS SysID1 VDD SysADC2 VSS SysAD63 VDD SysAD29 VSS SysAD58 VDDIO VSS VDDIO VDDIO VDDIO VDDIO VSS VSS IC VDD RdRdy# VSS SysID0 VDD SysADC5 No. D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 E1 E2 E3 E4 E18 E19 E20 E21 F1 F2 F3 F4 F18 F19 F20 F21 G1 G2 G3 G4 G18 G19 G20 G21 H1 H2 H3 VSS SysAD31 VDD SysAD60 VSS SysAD26 VSS VSS VDDIO VDDIO SysCmd0 DisDValidO# DWBTrans# O3Return# SysAD57 SysAD25 SysAD56 SysAD24 SysCmd1 VSS VSS VSS VDD VDD VDD SysAD55 SysCmd2 SysCmd3 SysCmd4 SysCmd5 SysAD23 SysAD54 SysAD22 SysAD53 SysCmd6 VDD VDD Pin Name No. H4 H18 H19 H20 H21 J1 J2 J3 J4 J18 J19 J20 J21 K1 K2 K3 K4 K18 K19 K20 K21 L1 L2 L3 L4 L18 L19 L20 L21 M1 M2 M3 M4 M18 M19 M20 M21 VDD VSS VSS VSS SysAD21 SysCmd7 SysCmd8 TIntSel Int0# SysAD52 SysAD20 SysAD51 SysAD19 Int1# VSS VSS VSS VDD VDD VDD VDD Int2# Int3# Int4# Int5# SysAD17 SysAD49 SysAD18 SysAD50 RMode#/BKTGIO# VDD VDD VDD VSS VSS VSS VSS Pin Name Caution Leave the IC pin open. Remark # indicates active low. Data Sheet U15700EJ1V0DS 3 µPD30550 (2/2) No. N1 N2 N3 N4 N18 N19 N20 N21 P1 P2 P3 P4 P18 P19 P20 P21 R1 R2 R3 R4 R18 R19 R20 R21 T1 T2 T3 T4 T18 T19 T20 Pin Name VDDIO NMI# VDDIO BigEndian SysAD15 SysAD47 SysAD16 SysAD48 VSS VSS VSS VSS VDD VDD VDD SysAD46 DivMode0 DivMode1 DivMode2 VDDIO SysAD44 SysAD13 SysAD45 SysAD14 VDD VDD VDD VDD VSS VSS VSS No. T21 U1 U2 U3 U4 U18 U19 U20 U21 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 W1 Pin Name SysAD12 NTrcClk NTrcData0 NTrcData1 NTrcData3 SysAD10 SysAD42 SysAD11 SysAD43 NTrcData2 NTrcEnd VSS VSS VSSPA2 VSS VDDIO VDD JTMS VSS SysAD33 VDD SysAD4 VSS SysAD7 VDD SysAD41 VSS VSS VDDIO VDDIO VDDIO No. W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Pin Name VDDIO VSS VSS VDDPA2 VSS VDDIO VDD JTDI VSS SysAD1 VDD SysAD35 VSS SysAD38 VDD SysAD9 VSS VSS VDDIO VDDIO VSS VSS VDDIO VDDIO VSSPA1 SysClock JTRST# VDD JTCK VSS SysAD32 No. Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 VDD SysAD3 VSS SysAD37 SysAD39 SysAD40 VDDIO VDDIO VSS VSS VSS VSS VDDIO VDDIO VDDPA1 VDDIO IC JTDO DrvCon VSS SysAD0 SysAD2 SysAD34 SysAD36 SysAD5 SysAD6 SysAD8 VDDIO VDDIO VSS VSS Pin Name Caution Leave the IC pin open. Remarks 1. # indicates active low. 4 Data Sheet U15700EJ1V0DS µPD30550 PIN NAMES BigEndian: BKTGIO#: BusMode: ColdReset#: DisDValidO#: DivMode(2:0): DrvCon: DWBTrans#: ExtRqst#: IC Int(5:0)#: JTCK: JTDI: JTDO: JTMS: JTRST#: NMI#: NTrcClk: NTrcData(3:0) : NTrcEnd: O3Return#: Remark Big endian Break/trigger input/output Bus mode Cold reset Disable delay ValidOut# Divide mode Driver control Doubleword block transfer External request Internally connected Interrupt JTAG clock JTAG data input JTAG data output JTAG mode select JTAG reset Non-maskable interrupt N-Trace clock N-Trace data output N-Trace end Out-of-Order Return mode SysID(2:0): TIntSel: ValidIn#: ValidOut#: VDD: VDDIO: VDDPA1, VDDPA2: VSS: VSSPA1, VSSPA2: WrRdy#: SysClock: SysCmd(8:0): PReq#: RdRdy#: Release#: Reset#: SysAD(63:0): SysADC(7:0): Processor request Read ready Release Reset System address/data bus System address/data check bus System clock System command/data identifier bus System bus identifier Timer interrupt selection Valid input Valid output Power supply for CPU core Power supply for I/O Noise Sensitive VDD for PLL Ground Noise Sensitive VSS for PLL Write ready # indicates active low. Data Sheet U15700EJ1V0DS 5 µPD30550 INTERNAL BLOCK DIAGRAM VR5500 Instruction cache BHT IFU RAS IMQ Control signal SysAD bus (64/32 bits) SIU RCU RF ICU RS WTB RNRF EXU Test interface ALU0 FPU/ MACU SysClock Clock generator DCU Data cache SB RB ALU1 FPU BRU LSU CP0 TLB 6 Data Sheet U15700EJ1V0DS µPD30550 CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................8 1.1 List of Pin Functions ...................................................................................................................................... 8 1.2 Recommended Connection of Unused Pins .............................................................................................. 12 2. ELECTRICAL SPECIFICATIONS ..........................................................................................................14 3. PACKAGE DRAWING............................................................................................................................24 4. RECOMMENDED SOLDERING CONDITIONS .....................................................................................25 Data Sheet U15700EJ1V0DS 7 µPD30550 1. PIN FUNCTIONS Remark # indicates active low. 1.1 List of Pin Functions (1) System interface signals Pin Name SysAD(63:0) I/O I/O System address/data bus A 64-bit bus for communication between the processor and external agent. The lower 32 bits (SysAD(31:0)) are used in 32-bit bus mode. SysADC(7:0) I/O System address/data check bus A bus for SysAD bus parity. Valid only during a data cycle. The lower 32 bits (SysADC(3:0)) are used in 32-bit bus mode. SysCmd(8:0) I/O System command/data ID bus A 9-bit bus that transfers command and data identifiers between the processor and external agent SysID(2:0) I/O System bus protocol ID These signals transfer request identifiers in the out-of-order return mode. The processor drives a valid identifier in synchronization with the activation of the ValidOut# signal. The external agent must drive valid identifiers in synchronization with the activation of the ValidIn# signal. ValidIn# Input Valid In This signal indicates the external agent is driving a valid address or data onto the SysAD bus, a valid command or data identifier onto the SysCmd bus, or a valid request identifier onto the SysID bus in the out-of-order return mode. ValidOut# Output Valid out This signal indicates the processor is driving a valid address or data onto the SysAD bus, a valid command or data identifier onto the SysCmd bus, or a valid request identifier onto the SysID bus in the out-of-order return mode. RdRdy# Input Read ready This signal indicates the external agent is ready to accept a processor read request WrRdy# Input Write ready This signal indicates the external agent is ready to accept a processor write request ExtRqst# Input External request This signal indicates the external agent is requesting the right to use the system interface Release# Output Releases interface This signal indicates the processor is releasing the system interface to external agent control PReq# Output Processor request This signal indicates the processor has a request that is pending Function 8 Data Sheet U15700EJ1V0DS µPD30550 (2) Initialization interface signals Pin Name DivMode(2:0) I/O Division mode These signals set the division ratio of PClock and SysClock as follows: 111: 5.5 110: 5 101: 4.5 100: 4 011: 3.5 010: 3 001: 2.5 000: 2 Set the input levels of these signals before a power-on reset. Make sure that the levels of these signals do not change while the VR5500 is operating. BigEndian Input Endian mode This signal sets the byte ordering for addressing. 1: Big endian 0: Little endian Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. BusMode Input Bus mode This signal sets the bus width of the system interface. 1: 64 bits 0: 32 bits Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. TIntSel Input Interrupt source select This signal sets the interrupt source to be assigned to the IP7 bit of the Cause register. 1: Timer interrupt 0: Int5# input and external write request (SysAD5) Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. DisDValidO# Input ValidOut# delay enable 1: ValidOut# is active even while the address cycle is stalled 0: ValidOut# is active during the address issuance cycle only Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. DWBTrans# Input Doubleword block transfer enable (valid in 32-bit bus mode only) 1: Disabled 0: Enabled Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. Function (1/2) Remark 1: High level, 0: Low level Data Sheet U15700EJ1V0DS 9 µPD30550 (2/2) Pin Name O3Return# I/O Input Out-of-Order Return mode This signal sets the protocol of the system interface. 1: Normal mode 0: Out-of-order return mode Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. ColdReset# Input Cold reset This signal completely initializes the internal status of the processor. Deassert it in synchronization with SysClock. Reset# Input Reset This signal logically initializes the internal status of the processor. Deassert it in synchronization with SysClock. DrvCon Input Drive control This signal sets the impedance of the external output driver. 1: Low 0: Normal (recommended) Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. Remark Applies to revision 2.0 or later products. Fixed to 0 in revision 1.x products. Function Remark 1: High level, 0: Low level The O3Return#, DWBTrans#, DisDValidO#, and BusMode signals are used for determining the protocol of the system interface. The protocol is selected as follows in accordance with the setting of these signals. Protocol VR5000 TM O3Return# 1 1 1 0 DWBTrans# 1 1 0 Arbitrary DisDValidO# 1 1 0 Arbitrary BusMode 1 0 0 Arbitrary compatible RM523x compatible VR5432 native mode compatible Out-of-order return mode Remark 1: High level, 0:Low level RM523x is a product of PMC-Sierra, Inc. (3) Interrupt interface signals Pin Name Int(5:0)# I/O Input Interrupt These are general-purpose processor interrupt requests. The input states can be checked by the Cause register. Whether Int5# is acknowledged or not depends on the status of the TIntSel signal during reset. NMI# Input Non-maskable interrupt This is the non-maskable interrupt request. Function 10 Data Sheet U15700EJ1V0DS µPD30550 (4) Clock interface signals Pin Name SysClock VDDPA1 VDDPA2 VSSPA1 VSSPA2 − I/O Input − System clock Clock input to the processor VDD for PLL Power supply for the internal PLL VSS for PLL Ground for the internal PLL Function (5) Power supply Pin Name VDD VDDIO VSS I/O − − − Power supply pin for core Power supply pin for I/O Ground potential pin Function Caution The VR5500 uses two separate power supply pins. The power supply pins can be applied in any sequence. Power application to the pins must occur within 100ms of each other. (6) Test interface signals Pin Name NTrcData(3:0) NTrcEnd NTrcClk RMode#/ BKTGIO# I/O Output Output Output I/O Trace data Trace data output Trace end This signal indicates the end of a trace data packet. Trace clock Clock for the test interface. The same clock as SysClock is output. Reset mode/break trigger I/O When the JTRST# signal is active, this is a debug reset mode input signal . During normal operation this serves as a break or trigger I/O signal. JTDI JTDO JTMS JTCK Input Output Input Input JTAG data input Serial data input for JTAG JTAG data output Serial data output for JTAG. Output is performed in synchronization with the rise of JTCK. JTAG mode select This signal selects the JTAG test mode. JTAG clock input Serial clock input for JTAG. The maximum frequency is 33 MHz. There is no need for it to be synchronized with SysClock. JTRST# Input JTAG reset input A signal for initializing the JTAG test module. Function Data Sheet U15700EJ1V0DS 11 µPD30550 1.2 Recommended Connection of Unused Pins (1) System interface pins (a) 32-bit bus mode The VR5500 allows selection of a SysAD bus width from 64 bits or 32 bits. When the 32-bit bus mode is selected, the VR5500 operates using only the required system interface pins. Therefore, set the unused pins as follows when operating the VR5500 in the 32-bit bus mode. Pin Name Recommended Connection of Unused Pins SysAD(63:32) SysADC(7:4) Leave open Leave open (b) Normal mode The VR5500 can process read/write transactions regardless of the order in which requests are issued in the out-of-order return mode. The SysID(2:0) signals are used to identify each request during this processing. Set these signals, which are not used in the normal mode, as follows. Pin Name Recommended Connection of Unused Pins SysID(2:0) Leave open (c) Parity bus The VR5500 allows selection of whether the data is protected using parity. When parity is used, the parity data is output from the processor or external agent to the SysADC bus. However, whether the parity is used or not is selected by software, so unless the program is started, the VR5500 cannot determine the operation of the SysADC bus. Therefore, care must be taken to prevent the SysADC bus from being left open or in a high-impedance state. Each pin of the SysADC bus should be connected to VDDIO via a high resistance value resistor when parity is not used. 12 Data Sheet U15700EJ1V0DS µPD30550 (2) Test interface pins The VR5500 can be used to perform testing and debugging via N-Wire and JTAG with the device mounted on the board. The test interface pins are used for connection with the external debug tool during this debugging. When this test interface is not going to be used and when it is in normal operation mode, set the test interface pins as follows. Pin Name Recommended Connection of Unused Pins JTCK JTDI JTMS JTRST# JTDO NTrcClk NTrcData(3:0) NTrcEnd RMode#/BKTGIO# Pull up Pull up Pull up Pull up Leave open Leave open Leave open Leave open Pull up Data Sheet U15700EJ1V0DS 13 µPD30550 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage Symbol VDDIO VDD VDDP Input voltage Note Conditions Ratings −0.5 to +4.0 −0.5 to +2.0 −0.5 to +2.0 −0.5 to VDDIO + 0.3 −1.5 to VDDIO + 0.3 −10 to +85 −40 to +125 Unit V V V V V °C °C VI Pulse of less than 7 ns Operating case temperature Storage temperature TC Tstg Note The upper limit of the input voltage (VCCIO + 0.3) is +4.0 V. Cautions 1. Do not short-circuit two or more outputs at the same time. 2. The maximum ratings shown in the table above indicate the point at which the product is on the verge of being physically damaged. Exceeding the maximum ratings even momentarily on any parameter may cause such damage. Therefore do not use the product under conditions which will violate these ratings. The specifications and conditions shown in the following DC Characteristics and AC Characteristics sections are the ranges within which the product can normally operate and the quality can be guaranteed. Operating conditions (1) 300 MHz product Parameter Supply voltage Symbol VDDIO Conditions MIN. 2.375 3.135 VDD VDDP 1.425 1.425 MAX. 2.625 3.465 1.575 1.575 Unit V V V V Caution VDD can also be used with the voltage range of the 400 MHz product (1.6 to 1.7 V). Internal operation at 300 MHz is still guaranteed. The core block supply current in this case (MAX. 1.8 A) is the same value as the 400 MHz product. (2) 400 MHz product Parameter Supply voltage Symbol VDDIO Conditions MIN. 2.375 3.135 VDD VDDP 1.6 1.6 MAX. 2.625 3.465 1.7 1.7 Unit V V V V Caution VDD can also be used with the voltage range of the 300 MHz product (1.425 to 1.575 V). In this case, internal operation at 300 MHz is guaranteed only. The core block supply current in this case (MAX. 1.4 A) is the same value as the 300 MHz product. 14 Data Sheet U15700EJ1V0DS µPD30550 Supply Current Parameter Supply current of core block Symbol IDD operation, VDD = VDDP = 1.575 V 400 MHz product, during normal operation, VDD = VDDP = 1.7 V IDD_sb 300 MHz product, in standby mode, VDD = VDDP = 1.575 V 400 MHz product, in standby mode, VDD = VDDP = 1.7 V 0.45 A 0.35 A 1.8 A Conditions 300 MHz product, during normal MIN. MAX. 1.4 Unit A Remark The supply current in the I/O block varies depending on the application used. It is normally 20% IDD or lower. DC Characteristics (1) When VDDIO = 2.5 V ±5% (300 MHz product: TC = −10 to +85°C, VDDIO = 2.5 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85°C, VDDIO = 2.5 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Parameter Output voltage, high Output voltage, low Input voltage, high Input voltage, low Note 1 Symbol VOH VOL VIH VIL Conditions VDDIO = MIN., IOH = 4 mA VDDIO = MIN., IOL = 4 mA MIN. 0.8 × VDDIO MAX. Unit V 0.4 2.0 −0.5 VDDIO + 0.3 0.2 × VDDIO 0.2 × VDDIO VDDIO + 0.3 0.2 × VDDIO 0.2 × VDDIO 5.0 −5.0 5.0 −5.0 V V V V V V V Note 1 Pulse of less than 7 ns Input voltage, high Input voltage, low Note 2 −1.5 0.8 × VDDIO −0.5 VIHC VILC Pulse of less than 7 ns Note 2 −1.5 Input current leakage, high Input current leakage, low Output current leakage, high Output current leakage, low ILIH ILIL ILOH ILOL VI = VDDIO VI = 0 V VO = VDDIO VO = 0 V µA µA µA µA Notes 1. 2. Does not apply to the SysClock pin. Only applies to the SysClock pin. Data Sheet U15700EJ1V0DS 15 µPD30550 (2) When VDDIO = 3.3 V ±5% (300 MHz product: TC = −10 to +85°C, VDDIO = 3.3 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85°C, VDDIO = 3.3 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Parameter Output voltage, high Output voltage, low Input voltage, high Input voltage, low Note 1 Symbol VOH VOL VIH VIL Conditions VDDIO = MIN., IOH = 4 mA VDDIO = MIN., IOL = 4 mA MIN. 2.4 MAX. Unit V 0.4 2.0 −0.5 VDDIO + 0.3 0.8 0.8 VDDIO + 0.3 0.2 × VDDIO 0.2 × VDDIO 5.0 −5.0 5.0 −5.0 V V V V V V V Note 1 Pulse of less than 7 ns Input voltage, high Input voltage, low Note 2 −1.5 0.8 × VDDIO −0.5 VIHC VILC Pulse of less than 7 ns Note 2 −1.5 Input current leakage, high Input current leakage, low Output current leakage, high Output current leakage, low ILIH ILIL ILOH ILOL VI = VDDIO VI = 0 V VO = VDDIO VO = 0 V µA µA µA µA Notes 1. 2. Does not apply to the SysClock pin. Only applies to the SysClock pin. 16 Data Sheet U15700EJ1V0DS µPD30550 Power-on Sequence The VR5500 uses two power supply pins. These power supply pins can be applied in any sequence. However, power may not be applied to one pin more than 100 ms before it is applied to the other. Parameter Power-on delay Symbol tDF Conditions MIN. 0 MAX. 100 Unit ms Capacitance (TA = 25°C, VDDIO = VDD = VDDP = 0 V) Parameter Input capacitance Output capacitance Symbol CIN COUT fC = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. MAX. 5.0 7.0 Unit pF pF AC Characteristics (300 MHz products: TC = −10 to +85, VDDIO = 2.5 V ±5%, 3.3 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85, VDDIO = 2.5 V ±5%, 3.3 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Clock parameters (1/2) Parameter System clock high-level width System clock low-level width Pipeline clock frequency Symbol tCH tCL 300 MHz product 400 MHz product System clock frequency Note Conditions MIN. 1.8 1.8 200 200 100 80 66.7 57.2 50 44.5 40 36.4 100 80 66.7 57.2 50 44.5 40 36.4 MAX. Unit ns ns 300 400 133 120 100 85.7 75 66.6 60 54.5 133 133 133 114 100 88.8 80 72.7 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 300 MHz product DivMode = 2:1 DivMode = 2.5:1 DivMode = 3:1 DivMode = 3.5:1 DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 5.5:1 400 MHz product DivMode = 2:1 DivMode = 2.5:1 DivMode = 3:1 DivMode = 3.5:1 DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 5.5:1 Note This is the frequency at which the operation of the internal PLL is guaranteed. Data Sheet U15700EJ1V0DS 17 µPD30550 Clock parameters (2/2) Parameter System clock cycle Symbol tCP 300 MHz product Conditions DivMode = 2:1 DivMode = 2.5:1 DivMode = 3:1 DivMode = 3.5:1 DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 5.5:1 400 MHz product DivMode = 2:1 DivMode = 2.5:1 DivMode = 3:1 DivMode = 3.5:1 DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 5.5:1 System clock jitter System clock rise time System clock fall time JTAG clock frequency tJ tCR tCF MIN. 7.5 8.3 10 11.7 13.3 15 16.7 18.3 7.5 7.5 7.5 8.8 10 11.3 12.5 13.8 MAX. 10 12.5 15 17.5 20 22.5 25 27.5 10 12.5 15 17.5 20 22.5 25 27.5 5 1.2 1.2 33 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns % ns ns MHz Remarks 1. The system clock jitter is a cycle-to-cycle jitter. 2. The JTAG clock runs asynchronously to the system clock. System interface parameters Parameter Data output hold time Note 1 Note 1 Symbol tDM tDO tDS tDH Conditions MIN. MAX. Unit 1.0 5.0 1.5 300 MHz product 400 MHz product 1.0 0.5 ns ns ns ns ns Data output delay time Data input setup time Data input hold time Note 2 Note 2 Notes 1. Applies to the Release#, ValidOut#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), and SysID(2:0) pins. 2. Applies to the ColdReset#, Reset#, Int(5:0), NMI#, ExtRqst#, RdRdy#, ValidIn#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), and SysID(2:0) pins. Load coefficient Parameter Load coefficient Symbol CLD Conditions MIN. MAX. 1.0 Unit ns/25 pF 18 Data Sheet U15700EJ1V0DS µPD30550 Measurement Conditions Measurement points SysClock 50% tDO tDM All output pins 50% Load conditions All output pins DUT CL = 50 pF Timing Charts Clock timing tCP tCH 80% SysClock 50% 20% tCL tCR tCF Data Sheet U15700EJ1V0DS 19 µPD30550 Clock jitter tJ tJ SysClock 50% System interface edge timing SysClock tDO tDH tDM SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) Output Output tDS Input tDO tDM ValidOut#, Release#, PReq# Output Output tDS tDH ValidIn#, ExtRqst#, RdRdy#, WrRdy#, Int(5:0)#, NMI# ColdReset#, Reset# Input 20 Data Sheet U15700EJ1V0DS µPD30550 Clock relationships (DivMode = 2:1) Cycle 1 2 3 4 SysClock (input) PClock (internal) tDO tDM Note (output) Data Data Data Data Note (input) tDS Data Data Data Data tDH Note SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) Power-on sequence tDF VDD 50% tDF VDDIO 50% Data Sheet U15700EJ1V0DS 21 µPD30550 Reset Timing Power-on reset timing VDD Note 1 VDDIO SysClock (input) Note 2 ≥100 ms ColdReset# (input) ≥64 K SysClock tDS ≥16 SysClock tDS Reset# (input) Notes 1. 2. 1.425 V (300 MHz product), 1.6 V (400 MHz product) 2.375 V at 2.5V operation or 3.135 V at 3.3V operation Cold reset timing VDD H VDDIO SysClock (input) H ≥64 K SysClock tDS tDS ≥16 SysClock tDS tDS ColdReset# (input) Reset# (input) 22 Data Sheet U15700EJ1V0DS µPD30550 Warm reset timing VDD H VDDIO H SysClock (input) ≥16 SysClock ColdReset# (input) H tDS Reset# (input) tDS Data Sheet U15700EJ1V0DS 23 µPD30550 3. PACKAGE DRAWING 272-PIN PLASTIC BGA (CAVITY DOWN ADVANCED TYPE) (29x29) D B A ZE ZD E 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AA Y W V U T R P N M L K J H G F E D C B A INDEX AREA A A2 A1 S 4-C1.4 detail of A part A y φb φ x1 φ x2 S M M e SAB S A4 ITEM D E e A A1 A2 A4 b x1 x2 y ZD ZE MILLIMETERS 29.00 ± 0.20 29.00 ± 0.20 1.27 1.75 ± 0.30 0.60 ± 0.10 1.15 0.25MIN. φ 0.75 ± 0.15 0.30 0.15 0.20 1.80 1.80 P272F2-127-BA1 24 Data Sheet U15700EJ1V0DS µPD30550 4. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For details on the recommended soldering conditions, refer to the Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 4-1. Surface mounting Type Soldering Conditions µPD30550F2-300-NN1: 272-pin plastic BGA (C/D advanced type) (29 × 29) µPD30550F2-400-NN1: 272-pin plastic BGA (C/D advanced type) (29 × 29) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Three times or less, Exposure limit: 3 days Note IR35-103-3 (after that, prebake at 125°C for 10 hours) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet U15700EJ1V0DS 25 µPD30550 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Reference document Electrical Characteristics for Microcomputer (U15170J) Note This document number is that of Japanese version. Note The related documents indicated in the publication may include preliminary versions. However, preliminary versions are not marked as such. 26 Data Sheet U15700EJ1V0DS µPD30550 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • • • • • Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements • In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 • Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 • Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 • Branch Sweden Taeby, Sweden Tel: 08-63 80 820 NEC Electronics (Europe) GmbH Fax: 08-63 80 388 Duesseldorf, Germany • United Kingdom Branch Tel: 0211-65 03 01 Milton Keynes, UK Fax: 0211-65 03 327 Tel: 01908-691-133 Fax: 01908-670-290 • Sucursal en España Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 • Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 J02.4 Data Sheet U15700EJ1V0DS 27