UPD3728

DATA SHEET MOS INTEGRATED CIRCUIT µPD3728 7300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µPD3728 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3728 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on. FEATURES • Valid photocell • Line spacing • Color filter • Resolution • Data rate • Output type • Power supply • On-chip circuits : 7300 pixels × 3 : 40 µm (4 lines) Red line-Green line, Green line-Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour) : 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side) : 40 MHz MAX. (20 MHz/1 output) : 2 outputs in phase/color : +12 V : Reset feed-through level clamp circuits Voltage amplifiers • Photocell's pitch : 10 µm • Drive clock level : CMOS output under 5 V operation ORDERING INFORMATION Part Number Package CCD linear image sensor 36-pin ceramic DIP (600 mil) µPD3728D The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13878EJ1V0DS00(1st edition) Date published April 1999 N CP(K) Printed in Japan © 1999 µPD3728 BLOCK DIAGRAM φ CLB 30 φ 1L 29 φ 20 28 GND 16 φ1 23 φ2 24 GND 31 VOUT2 (Blue, even) 32 CCD analog shift register Transfer gate S7299 S7300 D128 D129 D27 GND 33 ..... S1 S2 Photocell (Blue) ..... D134 22 φ TG1 (Blue) VOUT1 (Blue, odd) GND 34 35 Transfer gate CCD analog shift register VOUT3 36 (Green, odd) CCD analog shift register Transfer gate S7299 S7300 D128 D129 D27 S1 S2 ..... Photocell (Green) ..... D134 21 φ TG2 (Green) VOUT4 1 (Green, even) GND VOUT6 (Red, even) 2 3 Transfer gate CCD analog shift register CCD analog shift register Transfer gate S7299 S7300 D128 D129 D27 S1 S2 GND 4 ..... Photocell (Red) ..... D134 15 φ TG3 (Red) VOUT5 (Red, odd) 5 Transfer gate CCD analog shift register GND 6 7 VOD 8 9 13 14 φ RB φ10 φ1 φ2 2 DATA SHEET S13878EJ1V0DS00 µPD3728 PIN CONFIGURATION (Top View) CCD linear image sensor 36-pin ceramic DIP (600 mil) • µPD3728D Output signal 4 (Green, even) VOUT4 1 Ground GND 2 36 VOUT3 35 GND Output signal 3 (Green, odd) Ground Output signal 1 (Blue, odd) Ground Output signal 2 (Blue, even) Ground Reset feed-through level clamp clock Last stage shift register clock 1 Shift register clock 20 1 1 Output signal 6 (Red, even) VOUT6 3 Ground GND 4 1 Blue 34 VOUT1 33 GND 32 VOUT2 31 GND 30 φ CLB 29 φ 1L 28 φ 20 Output signal 5 (Red, odd) VOUT5 5 Ground Output drain voltage Reset gate clock Shift register clock 10 GND 6 VOD 7 φ RB 8 φ 10 9 Green Red No connection No connection No connection Shift register clock 1 Shift register clock 2 NC 10 NC 11 NC 12 27 NC 26 NC 25 NC 24 φ 2 23 φ 1 22 φ TG1 No connection No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green) No connection No connection φ 1 13 φ 2 14 Transfer gate clock 3 (for Red) φ TG3 15 7300 7300 7300 Ground No connection No connection GND 16 NC 17 NC 18 21 φ TG2 20 NC 19 NC PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 10 µm 7 µm 3 µm Blue photocell array 4 lines (40 µm) 10 µ m Channel stopper 10 µm Green photocell array 4 lines (40 µm) 10 µm Aluminum shield Red photocell array DATA SHEET S13878EJ1V0DS00 3 µPD3728 ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD Vφ1, Vφ1L, Vφ10, Vφ2, Vφ20 VφRB VφCLB VφTG1 to VφTG3 TA Tstg Symbol Ratings –0.3 to +15 –0.3 to +15 –0.3 to +15 –0.3 to +15 –0.3 to +15 –25 to +60 –40 to +100 Unit V V V V V °C °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high levelNote VOD Vφ1H, Vφ1LH, Vφ10H, Vφ2H, Vφ20H Vφ1L, Vφ1LL, Vφ10L, Vφ2L, Vφ20L VφRBH VφRBL VφCLBH VφCLBL VφTG1H to VφTG3H Symbol MIN. 11.4 4.5 –0.3 4.5 –0.3 4.5 –0.3 4.5 TYP. 12.0 5.0 0 5.0 0 5.0 0 Vφ1H (Vφ10H) 0 2 MAX. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 Vφ1H (Vφ10H) +0.5 40 Unit V V V V V V V V Transfer gate clock low level Data rate VφTG1L to VφTG3L 2fφRB –0.3 – V MHz Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H (Vφ10H)), Image lag can increase. Remark Pin 9 (φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so. 4 DATA SHEET S13878EJ1V0DS00 µPD3728 ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, fφRB = 1 MHz, data rate = 2 MHz, storage time = 10 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Note 1 Symbol Vsat SER SEG SEB PRNU ADS1 ADS2 Test Conditions MIN. 1.5 TYP. 2.0 0.35 0.39 0.31 MAX. – Unit V lx•s lx•s lx•s VOUT = 1 V Light shielding 6 1.0 0.5 18 5.0 5.0 5.0 5.0 800 0.5 7.3 6.6 8.3 5.0 5.0 6.0 % mV mV mV mV mW kΩ V/lx•s V/lx•s V/lx•s % % V ns Dark signal non-uniformity Note 1 DSNU1 DSNU2 Light shielding 2.0 1.0 600 0.3 3.9 3.6 4.5 5.6 5.1 6.4 2.0 1.0 4.0 5.0 20 0 95 98 Power consumption Output impedance Response Red Green Blue Image lag Note 1 PW ZO RR RG RB IL1 IL2 VOUT = 1 V Offset level Note 2 Note 3 VOS td RI TTE VOUT = 1 V VOUT = 1 V VOUT = 1 V, data rate = 40 MHz Output fall delay time Register imbalance 4.0 % % Total transfer efficiency Response peak Red Green Blue 630 540 460 DR11 DR12 DR21 DR22 Vsat/DSNU1 Vsat/DSNU2 Vsat/σbit1 Vsat/σbit2 Light shielding Light shielding, bit clamp mode (t7 = 150 ns) Light shielding, line clamp mode (t19 = 3 µs) –500 – – – – 1000 2000 2000 4000 +200 1.0 0.5 4.0 2.0 +500 – – – – nm nm nm times times times times mV mV mV mV mV Dynamic range Note 1 Reset feed-through noise Random noise Note 1 Note 2 RFTN σbit1 σbit2 σline1 σline2 Notes 1. ADS1, DSNU1, IL1, DR11, DR21, σbit1 and σline1 show the specification of VOUT1 and VOUT2. ADS2, DSNU2, IL2, DR12, DR22, σbit2 and σline2 show the specification of VOUT3 to VOUT6. 2. Refer to TIMING CHART 2, 5. 3. When the fall time of φ1L (t2’) is the TYP. value (refer to TIMING CHART 2, 5). DATA SHEET S13878EJ1V0DS00 5 µPD3728 INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Symbol Pin name Pin No. C φ1 MIN. TYP. 350 350 350 350 350 350 10 10 10 100 100 100 MAX. 500 500 500 500 500 500 Unit pF pF pF pF pF pF pF pF pF pF pF pF φ1 13 23 φ10 Shift register clock pin capacitance 2 C φ2 9 14 24 φ2 φ20 Last stage shift register clock pin capacitance Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance C φL CφRB CφCLB CφTG 28 29 8 30 22 21 15 φ1L φRB φCLB φTG1 φTG2 φTG3 Remark Pins 13, 23 (φ1) and pin 9 (φ10) are connected each other inside of the device. Pins 14, 24 (φ2) and pin 28 (φ20) are connected each other inside of the device. 6 DATA SHEET S13878EJ1V0DS00 TIMING CHART 1 (Bit clamp mode, for each color) φ TG1 to φ TG3 φ 1 (φ 10) φ 2 (φ 20) φ 1L 7426 7428 7430 7432 7434 2 4 6 8 10 12 14 16 18 20 22 VOUT2, 4, 6 24 26 Optical black (96 pixels) Invalid photocell (6 pixels) Valid photocell (7300 pixels) Invalid photocell (6 pixels) 7436 7438 120 122 124 126 128 130 132 28 30 DATA SHEET S13878EJ1V0DS00 φ RB φ CLB Note 7425 7427 7429 7431 7433 1 3 5 7 9 11 13 15 17 19 21 23 25 7435 7437 119 121 123 125 127 129 131 27 29 Note VOUT1, 3, 5 µPD3728 Note Input the φRB and φCLB pulses continuously during this period, too. 7 µPD3728 TIMING CHART 2 (Bit clamp mode, for each color) t1 t2 φ 1 (φ 10) 10 % 90 % φ 2 (φ 20) 90 % 10 % 90 % 10 % t1' 90 % 10 % t5 t3 t10 t8 90 % 10 % td t7 t9 t11 t6 t4 t2' φ 1L φ RB φ CLB VOUT1 to VOUT6 RFTN VOS 10 % Symbol t1, t2 t1’, t2’ t3 t4 t5, t6 t7 t8, t9 t10 t11 MIN. 0 0 20 5 0 20 0 –10Note 1 –5Note 2 TYP. 50 5 50 200 20 150 20 +50 +50 MAX. Unit ns ns ns – ns ns ns ns – ns ns 8 DATA SHEET S13878EJ1V0DS00 µPD3728 Notes 1. MIN. of t10 shows that the φRB and φCLB overlap each other. φ RB 90 % t10 φ CLB 90 % 2. MIN. of t11 shows that the φ1L and φCLB overlap each other. φ 1L 90 % φ CLB t11 90 % DATA SHEET S13878EJ1V0DS00 9 µPD3728 TIMING CHART 3 (Bit clamp mode, for each color) t13 90 % 10 % t15 t16 t12 t14 φ TG1 to φ TG3 φ 1 (φ 10) φ 2 (φ 20) 90 % φ 1L φ RB φ CLB Note 1 90 % t11 90 % Symbol t11 t12 t13, t14 t15, t16 MIN. –5Note 2 3000 0 900 TYP. +50 10000 50 1000 MAX. Unit ns ns ns ns Notes 1. Input the φRB and φCLB pulses continuously during this period, too. 2. MIN. of t11 shows that the φ1L and φCLB overlap each other. φ 1L 90 % t11 φ CLB 90 % φ1 (φ10), φ2 (φ20) cross points φ1L, φ2 (φ20) cross points φ 1 (φ 10) φ 2 (φ 20) 2 V or more φ 2 (φ 20) 2 V or more φ 1L 2 V or more 0.5 V or more Remark Adjust cross points (φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin. 10 DATA SHEET S13878EJ1V0DS00 TIMING CHART 4 (Line clamp mode, for each color) φ TG1 to φ TG3 φ 1 (φ 10) φ 2 (φ 20) φ 1L VOUT2, 4, 6 Optical black (96 pixels) Valid photocell (7300 pixels) Invalid photocell (6 pixels) Invalid photocell (6 pixels) 7426 7428 7430 7432 7434 7436 7438 120 122 124 126 128 130 132 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 DATA SHEET S13878EJ1V0DS00 φ RB φ CLB Note 7425 7427 7429 7431 7433 7435 7437 119 121 123 125 127 129 131 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 Note VOUT1, 3, 5 µPD3728 Note Set the φRB to high level during this period. Remark Inverse pulse of the φTG1 to φTG3 can be used as φCLB. 11 µPD3728 TIMING CHART 5 (Line clamp mode, for each color) t1 t2 φ 1(φ 10) 10 % 90 % φ 2(φ 20) 90 % 10 % 90 % 10 % t1' 90 % t5 t3 t6 t4 t2' φ 1L φ RB 10 % “H” φ CLB td VOUT1 to VOUT6 RFTN VOS 10 % Symbol t1, t2 t1’, t2’ t3 t4 t5, t6 MIN. 0 0 20 5 0 TYP. 50 5 50 200 20 MAX. Unit ns ns ns – ns ns 12 DATA SHEET S13878EJ1V0DS00 µPD3728 TIMING CHART 6 (Line clamp mode, for each color) t13 90 % 10 % t15 t12 t14 φ TG1 to φ TG3 t16 φ 1 (φ 10) φ 2 (φ 20) 90 % φ 1L φ RB φ CLB 90 % Note t17 90 % 10 % t20 t18 t19 t21 Symbol t12 t13, t14 t15, t16 t17, t18 t19 t20, t21 MIN. 3000 0 900 100 200 0 TYP. 10000 50 1000 1000 t12 20 MAX. Unit ns ns ns ns ns ns Note Set the φRB to high level during this period. Remark Inverse pulse of the φTG1 to φTG3 can be used as φCLB. φ1 (φ10), φ2 (φ20) cross points φ 1 (φ 10) φ1L, φ2 (φ20) cross points φ 2 (φ 20) 2 V or more 2 V or more 2 V or more 0.5 V or more φ 2 (φ 20) φ 1L Remark Adjust cross points (φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin. DATA SHEET S13878EJ1V0DS00 13 µPD3728 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x : maximum of xj − x  7300 j=1 Σx j x= 7300 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 7300 j=1 Σd j ADS (mV) = 7300 dj : Dark signal of valid pixel number j 14 DATA SHEET S13878EJ1V0DS00 µPD3728 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 7300 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag: IL The rate between the last output voltage and the next one after read out the data of a line. φTG Light ON OFF VOUT V1 VOUT V1 IL (%) = VOUT ×100 DATA SHEET S13878EJ1V0DS00 15 µPD3728 9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 n RI (%) = ∑ (V2j – 1 – V2j) j= 1 2 1 n ∑ Vj j= 1 n × 100 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 σ (mV) = Σ (V – V) i 2 i=1 , V= 1 100 100 100 i=1 ΣV i Vi: A valid pixel output signal among all of the valid pixels for each color VOUT V1 V2 line 1 line 2 V100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). … line 100 … 16 DATA SHEET S13878EJ1V0DS00 µPD3728 STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 °C) 4 Relative Output Voltage Relative Output Voltage 1 2 1 0.5 0.25 0.2 0.1 0 10 20 30 40 50 0.1 1 5 Storage Time (ms) 10 Operating Ambient Temperature TA(°C) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (TA = +25 °C) 100 B 80 R Response Ratio (%) 60 G 40 20 G B 0 400 500 600 Wavelength (nm) 700 800 DATA SHEET S13878EJ1V0DS00 17 µPD3728 APPLICATION CIRCUIT EXAMPLE +5 V 10 Ω + 10 µ F/16 V 0.1 µ F B4 +12 V µ PD3728 1 2 B6 + 36 35 34 33 32 31 30 29 28 47 Ω 47 Ω 2Ω B2 B1 B3 VOUT4 GND VOUT6 GND VOUT5 GND VOD VOUT3 GND VOUT1 GND VOUT2 GND 0.1 µ F 47 µ F/25 V +5 V 3 4 + 0.1 µ F 10 µ F/16 V B5 5 6 7 φ RB 47 Ω 2Ω φ CLB φ 1L φ 20 φ CLB 8 9 φ RB φ 10 10 11 12 2Ω 13 14 15 16 17 18 NC NC NC NC NC NC 27 26 25 24 23 22 21 20 19 2Ω 2Ω 2Ω 2Ω φ2 2Ω 2Ω φ1 φ2 φ TG3 GND NC NC φ2 φ1 φ TG1 φ TG2 NC NC φ1 φ TG Remarks 1. Pin 9 (φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so. 2. The inverters shown in the above application circuit example are the 74AC04. 18 DATA SHEET S13878EJ1V0DS00 µPD3728 B1 to B6 EQUIVALENT CIRCUIT +12 V 47 µ F/25 V + 0.1 µ F 4.7 kΩ 110 Ω CCD VOUT 47 Ω 2SA1005 1 kΩ 2SC945 DATA SHEET S13878EJ1V0DS00 19 µPD3728 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (600mil) (Unit : mm) 94.00±0.50 9.5±0.9 1 (35.0) The 1st valid pixel 2 14.99±0.3 15.24 (4.33) 1.27±0.05 (2.33) 3 0.46±0.05 88.9±0.6 2.54 20.32 2.0±0.3 4 0.25±0.05 3.50±0.5 0.97±0.3 3.30±0.35 Name Glass cap 1 The 1st valid pixel 2 The 1st valid pixel 3 The surface of the chip 4 The bottom of the package Dimensions 93.0 × 13.6 × 1.0 Refractive index 1.5 The center of the pin1 The center of the package (Reference) The top of the glass cap (Reference) The surface of the chip 36D-1CCD-PKG1-1 20 DATA SHEET S13878EJ1V0DS00 µPD3728 NOTES ON THE USE OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. When mounting the package, use a circuit board which will not subject the package to bending stress, or use a socket. For this product, the reference value for the three-point bending strengthNote is 30 kg. Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm / min. Load Load 70 mm 70 mm DATA SHEET S13878EJ1V0DS00 21 µPD3728 [MEMO] 22 DATA SHEET S13878EJ1V0DS00 µPD3728 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. DATA SHEET S13878EJ1V0DS00 23 µPD3728 [MEMO] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8