UPD42S18165L

DATA SHEET µPD42S18165L, 4218165L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE MOS INTEGRATED CIRCUIT Description The µPD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and is useful for the read operation. Besides, the µPD42S18165L can execute CAS before RAS self refresh. The µPD42S18165L, 4218165L are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ. Features • EDO (Hyper page mode) • 1,048,576 words by 16 bits organization • Single +3.3 V ±0.3 V power supply • Fast access and cycle time Power consumption Active (MAX.) 612 mW 540 mW 504 mW Access time (MAX.) 50 ns 60 ns 70 ns R/W cycle time (MIN.) 84 ns 104 ns 124 ns EDO (Hyper page mode) cycle time (MIN.) 20 ns 25 ns 30 ns Part number µPD42S18165L-A50, 4218165L-A50 µPD42S18165L-A60, 4218165L-A60 µPD42S18165L-A70, 4218165L-A70 • The µPD42S18165L can execute CAS before RAS self refresh Power consumption at standby (MAX.) 0.54 mW (CMOS level input) Part number Refresh cycle 1,024 cycles/128 ms Refresh CAS before RAS self refresh, CAS before RAS refresh, RAS only refresh, Hidden refresh CAS before RAS refresh, RAS only refresh, Hidden refresh µPD42S18165L µPD4218165L 1,024 cycles/16 ms 1.8 mW (CMOS level input) The information in this document is subject to change without notice. Document No. M10562EJ8V0DS00 (8th edition) Date Published January 1997 N Printed in Japan The mark shows major revised points. © 1995 µPD42S18165L, 4218165L Ordering Information Access time (MAX.) 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 42-pin plastic SOJ (400 mil) 50-pin plastic TSOP (II) (400 mil) CAS before RAS refresh RAS only refresh Hidden refresh 42-pin plastic SOJ (400 mil) Part number Package 50-pin plastic TSOP (II) (400 mil) Refresh CAS before RAS self refresh CAS before RAS refresh RAS only refresh Hidden refresh µPD42S18165LG5-A50-7JF µPD42S18165LG5-A60-7JF µPD42S18165LG5-A70-7JF µPD42S18165LLE-A50 µPD42S18165LLE-A60 µPD42S18165LLE-A70 µPD4218165LG5-A50-7JF µPD4218165LG5-A60-7JF µPD4218165LG5-A70-7JF µPD4218165LLE-A50 µPD4218165LLE-A60 µPD4218165LLE-A70 2 µPD42S18165L, 4218165L Pin Configurations (Marking Side) 50-pin Plastic TSOP (II) (400 mil) 42-pin Plastic SOJ (400 mil) VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC 1 2 3 4 5 6 7 8 9 10 50 49 48 47 46 45 44 43 42 41 GND I/O16 I/O15 I/O14 I/O13 GND I/O12 I/O11 I/O10 I/O9 NC VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC NC WE RAS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 GND I/O16 I/O15 I/O14 I/O13 GND I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND µ PD42S18165LLE µ PD4218165LLE µ PD42S18165LG5-7JF µ PD4218165LG5-7JF 11 40 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND NC NC A0 A1 A2 A3 VCC A0 to A9 I/O1 to I/O16 RAS UCAS LCAS WE OE V CC GND NC : Address Inputs : Data Inputs/Outputs : Row Address Strobe : Column Address Strobe (upper) : Column Address Strobe (lower) : Write Enable : Output Enable : Power Supply : Ground : No Connection 3 µPD42S18165L, 4218165L Block Diagram RAS LCAS UCAS WE Lower Byte Control Data Output Buffer I/O1 to I/O8 (Lower Byte) OE Clock Generator Upper Byte Control VCC GND CAS before RAS Counter Row Decoder Data Input Buffer Memory Cell Array 1,024 A0 to A9 Row Address Buffer Column Address Buffer X0 to X9 1,024 × 1,024 × 16 1,024 × 16 Data Output Buffer × 16 I/O9 to I/O16 (Upper Byte) Data Input Buffer Y0 to Y9 Sense Amplifier 1,024 Column Decoder 4 µPD42S18165L, 4218165L Input/Output Pin Functions The µPD42S18165L, 4218165L have input pins RAS, CASNote, WE, OE, A0 to A9 and input/output pins I/O1 to I/O16. Pin name RAS (Row address strobe) Input/Output Input Function RAS activates the sense amplifier by latching a row address and selecting a corresponding word line. It refreshes memory cell array of one line selected by the row address. It also selects the following function. • CAS before RAS refresh CAS activates data input/output circuit by latching column address and selecting a digit line connected with the sense amplifier. Address bus. Input total 20-bit of address signal, upper 10-bit and lower 10-bit in sequence (address multiplex method). Therefore, one word is selected from 1,048,576-word by 16-bit memory cell array. In actual operation, latch row address by specifying row address and activating RAS. Then, switch the address bus to column address and activate CAS. Each address is taken into the device when RAS and CAS are activated. Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH) are specified for the activation of RAS and CAS. CAS (Column address strobe) A0 to A9 (Address inputs) WE (Write enable) OE (Output enable) Write control signal. Write operation is executed by activating RAS, CAS and WE. Read control signal. Read operation can be executed by activating RAS, CAS and OE. If WE is activated during read operation, OE is to be ineffective in the device. Therefore, read operation cannot be executed. Input/Output 16-bit data bus. I/O1 to I/O16 are used to input/output data. I/O1 to I/O16 (Data inputs/outputs) Note CAS means UCAS and LCAS. 5 µPD42S18165L, 4218165L Hyper Page Mode (EDO) The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the hyper page mode (EDO) are as follows. 1. Data output time is extended. In the hyper page mode (EDO), the output data is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. 2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode. In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that in the fast page mode is 40 ns. In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle. The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described in the next page. Hyper Page Mode (EDO) Read Cycle RAS VIH – VIL – tHPC tOFR CAS VIH – VIL – tOFC Address VIH – VIL – Row Col.A tRAC tAA tCAC Col.B tAA tCAC Col.C tAA tCAC tRCH tRRH tWPZ WE VIH – VIL – tOCH tOEA VIH – VIL – tOLZ tCLZ VOH – VOL – Hi - Z tDHC tOEZ tCLZ tOEZ tOEZ Hi - Z tCHO tOEP tOEP tOCH tOEA tCHO tWEZ OE I/O Data out A Data out B Data out C Data out C 6 µPD42S18165L, 4218165L Cautions when using the hyper page mode (EDO) 1. CAS access should be used to operate t HPC a t the MIN. value. 2. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective specification depends on the state of each signal. (1) Both RAS and CAS are inactive (at the end of read cycle) WE: inactive, OE: active t OFC i s effective when RAS is inactivated before CAS is inactivated. t OFR i s effective when CAS is inactivated before RAS is inactivated. The slower of t OFC a nd tOFR b ecomes effective. (2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle) WE, OE: inactive ····· t OEZ i s effective. Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle) WE, OE: active and either t RRH o r t RCH m ust be met ····· t WEZ a nd t WPZ a re effective. The faster of t OEZ a nd t WEZ b ecomes effective. The faster of (1) and (2) becomes effective. 3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output with the OE signal. (1) CAS: inactive, OE: active ····· t CHO i s effective. (2) CAS, OE: active ····· t OCH i s effective. 7 µPD42S18165L, 4218165L Electrical Specifications • CAS means UCAS and LCAS. • All voltages are referenced to GND. • After power up (V CC ≥ V CC(MIN.)), wait more than 100 µ s (RAS, CAS inactive) and then, execute eight CAS before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit. Absolute Maximum Ratings Parameter Voltage on any pin relative to GND Supply voltage Output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VCC IO PD TA Tstg Condition Rating –0.5 to +4.6 –0.5 to +4.6 20 1 0 to +70 –55 to +125 Unit V V mA W ˚C ˚C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 –0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 +0.8 70 Unit V V V ˚C Capacitance (TA = 25 ˚C, f = 1 MHZ) Parameter Input capacitance Symbol CI1 CI2 Data input/output capacitance CI/O Address RAS, CAS, WE, OE I/O Test condition MIN. TYP. MAX. 5 7 7 pF Unit pF 8 µPD42S18165L, 4218165L DC Characteristics (Recommended operating conditions unless otherwise noted) Parameter Operating current Symbol ICC1 Test condition RAS, CAS cycling tRC = tRC (MIN.), IO = 0 mA tRAC = 50 ns tRAC = 60 ns tRAC = 70 ns Standby current MIN. MAX. 170 150 140 0.5 0.15 2.0 0.5 170 150 140 120 110 100 170 150 140 300 mA 1, 2 mA 1, 2, 5 mA 1, 2, 3 ,4 mA Unit mA Notes 1, 2, 3 µPD42S18165L ICC2 RAS, CAS ≥ VIH (MIN.), IO = 0 mA RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA µPD4218165L RAS, CAS ≥ VIH (MIN.), IO = 0 mA RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA RAS only refresh current ICC3 RAS cycling, CAS ≥ VIH (MIN.) tRC = tRC (MIN.), IO = 0 mA tRAC = 50 ns tRAC = 60 ns tRAC = 70 ns Operating current (Hyper page mode (EDO)) ICC4 RAS ≤ VIL (MAX.), CAS cycling tHPC = tHPC (MIN.), IO = 0 mA tRAC = 50 ns tRAC = 60 ns tRAC = 70 ns CAS before RAS refresh current ICC5 RAS cycling tRC = tRC (MIN.) , IO = 0 mA tRAC = 50 ns tRAC = 60 ns tRAC = 70 ns CAS before RAS long refresh current (1,024 cycles / 128 ms, only for the µPD42S18165L) ICC6 CAS before RAS refresh : tRC = 125.0 µs RAS, CAS: VCC – 0.2 V ≤ VIH ≤ VIH (MAX.) 0 V ≤ VIL ≤ 0.2 V Standby: RAS, CAS ≥ VCC – 0.2 V Address: VIH or VIL WE, OE: VIH I O = 0 mA tRAS ≤ 300 ns µA 1, 2 tRAS ≤ 1 µs 400 µA 1, 2 CAS before RAS self refresh current (only for the µPD42S18165L) ICC7 RAS, CAS : tRASS = 5 ms VCC – 0.2 V ≤ VIH ≤ VIH (MAX.) 0 V ≤ VIL ≤ 0.2 V I O = 0 mA VI = 0 to 3.6 V All other pins not under test = 0 V VO = 0 to 3.6 V Output is disabled (Hi-Z) IO = –2.0 mA IO = +2.0 mA –5 200 µA 2 Input leakage current II (L) +5 µA µA V Output leakage current IO (L) –5 +5 High level output voltage Low level output voltage VOH VOL 2.4 0.4 V Notes 1. ICC1, ICC3, ICC4, ICC5 and ICC6 depend on cycle rates (tRC and tHPC). 2. Specified values are obtained with outputs unloaded. 3. ICC1 and ICC3 are measured assuming that address can be changed once or less during RAS ≤ VIL (MAX.) and CAS ≥ VIH (MIN.). 4. ICC3 is measured assuming that all column address inputs are held at either high or low. 5. ICC4 is measured assuming that all column address inputs are switched only once during each hyper page (EDO) cycle. 9 µPD42S18165L, 4218165L AC Characteristics (Recommended Operating Conditions unless otherwise noted) AC Characteristics Test Conditions (1) Input timing specification (2) Output timing specification VIH (MIN.) = 2.0 V VIL (MAX.) = 0.8 V tT = 2 ns (3) Output load condition VCC 1,180 Ω I/O 100 pF CL 870 Ω VOH (MIN.) = 2.0 V VOL (MAX.) = 0.8 V tT = 2 ns Common to Read, Write, Read Modify Write Cycle tRAC = 50 ns Parameter Read / Write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width RAS hold time CAS hold time RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time OE lead time referenced to RAS CAS to data setup time OE to data setup time OE to data delay time Masked byte write hold time referenced to RAS Transition time (rise and fall) Refresh time Symbol MIN. tRC tRP tCPN tRAS tCAS tRSH tCSH tRCD tRAD tCRP tASR tRAH tASC tCAH tOES tCLZ tOLZ tOED tMRH tT 84 30 8 50 8 10 38 11 9 5 0 7 0 7 0 0 0 10 0 1 – – MAX. – – – 10,000 10,000 – – 37 25 – – – – – – – – – – 50 128 16 MIN. 104 40 10 60 10 10 40 14 12 5 0 10 0 10 0 0 0 13 0 1 – – MAX. – – – 10,000 10,000 – – 45 30 – – – – – – – – – – 50 128 16 MIN. 124 50 10 70 12 12 50 14 12 5 0 10 0 12 0 0 0 15 0 1 – – MAX. – – – 10,000 10,000 – – 52 35 – – – – – – – – – – 50 128 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 4 2 2 3 1 tRAC = 60 ns tRAC = 70 ns Unit Notes µPD42S18165L µPD4218165L tREF 10 µPD42S18165L, 4218165L Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 µs. If 10 µs < tRAS < 100 µs, RAS precharge time for CAS before RAS self refresh (tRPS) is applied. 2. For read cycles, access time is defined as follows: Input conditions tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRCD > tRCD (MAX.) Access time tRAC (MAX.) tAA (MAX.) tCAC (MAX.) Access time from RAS tRAC (MAX.) tRAD + tAA (MAX.) tRCD + tCAC (MAX.) tRAD (MAX.) and tRCD (MAX.) are specified as reference points only ; they are not restrictive operating parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause any operation problems. 3. tCRP (MIN.) requirement is applied to RAS, CAS cycles. 4. This specification is applied only to the µPD42S18165L. Read Cycle tRAC = 50 ns Parameter Access time from RAS Access time from CAS Access time from column address Access time from OE Column address lead time referenced to RAS Read command setup time Read command hold time referenced to RAS Read command hold time referenced to CAS Output buffer turn-off delay time from OE CAS hold time to OE Symbol MIN. tRAC tCAC tAA tOEA tRAL tRCS tRRH tRCH tOEZ t CHO – – – – 25 0 0 0 0 5 MAX. 50 15 25 13 – – – – 10 – MIN. – – – – 30 0 0 0 0 5 MAX. 60 17 30 15 – – – – 13 – MIN. – – – – 35 0 0 0 0 5 MAX. 70 18 35 18 – – – – 15 – ns ns ns ns ns ns ns ns ns ns 2 2 3 4 1 1 1 tRAC = 60 ns tRAC = 70 ns Unit Notes Notes 1. For read cycles, access time is defined as follows: Input conditions tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRCD > tRCD (MAX.) Access time tRAC (MAX.) tAA (MAX.) tCAC (MAX.) Access time from RAS tRAC (MAX.) tRAD + tAA (MAX.) tRCD + tCAC (MAX.) tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause any operation problems. 2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles. 3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or VOL. 4. WE: inactive (in read cycle) CAS: inactive, OE: active ····· tCHO is effective. CAS, OE: active ····· tOCH is effective. 11 µPD42S18165L, 4218165L Write Cycle tRAC = 50 ns Parameter WE hold time referenced to CAS WE pulse width WE lead time referenced to RAS WE lead time referenced to CAS WE setup time OE hold time Data-in setup time Data-in hold time Symbol MIN. tWCH tWP tRWL tCWL tWCS tOEH tDS tDH 7 8 10 8 0 0 0 7 MAX. – – tRAC = 60 ns MIN. 10 10 10 10 0 0 0 10 MAX. – – – – – – – – tRAC = 70 ns Unit Notes MIN. 10 10 12 12 0 0 0 10 MAX. – – – – – – – – ns ns ns ns ns ns ns ns 3 3 2 1 1 – – – – – – Notes 1. tWP (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should be met. 2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. 3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and read modify write cycles, they are referenced to the WE falling edge. Read Modify Write Cycle tRAC = 50 ns Parameter Read modify write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Symbol MIN. tRWC tRWD tCWD tAWD 107 64 27 39 MAX. – – – – MIN. 133 77 32 47 MAX. – – – – MIN. 157 89 37 54 MAX. – – – – ns ns ns ns 1 1 1 tRAC = 60 ns tRAC = 70 ns Unit Notes Note 1. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is met, the state of the data out is indeterminate. 12 µPD42S18165L, 4218165L Hyper Page Mode (EDO) tRAC = 50 ns Parameter Read / Write cycle time RAS pulse width CAS pulse width CAS precharge time Access time from CAS precharge CAS precharge to WE delay time RAS hold time from CAS precharge Read modify write cycle time Data output hold time OE to CAS hold time OE precharge time Output buffer turn-off delay from WE WE pulse width Output buffer turn-off delay from RAS Output buffer turn-off delay from CAS Symbol MIN. tHPC tRASP tHCAS tCP tACP tCPWD tRHCP tHPRWC tDHC tOCH tOEP tWEZ tWPZ tOFR tOFC 20 50 8 8 – 41 30 52 5 5 5 0 7 0 0 MAX. – 125,000 10,000 – 30 – – – – – – 10 – 10 10 MIN. 25 60 10 10 – 52 35 66 5 5 5 0 10 0 0 MAX. – 125,000 10,000 – 35 – – – – – – 13 – 13 13 MIN. 30 70 12 10 – 59 40 75 5 5 5 0 10 0 0 MAX. – 125,000 10,000 – 40 – – – – – – 15 – 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4,5 5 4,5 4,5 3 2 1 tRAC = 60 ns tRAC = 70 ns Unit Notes Notes 1. tHPC (MIN.) is applied to CAS access. 2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is met, the state of the data out is indeterminate. 3. WE: inactive (in read cycle) CAS: inactive, OE: active ······ tCHO is effective. CAS, OE: active ······ tOCH is effective. 4. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is not referenced to VOH or VOL. 5. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective specification depends on state of each signal. (1) Both RAS and CAS are inactive (at the end of the read cycle) WE: inactive, OE: active tOFC is effective when RAS is inactivated before CAS is inactivated. tOFR is effective when CAS is inactivated before RAS is inactivated. The slower of tOFC and tOFR becomes effective. (2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle) WE, OE: inactive ······ tOEZ is effective. Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle) WE, OE: active and either tRRH or tRCH must be met ······ tWEZ and tWPZ are effective. The faster of tOEZ and tWEZ becomes effective. The faster of (1) and (2) becomes effective. 13 µPD42S18165L, 4218165L Refresh Cycle tRAC = 50 ns Parameter CAS setup time CAS hold time (CAS before RAS refresh) RAS precharge CAS hold time RAS pulse width (CAS before RAS self refresh) RAS precharge time (CAS before RAS self refresh) CAS hold time (CAS before RAS self refresh) WE hold time Symbol MIN. tCSR tCHR tRPC tRASS tRPS tCHS tWHR 5 10 5 100 90 –50 15 MAX. – – – – – – – MIN. 5 10 5 100 110 –50 15 MAX. – – – – – – – MIN. 5 10 5 100 130 –50 15 MAX. – – – – – – – ns ns ns tRAC = 60 ns tRAC = 70 ns Unit Notes µs ns ns ns 1 1 1 Note 1. This specification is applied only to the µPD42S18165L. 14 µPD42S18165L, 4218165L Read Cycle tRC tRAS RAS VIH – VIL – tCSH tCRP UCAS LCAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH tASC tCAH tRAL tRCD tRSH tCAS tCPN tRP Row tRCS Col. tRCH tRRH tOCH tOES tCHO tOEA tWEZ tWPZ WE VIH – VIL – OE VIH – VIL – tRAC tAA tCAC tOLZ tCLZ tOFC tOEZ tOFR Data out Hi - Z U I/O L I/O VOH – VOL – Hi - Z 15 µPD42S18165L, 4218165L Upper Byte Read Cycle tRC tRAS RAS VIH – VIL – tCSH tCRP UCAS VIH – VIL – tCRP LCAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH tASC tCAH tRAL tMRH tRCD tRSH tCAS tCPN tRP Row tRCS Col. tRCH tRRH tWPZ WE VIH – VIL – tOCH tOES tOEA tCHO tWEZ OE VIH – VIL – tRAC tAA tCAC tOLZ tCLZ tOFR Data out Hi - Z tOFC tOEZ U I/O VOH – VOL – Hi - Z Remark L I/O: Hi-Z 16 µPD42S18165L, 4218165L Lower Byte Read Cycle tRC tRAS RAS VIH – VIL – tCRP VIH – VIL – tCSH tCRP LCAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH Row tRCS VIH – VIL – tASC Col. tRCH tRRH tWPZ tCAH tRAL tRCD tRSH tCAS tCPN tMRH tRP UCAS WE tOCH tOES tOEA tCHO tWEZ OE VIH – VIL – tRAC tAA tCAC tOLZ tCLZ tOFR Data out Hi - Z tOFC tOEZ L I/O VOH – VOL – Hi - Z Remark U I/O: Hi-Z 17 µPD42S18165L, 4218165L Early Write Cycle tRC tRAS RAS VIH– VIL– tCSH tCRP UCAS LCAS VIH– VIL– tRAD tASR Address VIH– VIL– tRAH tASC Col. tCAH tRCD tRSH tCAS tCPN tRP Row tWCS WE VIH– VIL– tDS U I/O L I/O VIH– VIL– tWCH tDH Data in Remark O E: Don’t care 18 µPD42S18165L, 4218165L Upper Byte Early Write Cycle tRC tRAS RAS VIH – VIL – tCSH tCRP UCAS VIH – VIL – tCRP LCAS VIH – VIL – tASR VIH – VIL – tRAD tRAH tASC tCAH tMRH tRCD tRSH tCAS tCPN tRP Address Row Col. tWCS WE VIH – VIL – tDS U I/O VIH – VIL – tWCH tDH Data in Remark OE, L I/O: Don’t care 19 µPD42S18165L, 4218165L Lower Byte Early Write Cycle tRC tRAS RAS VIH – VIL – tCRP UCAS VIH – VIL – tCSH tCRP LCAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH Row tASC Col. tCAH tRCD tRSH tCAS tCPN tMRH tRP tWCS WE VIH – VIL – tDS L I/O VIH – VIL – tWCH tDH Data in Remark OE, U I/O: Don’t care 20 µPD42S18165L, 4218165L Late Write Cycle t RC t RAS RAS VIH– VIL– t CSH t CRP UCAS LCAS VIH– VIL– t RAD t ASR Address VIH– VIL– t RAH t ASC Col. t CWL t RWL t RCS WE VIH– VIL– t WP t CAH t RCD t RSH t CAS t CPN t RP Row t OEH OE VIH– VIL– t OED U I/O L I/O VIH– VIL– Hi-Z t DS t DH Data in 21 µPD42S18165L, 4218165L Upper Byte Late Write Cycle tRC tRAS RAS VIH – VIL – tCSH tCRP UCAS VIH – VIL – tCRP LCAS VIH – VIL – tASR Address VIH – VIL – tRAD tRAH tASC tCAH tMRH tRCD tRSH tCAS tCPN tRP Row Col. tCWL tRWL tRCS tWP WE VIH – VIL – tOEH OE VIH – VIL – tOED tDS tDH Data in U I/O VIH – VIL – Hi - Z Remark L I/O: Don’t care 22 µPD42S18165L, 4218165L Lower Byte Late Write Cycle tRC tRAS RAS VIH – VIL – tCRP UCAS VIH – VIL – tCSH tCRP LCAS VIH – VIL – tASR Address VIH – VIL – tRAD tRAH tASC tCAH tRCD tRSH tCAS tCPN tMRH tRP Row Col. tCWL tRWL tRCS tWP WE VIH – VIL – tOEH OE VIH – VIL – tOED tDS tDH Data in L I/O VIH – VIL – Hi - Z Remark U I/O: Don’t care 23 µPD42S18165L, 4218165L Read Modify Write Cycle t RWC t RAS RAS VIH– VIL– t CSH t CRP UCAS LCAS VIH– VIL– t RAD t ASR Address VIH– VIL– t RAH Row t ASC Col. t RWD t AWD t CWD t CWL t RWL t WP t CAH t RCD t RSH t CAS t CPN t RP t RCS WE VIH– VIL– t OEA OE VIH– VIL– t RAC t AA t CAC U I/O L I/O VIH– VIL– t OLZ t CLZ U I/O VOH– L I/O VOL– Hi-Z t OEZ Data out t OEH t OED t DS Data in t DH Hi-Z 24 µPD42S18165L, 4218165L Upper Byte Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tCSH tCRP UCAS VIH – VIL – tCRP LCAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH Row tASC Col. tRWD tAWD tCWD tCWL tRWL tWP tCAH tRCD tRSH tCAS tCPN tRP tMRH tRCS WE VIH – VIL – tOEA OE VIH – VIL – tRAC tAA tCAC U I/O VIH – VIL – tOLZ tCLZ U I/O VOH – VOL – Hi - Z tOEZ Data out tOED tDS tOEH tDH Data in Hi - Z Remark In this cycle, the input data to Lower I/O is ineffective. The data out of that remains Hi-Z. 25 µPD42S18165L, 4218165L Lower Byte Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tCRP UCAS VIH – VIL – tCSH tCRP LCAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH Row tASC Col. tRWD tAWD tCWD tCWL tRWL tWP tCAH tRCD tRSH tCAS tCPN tMRH tRP tRCS WE VIH – VIL – tOEA OE VIH – VIL – tRAC tAA tCAC L I/O VIH – VIL – tOLZ tCLZ L I/O VOH – VOL – Hi - Z tOEZ Data out tOED tDS tOEH tDH Data in Hi - Z Remark In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi-Z. 26 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Read Cycle tRASP RAS VIH – VIL – tCSH tCRP UCAS LCAS VIH – VIL – tASR Address VIH – VIL – Row tRAD tRAH tASC tCAH Col. tASC Col. tCAH tASC Col. tRCH tRRH tRAL tCAH tOFR tOFC tRCD tHCAS tCP tHCAS tHPC tCP tRHCP tRP tRSH tHCAS tCPN tRCS WE VIH – VIL – tWPZ tWEZ tOCH OE VIH – VIL – tOEA tOLZ tRAC tAA tCAC tCLZ U I/O L I/O VOH – VOL – Hi - Z tACP tAA tCAC tACP tAA tCAC tCHO tDHC tDHC tOEZ Data out Data out Data out Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 27 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Byte Read Cycle tRASP VIH – RAS VIL – tCSH tCRP UCAS VIH – VIL – tCRP LCAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH tASC tCAH Col. tRCS WE VIH – VIL – tWEZ tOCH OE VIH – VIL – tOEA tOLZ tRAC tAA tCAC tCLZ U I/O VOH – VOL – Hi - Z Data out tDHC Data out tACP tAA tCAC tCLZ tDHC tOEZ tACP tAA tCAC tCHO tASC tCAH Col. tASC Col. tRCH tRRH tWPZ tRAL tCAH tOFR tOFC tCP tHCAS tCP tMRH tRCD tHCAS tHPC tRHCP tRP tRSH tHCAS tCPN Row L I/O VOH – VOL – Hi - Z Data out Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS or LCAS simultaneously, or at random. 28 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Read Cycle (WE Control) t RASP RAS VIH – VIL – t CSH t CRP UCAS LCAS VIH – VIL – t ASR Address VIH – VIL – Row t RAD t RAH t ASC t CAH Col. t ASC Col. t WPZ t RCH t RCS tCAH t RAL t ASC Col. t RCH t RCS WE VIH – VIL – t OCH t OEA t OLZ OE VIH – VIL – t RAC t AA t CAC t CLZ U I/O L I/O VOH – VOL – Hi - Z t OFR t AA t WEZ t CAC t CLZ Hi - Z t WEZ Hi - Z t AA t CAC t CLZ Data out Data out t OFC t OEZ tCHO tWEZ t RCH t WPZ t RCS t RRH t WPZ tCAH t RCD t HCAS t HCAS t RHCP t RP t RSH t HCAS t CPN Data out Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 29 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Read Cycle (OE Control) tRASP RAS VIH – VIL – tCSH tCRP UCAS VIH – LCAS VIL – tRAD tASR Address VIH – VIL – tRAH tASC tCAH Col.A tRAC tAA tCAC tASC tCAH tASC tRAL tCAH tOFC tOFR tRCD tHCAS tCP tHPC tHCAS tCP tRHCP tRSH tHCAS tCPN tRP Row Col.B tAA tCAC Col.C tRCH tOES tCAC tAA tCHO tACP tOEP tOEP tOCH tCHO tRRH tRCS WE VIH – VIL – tCHO tOCH tOEA tOEP tACP tOCH OE VIH – VIL – tOLZ tCLZ tOEZ tCLZ tOEZ Data out B tOEA tOLZ tOEZ tOEA tOLZ tOEZ Hi - Z U I/O VOH – L I/O VOL – Hi - Z Data out A Data out B Data out C Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 30 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Early Write Cycle tRASP RAS VIH– VIL– tCSH tCRP UCAS LCAS VIH– VIL– tRAD tASR Address VIH– VIL– tRAH tASC Col. tCAH tASC tCAH Col. tASC tCAH tRAL tRCD tHCAS tCP tHPC tHCAS tCP tRHCP tRP tRSH tHCAS tCPN Row Col. tWCS WE VIH– VIL– tDS U I/O L I/O VIH– VIL– tWCH tWCS tWCH tWCS tWCH tDH tDS tDH tDS tDH Data in Data in Data in Remarks 1. OE: Don’t care 2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 31 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Byte Early Write Cycle tRASP RAS VIH– VIL– tCSH tRCD tHCAS tHPC tRHCP tRP tCRP UCAS VIH– VIL– tRSH tHCAS tCPN tCRP LCAS VIH– VIL– tRAD tRAH tCP tHCAS tCP tMRH tASR Address VIH– VIL– tASC Col. tCAH tASC Col. tCAH tASC Col. tRAL tCAH Row tWCS WE VIH– VIL– tWCH tWCS tWCH tWCS tWCH tDS U I/O VIH– VIL– Data in tDH tDS tDH Data in tDS L I/O VIH– VIL– tDH Data in Remarks 1. OE: Don’t care 2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS or LCAS simultaneously, or at random. 32 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Late Write Cycle t RASP RAS VIH– VIL– t CSH t CRP UCAS LCAS VIH– VIL– t RAD t ASR t RAH Address VIH– VIL– Row t ASC Col. t CWL t RCS WE VIH– VIL– t OEH VIH– VIL– t OEH t OEH t WP t RCS t CAH t ASC Col. t CWL t WP t RCS t CAH t ASC t RAL t CAH Col. t CWL t RWL t WP t RCD t HCAS t CP t HPC t HCAS t CP t RHCP t RSH t HCAS t RP t CPN OE t OED U I/O L I/O VIH– VIL– Hi-Z t DS t DH t OED Hi-Z t DS t DH t OED Hi-Z t DS t DH Data in Data in Data in Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 33 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Byte Late Write Cycle tRASP tRHCP RAS VIH– VIL– tCSH tRCD tHCAS tHPC tRSH tHCAS tRP tCRP UCAS VIH– VIL– tCPN tCRP LCAS VIH– VIL– tRAD tASR Address VIH– VIL– tRAH tASC Col. tCWL tRCS WE VIH– VIL– tWP tCAH tCP tHCAS tCP tMRH tASC Col. tCAH tASC Col. tCWL tRAL tCAH Row tCWL tRWL tRCS tWP tRCS tWP tOEH OE VIH– VIL– tOEH tOEH tOED U I/O VIH– VIL– Hi - Z tDS tDH tOED Hi - Z tOED Hi - Z tDS tDH Data in Data in tOED VIH– L I/O VIL– Hi - Z tOED Hi - Z tDS tDH Data in tOED Hi - Z Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS or LCAS simultaneously, or at random. 34 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Read Modify Write Cycle t RASP RAS VIH– VIL– t HPRWC t HCAS t RP t CRP UCAS LCAS VIH– VIL– t RCD t CP t HCAS t CP t HCAS t CPN t RAD t ASR t RAH Address VIH– VIL– t ASC t CAH t ASC t CAH t ASC t CAH t RAL Row Col. t RWD t AWD t CWD Col. t ACP t CWL t WP t RCS t CPWD t AWD t CWD t CWL t WP Col. t ACP t RCS t RCS WE VIH– VIL– t RAC t AA t CAC t OEA OE VIH– VIL– t CLZ t OLZ U I/O VOH– L I/O VOL– Hi-Z t CPWD t AWD t CWD t CWL t RWL t WP t AA t OEH t CAC t OEA t OEH t AA t CAC t OEA t OEH t OED t OEZ out Hi-Z t CLZ t OLZ t OED t OEZ out Hi-Z t OLZ t CLZ t OED t OEZ out Hi-Z t DS U I/O L I/O VIH– VIL– t DH in t DS t DH in t DS t DH in Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 35 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Byte Read Modify Write Cycle tRASP RAS VIH– VIL– tCRP UCAS VIH– VIL– tHPRWC tHCAS tRP tRCD tHCAS tCPN tCRP LCAS VIH– VIL– tRAD tASR tRAH tASC Address VIH– VIL– Row Col. tRWD tAWD tCWD tCAH tCP tHCAS tCP tMRH tRAL tASC tCAH tASC Col. tACP tCPWD tAWD tCWD tCWL tWP tRCS tCPWD tAWD tCWD tCWL tRWL tWP tCAH Col. tACP tRCS WE VIH– VIL– tRAC tAA tCAC OE VIH– VIL– tOEA tCWL tWP tRCS tAA tOEH tCAC tOEA tOED tOEZ out Hi - Z tOEH tAA tCAC tOEA tOEH tCLZ tOLZ VOH– U I/O VOL– VOH– VOL– Hi - Z tCLZ tOLZ tOED tOEZ tCLZ tOLZ tOED tOEZ out Hi - Z L I/O Hi - Z tDS tDH in out Hi - Z tDS tDH in tDS tDH in VIH– U I/O VIL– L I/O VIH– VIL– Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS or LCAS simultaneously, or at random. 36 µPD42S18165L, 4218165L Hyper Page Mode (EDO) Read and Write Cycle tRASP RAS VIH – VIL – tCSH tCRP UCAS LCAS VIH – VIL – tASR Address VIH – VIL – Row tRAD tRAH tASC tCAH Col. tASC Col. tCAH tASC Col. tRAL tCAH tRCD tHCAS tCP tHCAS tHPC tCP tRHCP tRP tRSH tHCAS tCPN tRCS WE VIH – VIL – tOCH tOEA tOLZ tRAC tAA tCAC tCLZ U I/O L I/O VOH – VOL – Hi - Z Data out tACP tAA tCAC tRCH tWCS tWCH tCHO OE VIH – VIL – tOEZ tDHC tWEZ Hi - Z Data out tDS U I/O L I/O VIH – VIL – tDH Data in Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 37 µPD42S18165L, 4218165L CAS Before RAS Self Refresh Cycle (Only for the µPD42S18165L) tRASS RAS VIH – VIL – tRPC tCHS UCAS LCAS VIH – VIL – t CSR tCPN tRPS tCRP Remark Address, WE, OE: Don’t care L I/O, U I/O: Hi-Z Cautions on Use of CAS Before RAS Self Refresh CAS before RAS self refresh can be used independently when used in combination with distributed CAS before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with long RAS only refresh (both distributed and burst), the following cautions must be observed. (1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please perform CAS before RAS refresh 1,024 times within a 16 ms interval just before and after setting CAS before RAS self refresh. (2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only refresh 1,024 times within a 16 ms interval just before and after setting CAS before RAS self refresh. (3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 µs), CAS before RAS refresh cycles will be executed one time. If 10 µs < tRAS < 100 µs, RAS precharge time for CAS before RAS self refresh (tRPS) is applied. And refresh cycles (1,024/128 ms) should be met. For details, please refer to How to use DRAM User’s Manual. 38 µPD42S18165L, 4218165L CAS Before RAS Refresh Cycle tRC tRAS RAS VIH– VIL– tCSR UCAS LCAS VIH– VIL– tCHR tRPC tCSR tCHR tRPC tRP tRAS tRC tRP tCRP tCPN Remark Address, WE, OE: Don’t care L I/O, U I/O: Hi-Z RAS Only Refresh Cycle tRC tRAS RAS VIH– VIL– tCRP tCRP UCAS VIH– LCAS VIL– tASR tRAH tRPC tCPN tRP tRAS tRC tRP tASR Address VIH– VIL– Row tRAH Row Remark WE, OE: Don’t care L I/O, U I/O: Hi-Z 39 µPD42S18165L, 4218165L Hidden Refresh Cycle (Read) tRC tRAS VIH – RAS VIL – tRP tRC tRAS tRP tCRP UCAS VIH – LCAS VIL – tRAD tRAH Row tRCD tRSH tCHR tCPN tRAL tASC Col. tRCH tRCS tWHR tWPZ tCAH tASR Address VIH – VIL – WE VIH – VIL – tOES tOEA tCHO tWEZ OE VIH – VIL – tRAC tAA tCAC tOLZ tCLZ tOFR tOFC tOEZ Data out Hi - Z U I/O VOH – L I/O VOL – Hi - Z 40 PD42S18165L, 4218165L Hidden Refresh Cycle (Write) tRC tRAS RAS VIH– VIL– tRP tRAS tRC tRP tCRP UCAS VIH– LCAS VIL– tRAD tASR Address VIH– VIL– tRAH tRCD tRSH tCHR tCPN tASC Col. tCAH Row tWCS WE VIH– VIL– tWCH tDS U I/O L I/O VIH– VIL– Data in tDH Remark OE: Don’t care 41 PD42S18165L, 4218165L Package Drawings 50PIN PLASTIC TSOP(II) (400 mil) 50 26 detail of lead end F E 1 A 25 H I J G N C D NOTE B K L M M ITEM A B C D E F G H I J K L M N P MILLIMETERS 21.17 MAX. 1.0 MAX. 0.8 (T.P.) 0.32 +0.08 –0.07 0.1±0.05 1.2 MAX. 0.97 11.76±0.2 10.16±0.1 0.8±0.2 0.145 + 0.025 –0.015 0.5±0.1 0.13 0.10 7 3 +3 – P INCHES 0.834 MAX. 0.040 MAX. 0.031 (T.P.) 0.013±0.003 0.004±0.002 0.048 MAX. 0.038 0.463±0.008 0.400±0.004 0.031 +0.009 –0.008 0.006±0.001 0.020 +0.004 –0.005 0.005 0.004 7 3 +3 – S50G5-80-7JF4 Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 42 PD42S18165L, 4218165L 42 PIN PLASTIC SOJ (400 mil) B 42 22 C 1 21 E J F D G T H I K M N M Q P P42LE-400A NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM B C D E F G H I J K M N P Q T U MILLIMETERS 27.56 +0.2 –0.35 10.16 11.18 ± 0.2 1.08 ± 0.15 0.74 3.5 ± 0.2 2.545 ± 0.2 0.8 MIN. 2.6 1.27 (T.P.) 0.40 ± 0.10 0.12 9.4 ± 0.20 0.10 R 0.85 0.20 +0.10 –0.05 INCHES 1.085+0.008 –0.014 0.400 0.440 ± 0.008 0.043+0.006 –0.007 0.029 0.138 ± 0.008 0.100 ± 0.008 0.031 MIN. 0.102 0.050 (T.P.) 0.016 +0.004 –0.005 0.005 0.370 ± 0.008 0.004 R 0.033 0.008 +0.004 –0.002 U 43 PD42S18165L, 4218165L Recommended Soldering Conditions The following conditions (see tables below and next page) must be met for soldering conditions of the µ PD42S18165L, 4218165L. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. Types of Surface Mount Device µ PD42S18165LG5-7JF, 4218165LG5-7JF: 50-pin plastic TSOP (II) (400 mil) Soldering process Infrared ray reflow Soldering conditions Peak temperature of package surface: 235 °C or lower, Reflow time: 30 seconds or less (210 °C or higher), Number of reflow processes: MAX. 3 Exposure limit: 7 daysNote (10 hours pre-baking is required at 125 °C afterwards) VPS Peak temperature of package: 215 °C or lower, Reflow time: 40 seconds or less (200 °C or higher), Number of reflow processes: MAX. 3 Exposure limit: 7 daysNote (10 hours pre-baking is required at 125 °C afterwards) Partial heating method Terminal temperature: 300 °C or lower, Time: 3 seconds or lower (Per side of the package). – VP15-107-3 Symbol IR35-107-3 Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Caution Do not apply more than one soldering method at any one time, except for “Partial heating method”. 44 PD42S18165L, 4218165L µ PD42S18165LLE, 4218165LLE: 42-pin plastic SOJ (400 mil) Soldering process Infrared ray reflow Soldering conditions Peak temperature of package surface: 235 °C or lower, Reflow time: 30 seconds or less (210 °C or higher), Number of reflow processes: MAX. 3 Exposure limit: 7 daysNote (20 hours pre-baking is required at 125 °C afterwards) Peak temperature of package: 215 °C or lower, Reflow time: 40 seconds or less (200 °C or higher), Number of reflow processes: MAX. 3 Exposure limit: 7 daysNote (20 hours pre-baking is required at 125 °C afterwards) Terminal temperature: 300 °C or lower, Time: 3 seconds or less (Per side of the package). Symbol IR35-207-3 VPS VP15-207-3 Partial heating method – Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Caution Do not apply more than one soldering method at any one time, except for “Partial heating method”. 45 PD42S18165L, 4218165L [MEMO] 46 PD42S18165L, 4218165L NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 47 µPD42S18165L, 4218165L [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 48