UPD431000AGW-A10

DATA SHEET MOS INTEGRATED CIRCUIT µ PD431000A 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT Description The µPD431000A is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM. The µPD431000A has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. In addition to this, A and B versions are low voltage operations. The µPD431000A is packed in 32-pin PLASTIC DIP, 32-pin PLASTIC SOP and 32-pin PLASTIC TSOP (I) (8 × 13.4 mm) and (8 × 20 mm). Features • 131,072 words by 8 bits organization • Fast access time: 70, 85, 100, 120, 150 ns (MAX.) • Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) • Operating ambient temperature: TA = 0 to 70 °C • Low VCC data retention: 2.0 V (MIN.) • Output Enable input for easy application • Two Chip Enable inputs: /CE1, CE2 Part number Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C 0 to 70 At operating mA (MAX.) 70 Supply current At standby At data retention µA (MAX.) 100 20 µA (MAX.) Note1 15 3 µPD431000A-xxL µPD431000A-xxLL µPD431000A-Axx µPD431000A-Bxx 70 70 Note2 70, 85 4.5 to 5.5 Note2 , 100 3.0 to 5.5 2.7 to 5.5 35 30 Note3 Note4 13 11 Note5 Note6 , 100, 120, 150 Notes 1. TA ≤ 40 °C 2. VCC = 4.5 to 5.5 V 3. 70 mA (VCC > 3.6 V) 4. 70 mA (VCC > 3.3 V) 5. 20 µA (VCC > 3.6 V) 6. 20 µA (VCC > 3.3 V) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M11657EJBV0DS00 (11th edition) Date Published April 2002 NS CP (K) Printed in Japan The mark 5 shows major revised points. © 1990, 1993, 1995 µPD431000A Ordering Information Part number Package Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C 0 to 70 L version Remark µPD431000ACZ-70L µPD431000ACZ-85L µPD431000ACZ-70LL µPD431000ACZ-85LL µPD431000AGW-70L µPD431000AGW-85L µPD431000AGW-70LL µPD431000AGW-85LL µPD431000AGW-A10 µPD431000AGW-B12 µPD431000AGW-B15 µPD431000AGZ-85L-KJH µPD431000AGZ-70LL-KJH µPD431000AGZ-85LL-KJH µPD431000AGZ-B10-KJH µPD431000AGZ-B15-KJH µPD431000AGZ-70LL-KKH µPD431000AGZ-B15-KKH µPD431000AGU-B10-9JH µPD431000AGU-B12-9JH µPD431000AGU-B15-9JH µPD431000AGU-B10-9KH 32-pin PLASTIC DIP (15.24mm (600)) 70 85 70 85 4.5 to 5.5 LL version 32-pin PLASTIC SOP (13.34 mm (525)) 70 85 70 85 100 120 150 4.5 to 5.5 L version LL version 3.0 to 5.5 2.7 to 5.5 A version B version 32-pin PLASTIC TSOP(I) (8x20) (Normal bent) 85 70 85 100 150 4.5 to 5.5 L version LL version 2.7 to 5.5 B version 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent) 32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent) 70 150 100 120 150 4.5 to 5.5 2.7 to 5.5 2.7 to 5.5 LL version B version B version 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent) 100 2 Data Sheet M11657EJBV0DS µPD431000A Pin Configurations (Marking Side) /xxx indicates active low signal. 32-pin PLASTIC DIP (15.24 mm (600)) [µPD431000ACZ-xxL] [µPD431000ACZ-xxLL] NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 /WE A13 A8 A9 A11 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 A0 - A16 I/O1 - I/O8 /CE1, CE2 /WE /OE VCC GND NC : Address inputs : Data inputs / outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M11657EJBV0DS 3 µPD431000A 32-pin PLASTIC SOP (13.34 mm (525)) [µPD431000AGW-xxL] [µPD431000AGW-xxLL] [µPD431000AGW-Axx] [µPD431000AGW-Bxx] NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 /WE A13 A8 A9 A11 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 A0 - A16 I/O1 - I/O8 /CE1, CE2 /WE /OE VCC GND NC : Address inputs : Data inputs / outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M11657EJBV0DS µPD431000A 32-pin PLASTIC TSOP(I) (8x20) (Normal bent) [µPD431000AGZ-xxL-KJH] [µPD431000AGZ-xxLL-KJH] [µPD431000AGZ-Bxx-KJH] A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent) [µPD431000AGZ-xxLL-KKH] [µPD431000AGZ-Bxx-KKH] /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 A0 - A16 I/O1 - I/O8 /CE1, CE2 /WE /OE VCC GND NC : Address inputs : Data inputs / outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M11657EJBV0DS 5 µPD431000A 32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent) [µPD431000AGU-Bxx-9JH] A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent) [µPD431000AGU-Bxx-9KH] /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 A0 - A16 I/O1 - I/O8 /CE1, CE2 /WE /OE VCC GND NC : Address inputs : Data inputs / outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawings for the 1-pin index mark. 6 Data Sheet M11657EJBV0DS µPD431000A Block Diagram VCC GND A0 A16 Address buffer Row decoder Memory cell array 1,048,576 bits I/O1 I/O8 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /OE /WE Truth Table /CE1 H × L L L CE2 × L H H H /OE × × H L × /WE × × H H L Output disable Read Write DOUT DIN ICCA Mode Not selected I/O High impedance Supply current ISB Remark × : VIH or VIL Data Sheet M11657EJBV0DS 7 µPD431000A Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition –0.5 –0.5 Rating Note Unit V V °C °C to +7.0 Note to VCC + 0.5 0 to 70 –55 to +125 Note –3.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition µPD431000A-xxL µPD431000A-xxLL MIN. MAX. 5.5 VCC+0.5 +0.8 70 µPD431000A-Axx µPD431000A-Bxx Unit MIN. 3.0 2.2 –0.3 0 Note MAX. 5.5 VCC+0.5 +0.5 70 MIN. 2.7 2.2 –0.3 0 Note MAX. 5.5 VCC+0.5 +0.5 70 V V V °C Supply voltage High level input voltage Low level input voltage Operating ambient temperature VCC VIH VIL TA 4.5 2.2 –0.3 0 Note Note –3.0 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test conditions MIN. TYP. MAX. 6 10 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 8 Data Sheet M11657EJBV0DS µPD431000A DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition µPD431000A-xxL MIN. TYP. MAX. +1.0 µPD431000A-xxLL MIN. –1.0 TYP. MAX. +1.0 µPD431000A-Axx MIN. –1.0 TYP. MAX. +1.0 Unit Input leakage current I/O leakage current ILI VIN = 0 V to VCC –1.0 µA ILO VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, II/O = 0 mA Minimum cycle time VCC ≤ 3.6 V 40 70 40 70 40 70 mA – 15 – 10 – 15 – 10 35 15 8 10 ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ VCC ≤ 3.6 V ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.6 V – 3 – 2 100 – 2 100 – 2.4 – – 0.4 – – 1 – 1 – 3 – 20 – 20 – 2.4 2.4 VCC–0.1 8 3 2 1 0.5 1 0.5 20 13 20 13 V mA Standby supply current ISB /CE1 = VIH or CE2 = VIL VCC ≤ 3.6 V ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V VCC ≤ 3.6 V µA ISB2 CE2 ≤ 0.2 V VCC ≤ 3.6 V – 2.4 – – High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V IOH = –0.5 mA VOH2 Low level output voltage VOL2 VOL1 IOH = –0.02 mA IOL = 2.1 mA, VCC ≥ 4.5 V IOL = 1.0 mA IOL = 0.02 mA 0.4 – – 0.4 0.4 0.1 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless product classification. Data Sheet M11657EJBV0DS 9 µPD431000A DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, II/O = 0 mA Minimum cycle time ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CE1 = VIH or CE2 = VIL VCC ≤ 3.3 V ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V VCC ≤ 3.3 V ISB2 CE2 ≤ 0.2 V VCC ≤ 3.3 V High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V IOH = –0.5 mA VOH2 Low level output voltage VOL1 IOH = –0.02 mA IOL = 2.1 mA, VCC ≥ 4.5 V IOL = 1.0 mA VOL2 IOL = 0.02 mA 2.4 2.4 VCC–0.1 0.4 0.4 0.1 V 1 0.5 1 0.5 VCC ≤ 3.3 V 7 3 2 20 11 20 11 V mA VCC ≤ 3.3 V VCC ≤ 3.3 V 40 70 30 15 7 10 mA –1.0 –1.0 µPD431000A-Bxx TYP. MAX. +1.0 +1.0 Unit µA µA µA Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless product classification. 10 Data Sheet M11657EJBV0DS µPD431000A AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [µPD431000A-70L, µPD431000A-85L, µPD431000A-70LL, µPD431000A-85LL] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V 0.8 V Test points 1.5 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics should be measured with the following output load conditions. Figure 1 (tAA, tCO1, tCO2, tOE, tOH) +5 V Figure 2 (tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW ) +5 V 1.8 kΩ I/O (Output) 990 Ω 100 pF CL I/O (Output) 990 Ω 1.8 kΩ 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. [µPD431000A-A10, µPD431000A-B10, µPD431000A-B12, µPD431000A-B15] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V 0.5 V Test points 1.5 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics should be measured with the following output load conditions. Part number Output load condition tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW µPD431000A-A10, µPD431000A-B10, µPD431000A-B12 µPD431000A-B15 1TTL + 50 pF 1TTL + 100 pF 1TTL + 5 pF 1TTL + 5 pF Data Sheet M11657EJBV0DS 11 µPD431000A Read Cycle (1/2) Parameter Symbol VCC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition µPD431000A-70 µPD431000A-Axx µPD431000A-Bxx MIN. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 10 10 10 5 25 25 25 70 70 70 70 35 MAX. µPD431000A-85 µPD431000A-A10 MIN. 85 MAX. MIN. 100 MAX. ns 100 100 100 50 ns ns ns ns ns ns ns ns 35 35 35 ns ns ns Note 85 85 85 45 10 10 10 5 30 30 30 10 10 10 5 Note See the output load. Remark These AC characteristics are in common regardless of package types. Read Cycle (2/2) Parameter Symbol VCC ≥ 2.7 V Unit Condition µPD431000A-B10 MIN. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 10 10 10 5 35 35 35 100 100 100 100 50 MAX. µPD431000A-B12 MIN. 120 120 120 120 60 10 10 10 5 40 40 40 MAX. µPD431000A-B15 MIN. 150 150 150 150 70 10 10 10 5 50 50 50 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note Note See the output load. Remark These AC characteristics are in common regardless of package types. 12 Data Sheet M11657EJBV0DS µPD431000A Read Cycle Timing Chart tRC Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH CE2 (Input) tCO2 tLZ2 tHZ2 /OE (Input) tOE tOLZ I/O (Output) High impedance Data out tOHZ Remark In read cycle, /WE should be fixed to high level. Data Sheet M11657EJBV0DS 13 µPD431000A Write Cycle (1/2) Parameter ` Symbol VCC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition µPD431000A-70 µPD431000A-Axx µPD431000A-Bxx MIN. MAX. µPD431000A-85 µPD431000A-A10 MIN. 85 70 70 70 0 60 5 35 0 MAX. MIN. 100 80 80 80 0 60 0 60 0 MAX. ns ns ns ns ns ns ns ns ns 35 ns ns Note Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 70 55 55 55 0 50 5 35 0 25 5 30 5 5 Note See the output load. Remark These AC characteristics are in common regardless package types. Write Cycle (2/2) Parameter Symbol VCC ≥ 2.7 V Unit Condition µPD431000A-B10 MIN. Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 5 100 80 80 80 0 60 0 60 0 35 MAX. µPD431000A-B12 MIN. 120 100 100 100 0 85 0 60 0 40 5 MAX. µPD431000A-B15 MIN. 150 120 120 120 0 100 0 80 0 50 5 MAX. ns ns ns ns ns ns ns ns ns ns ns Note Note See the output load. Remark These AC characteristics are in common regardless of package types. 14 Data Sheet M11657EJBV0DS µPD431000A Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M11657EJBV0DS 15 µPD431000A Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tCW1 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 16 Data Sheet M11657EJBV0DS µPD431000A Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS CE2 (Input) tAW tWP /WE (Input) tCW2 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M11657EJBV0DS 17 µPD431000A Low VCC Data Retention Characteristics (TA = 0 to 70 °C) Parameter Symbol Test Condition µPD431000A-xxL µPD431000A-xxLL µPD431000A-Axx µPD431000A-Bxx Unit MIN. Data retention supply voltage VCCDR2 Data retention supply current ICCDR2 Chip deselection to data retention mode Operation recovery time tR 5 tCDR ICCDR1 VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V CE2 ≤ 0.2 V VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V VCC = 3.0 V, CE2 ≤ 0.2 V 0 2.0 2.0 TYP. MAX. 5.5 MIN. 2.0 TYP. MAX. 5.5 V 5.5 1 50 Note1 2.0 0.5 5.5 10 Note2 µA 1 50 Note1 0.5 0 10 Note2 ns 5 ms Notes 1. 15 µA (TA ≤ 40 °C) 2. 3 µA (TA ≤ 40 °C) 18 Data Sheet M11657EJBV0DS µPD431000A Data Retention Timing Chart (1) /CE1 Controlled tCDR VCC 4.5 V Note Data retention mode tR /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. (2) CE2 Controlled tCDR VCC 4.5 V Note Data retention mode tR VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M11657EJBV0DS 19 µPD431000A Package Drawings 32-PIN PLASTIC DIP (15.24mm(600)) 32 17 1 A J I 16 K P L F D H G N M C M B R NOTES 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N P R MILLIMETERS 40.64 MAX. 1.27 MAX. 2.54 (T.P.) 0.50 ± 0.10 1.1 MIN. 3.2 ± 0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 + 0.10 − 0.05 0.25 0.9 MIN. 0 - 15 ° P32C-100-600A-2 20 Data Sheet M11657EJBV0DS µPD431000A 32-PIN PLASTIC SOP (13.34 mm (525)) 32 17 detail of lead end P 1 A F G H I J 16 S N C D E NOTE S B K L M M ITEM A B C D E F G H I J K L M N P MILLIMETERS 20.61 MAX. 0.78 MAX. 1.27 (T.P.) 0.40+ 0.10 − 0.05 0.15 ± 0.05 2.95 MAX. 2.7 14.1 ± 0.3 11.3 1.4 ± 0.2 0.20 + 0.10 − 0.05 0.8 ± 0.2 0.12 0.10 3 °+ 7 ° −3° P32GW-50-525A-1 Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. Data Sheet M11657EJBV0DS 21 µPD431000A 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end 1 32 F G R Q 16 17 E L S P I J A S C D K MM B N S NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D E F G I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 0.97 ± 0.08 18.4 ± 0.1 0.8 ± 0.2 0.145 ± 0.05 0.5 0.10 0.10 20.0 ± 0.2 3 °+ 5 ° −3° 0.25 0.60 ± 0.15 S32GZ-50-KJH1-2 22 Data Sheet M11657EJBV0DS µPD431000A 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end E 1 32 Q S L R 16 17 F G D K N S S C MM B I P J A N OTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D E F G I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 0.97 ± 0.08 18.4 ± 0.1 0.8 ± 0.2 0.145 ± 0.05 0.5 0.10 0.10 20.0 ± 0.2 3° +5° −3° 0.25 0.60 ± 0.15 S32GZ-50-KKH1-2 Data Sheet M11657EJBV0DS 23 µPD431000A 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 S T R L 16 17 Q U P I J S A G H K C B M N S D M NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D G H I J K L M N P Q R S T U MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 1.0 ± 0.05 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 0.08 0.08 13.4 ± 0.2 0.1 ± 0.05 3° +5° −3° 1.2 MAX. 0.25 0.6 ± 0.15 P32GU-50-9JH-2 24 Data Sheet M11657EJBV0DS µPD431000A 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 Q R U L T 16 17 S K H N S D M C M B S G I P J A NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D G H I J K L M N P Q R S T U MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 1.0 ± 0.05 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 0.08 0.08 13.4 ± 0.2 0.1 ± 0.05 3° +5° −3° 1.2 MAX. 0.25 0.6 ± 0.15 P32GU-50-9KH-2 Data Sheet M11657EJBV0DS 25 µPD431000A Recommended Soldering Conditions The following conditions must be met when soldering conditions of the µPD431000A. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Types of Surface Mount Device µPD431000AGW-xxL µPD431000AGW-xxLL µPD431000AGW-Axx µPD431000AGW-Bxx : 32-pin PLASTIC SOP (13.34 mm (525)) : 32-pin PLASTIC SOP (13.34 mm (525)) : 32-pin PLASTIC SOP (13.34 mm (525)) : 32-pin PLASTIC SOP (13.34 mm (525)) µPD431000AGZ-xxL-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent) µPD431000AGZ-xxLL-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent) µPD431000AGZ-xxLL-KKH : 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent) µPD431000AGZ-Bxx-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent) µPD431000AGZ-Bxx-KKH : 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent) µPD431000AGU-Bxx-9JH : 32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent) µPD431000AGU-Bxx-9KH : 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent) Please consult with our sales offices. Types of Through Hole Mount Device µPD431000ACZ-xxL: 32-pin PLASTIC DIP (15.24 mm (600)) µPD431000ACZ-xxLL: 32-pin PLASTIC DIP (15.24 mm (600)) Soldering process Wave soldering (Only to leads) Partial heating method Soldering conditions Solder temperature: 260 °C or below, Flow time: 10 seconds or below Pin temperature : 300 °C or below, Time: 3 seconds or below (Per one lead) Caution Do not jet molten solder on the surface of package. 26 Data Sheet M11657EJBV0DS µPD431000A Revision History Edition/ Date 11th edition/ April 2002 Page This edition Throughout Previous edition Throughout Type of revision Location Description (Previous edition -> This edition) Addition Part number µPD431000AGZ-B10-KJH µPD431000AGU-B10-9JH µPD431000AGU-B10-9KH p. 2, 6, 25, 26 p. 2, 6, 25 Addition Package 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent) Data Sheet M11657EJBV0DS 27 µPD431000A [MEMO] 28 Data Sheet M11657EJBV0DS µPD431000A [MEMO] Data Sheet M11657EJBV0DS 29 µPD431000A [MEMO] 30 Data Sheet M11657EJBV0DS µPD431000A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M11657EJBV0DS 31 µPD431000A • The information in this document is current as of April, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4