UPD43256BGU-B12-A

DATA SHEET MOS INTEGRATED CIRCUIT μPD43256B 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT Description The μPD43256B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available. And A and B versions are wide voltage operations. The μPD43256B is packed in 28-pin PLASTIC DIP, 28-pin PLASTIC SOP and 28-pin PLASTIC TSOP (I) (8 x 13.4 mm). Features • 32,768 words by 8 bits organization • Fast access time: 70, 85, 100, 120, 150 ns (MAX.) • Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) • Low VCC data retention: 2.0 V (MIN.) • /OE input for easy application Part number Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C 0 to 70 At operating mA (MAX.) 45 Supply current At standby At data retention μA (MAX.) 50 15 μA (MAX.) Note1 3 2 μPD43256B-xxL μPD43256B-xxLL μPD43256B-Axx μPD43256B-Bxx Note2 70, 85 4.5 to 5.5 85, 100 Note2 , 120 Note2 3.0 to 5.5 2.7 to 5.5 100, 120, 150 Notes 1. TA ≤ 40 °C, VCC = 3.0 V 2. Access time: 85 ns (MAX.) (VCC = 4.5 to 5.5 V) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M10770EJEV0DS00 (14th edition) Date Published June 2006 NS CP (K) Printed in Japan 1990, 1993, 1994 μPD43256B Ordering Information Part number Package Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C 0 to 70 L version (1/2) Remark μPD43256BCZ-70L μPD43256BCZ-85L μPD43256BCZ-70LL μPD43256BCZ-85LL μPD43256BGU-70L μPD43256BGU-85L μPD43256BGU-70LL μPD43256BGU-85LL μPD43256BGU-A85 μPD43256BGU-A10 μPD43256BGU-A12 μPD43256BGU-B10 μPD43256BGU-B12 μPD43256BGW-70LL-9JL μPD43256BGW-85LL-9JL μPD43256BGW-A85-9JL μPD43256BGW-A10-9JL μPD43256BGW-A12-9JL μPD43256BGW-B10-9JL μPD43256BGW-B12-9JL μPD43256BGW-B15-9JL μPD43256BGW-70LL-9KL μPD43256BGW-85LL-9KL μPD43256BGW-A85-9KL μPD43256BGW-A10-9KL μPD43256BGW-A12-9KL μPD43256BGW-B10-9KL μPD43256BGW-B12-9KL μPD43256BGW-B15-9KL 28-pin PLASTIC DIP (15.24 mm (600)) 70 85 70 85 4.5 to 5.5 LL version 28-pin PLASTIC SOP (11.43 mm (450)) 70 85 70 85 85 100 120 100 120 2.7 to 5.5 3.0 to 5.5 L version LL version A version B version 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) 70 85 85 100 120 100 120 150 4.5 to 5.5 LL version 3.0 to 5.5 A version 2.7 to 5.5 B version 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) 70 85 85 100 120 100 120 150 4.5 to 5.5 LL version 3.0 to 5.5 A version 2.7 to 5.5 B version 2 Data Sheet M10770EJEV0DS μPD43256B (2/2) Part number Package Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C 0 to 70 L version Remark μPD43256BGU-70L-A μPD43256BGU-85L-A μPD43256BGU-70LL-A μPD43256BGU-85LL-A μPD43256BGU-A85-A μPD43256BGU-A10-A μPD43256BGU-A12-A μPD43256BGU-B10-A μPD43256BGU-B12-A μPD43256BGW-70LL-9JL-A μPD43256BGW-85LL-9JL-A μPD43256BGW-A85-9JL-A μPD43256BGW-A10-9JL-A μPD43256BGW-A12-9JL-A μPD43256BGW-B10-9JL-A μPD43256BGW-B12-9JL-A μPD43256BGW-B15-9JL-A 28-pin PLASTIC SOP (11.43 mm (450)) 70 85 70 85 85 100 120 100 120 4.5 to 5.5 LL version 3.0 to 5.5 A version 2.7 to 5.5 B version 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) 70 85 85 100 120 100 120 150 70 85 85 100 120 100 120 150 4.5 to 5.5 LL version 3.0 to 5.5 A version 2.7 to 5.5 B version μPD43256BGW-70LL-9KL-A 28-pin PLASTIC TSOP (I) μPD43256BGW-85LL-9KL-A (8x13.4) (Reverse bent) μPD43256BGW-A85-9KL-A μPD43256BGW-A10-9KL-A μPD43256BGW-A12-9KL-A μPD43256BGW-B10-9KL-A μPD43256BGW-B12-9KL-A μPD43256BGW-B15-9KL-A Remark 4.5 to 5.5 LL version 3.0 to 5.5 A version 2.7 to 5.5 B version Products with -A at the end of the part number are lead-free products. Data Sheet M10770EJEV0DS 3 μPD43256B Pin Configurations (Marking Side) /xxx indicates active low signal. 28-pin PLASTIC DIP (15.24 mm (600)) [ μPD43256BCZ-xxL ] [ μPD43256BCZ-xxLL ] A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 A0 - A14 I/O1 - I/O8 /CS /WE /OE VCC GND : Address inputs : Data inputs / outputs : Chip Select : Write Enable : Output Enable : Power supply : Ground Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M10770EJEV0DS μPD43256B 28-pin PLASTIC SOP (11.43 mm (450)) [ μPD43256BGU-xxL ] [ μPD43256BGU-xxLL ] [ μPD43256BGU-Axx ] [ μPD43256BGU-Bxx ] [ μPD43256BGU-xxL-A ] [ μPD43256BGU-xxLL-A ] [ μPD43256BGU-Axx-A ] [ μPD43256BGU-Bxx-A ] A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 A0 - A14 I/O1 - I/O8 /CS /WE /OE VCC GND : Address inputs : Data inputs / outputs : Chip Select : Write Enable : Output Enable : Power supply : Ground Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M10770EJEV0DS 5 μPD43256B 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) [ μPD43256BGW-xxLL-9JL ] [ μPD43256BGW-Axx-9JL ] [ μPD43256BGW-Bxx-9JL ] [ μPD43256BGW-xxLL-9JL-A ] [ μPD43256BGW-Axx-9JL-A ] [ μPD43256BGW-Bxx-9JL-A ] /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) [ μPD43256BGW-xxLL-9KL ] [ μPD43256BGW-Axx-9KL ] [ μPD43256BGW-Bxx-9KL ] [ μPD43256BGW-xxLL-9KL-A ] [ μPD43256BGW-Axx-9KL-A ] [ μPD43256BGW-Bxx-9KL-A ] A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 A0 - A14 I/O1 - I/O8 /CS /WE : : : : Address inputs Data inputs / outputs Chip Select Write Enable /OE VCC : Output Enable : Power supply Ground GND : Remark Refer to Package Drawings for the 1-pin index mark. 6 Data Sheet M10770EJEV0DS μPD43256B Block Diagram A0 A14 Address buffer Row decoder Memory cell array 262,144 bits I/O1 I/O8 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CS /OE /WE VCC GND Truth Table /CS H L L L /OE × H × L /WE × H L H Mode Not selected Output disable Write Read DIN DOUT I/O High impedance Supply current ISB ICCA Remark × : VIH or VIL Data Sheet M10770EJEV0DS 7 μPD43256B Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition Rating –0.5 –0.5 Note Unit V V °C °C to +7.0 Note to VCC + 0.5 0 to 70 –55 to +125 Note –3.0 V (MIN.) (Pulse width : 50 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition μPD43256B-xxL μPD43256B-xxLL MIN. MAX. 5.5 VCC+0.5 +0.8 70 μPD43256B-Axx μPD43256B-Bxx Unit MIN. 3.0 2.2 –0.3 0 Note MAX. 5.5 VCC+0.5 +0.5 70 MIN. 2.7 2.2 –0.3 0 Note MAX. 5.5 VCC+0.5 +0.5 70 V V V °C Supply voltage High level input voltage Low level input voltage Operating ambient temperature VCC VIH VIL TA 4.5 2.2 –0.3 0 Note Note –3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O Test conditions VIN = 0 V VI/O = 0 V MIN. TYP. MAX. 5 8 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. 8 Data Sheet M10770EJEV0DS μPD43256B DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition μPD43256B-xxL MIN. TYP. MAX. +1.0 +1.0 μPD43256B-xxLL MIN. –1.0 –1.0 TYP. MAX. +1.0 +1.0 Unit Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /OE = VIH or /CS = VIH or /WE = VIL –1.0 –1.0 μA μA Operating supply current ICCA1 ICCA2 ICCA3 /CS = VIL, Minimum cycle time, II/O = 0 mA /CS = VIL, II/O = 0 mA /CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V 45 10 10 45 10 10 mA Standby supply current ISB ISB1 /CS = VIH /CS ≥ VCC − 0.2 V IOH = –1.0 mA IOH = –0.1 mA IOL = 2.1 mA 2.4 VCC–0.5 3 1.0 50 2.4 VCC–0.5 3 0.5 15 mA μA V High level output voltage VOH1 VOH2 Low level output voltage VOL 0.4 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. Data Sheet M10770EJEV0DS 9 μPD43256B DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition μPD43256B-Axx MIN. TYP. MAX. +1.0 +1.0 μPD43256B-Bxx MIN. –1.0 –1.0 TYP. MAX. +1.0 +1.0 Unit Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /OE = VIH or /CS = VIH or /WE = VIL –1.0 –1.0 μA μA Operating supply current ICCA1 /CS = VIL, Minimum cycle time, II/O = 0 mA μPD43256B-Axx μPD43256B-Bxx VCC ≤ 3.3 V 45 – – 10 – 45 20 10 5 10 5 3 2 0.5 0.5 2.4 2.4 VCC–0.1 mA ICCA2 /CS = VIL, II/O = 0 mA VCC ≤ 3.3 V – 10 – 3 ICCA3 /CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V Standby supply current ISB /CS = VIH VCC ≤ 3.3 V mA – 0.5 15 – 2.4 2.4 VCC–0.1 ISB1 /CS ≥ VCC − 0.2 V VCC ≤ 3.3 V 15 10 μA High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V IOH = –0.5 mA, VCC < 4.5 V V VOH2 Low level output voltage VOL IOH = –0.02 mA IOL = 2.1 mA, VCC ≥ 4.5 V IOL = 1.0 mA, VCC < 4.5 V 0.4 0.4 0.1 0.4 0.4 0.1 V VOL1 IOL = 0.02 mA Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. 10 Data Sheet M10770EJEV0DS μPD43256B AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ μPD43256B-70L, μPD43256B-85L, μPD43256B-70LL, μPD43256B-85LL ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V 0.8 V Test points 1.5 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics should be measured with the following output load conditions. Figure 1 (tAA, tACS, tOE, tOH) +5 V Figure 2 (tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW) +5 V 1.8 kΩ I/O (Output) 990 Ω 100 pF CL I/O (Output) 990 Ω 1.8 kΩ 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. [ μPD43256B-A85, μPD43256B-A10, μPD43256B-A12, μPD43256B-B10, μPD43256B-B12, μPD43256B-B15 ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V 0.5 V Test points 1.5 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics should be measured with the following output load conditions. tAA, tACS, tOE, tOH 1TTL + 100 pF tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW 1TTL + 5 pF Data Sheet M10770EJEV0DS 11 μPD43256B Read Cycle (1/2) Parameter Symbol VCC ≥ 4.5 V Unit Condition μPD43256B-70 μPD43256B-85 μPD43256B-A85/A10/A12 μPD43256B-B10/B12/B15 MIN. Read cycle time Address access time /CS access time /OE access time Output hold from address change /CS to output in low impedance /OE to output in low impedance /CS to output in high impedance /OE to output in high impedance tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 10 10 5 70 MAX. MIN. 85 MAX. ns 85 85 40 ns ns ns ns ns ns 30 30 ns ns Note 70 70 35 10 10 5 30 30 Note See the output load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle (2/2) Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Condition μPD43256B -A85 μPD43256B -A10 μPD43256B -A12 μPD43256B -B10 μPD43256B -B12 μPD43256B -B15 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time Address access time /CS access time /OE access time Output hold from address change /CS to output in low impedance /OE to output in low impedance /CS to output in high impedance /OE to output in high impedance tOHZ 35 35 40 35 40 50 ns tCHZ 35 35 40 35 40 50 ns tOLZ 5 5 5 5 5 5 ns tCLZ 10 10 10 10 10 10 ns tACS tOE tOH 10 85 50 10 100 60 10 120 60 10 100 60 10 120 60 10 150 70 ns ns ns tRC tAA 85 85 100 100 120 120 100 100 120 120 150 150 ns ns Note Note See the output load. Remark These AC characteristics are in common regardless of package types. 12 Data Sheet M10770EJEV0DS μPD43256B Read Cycle Timing Chart tRC Address (Input) tAA /CS (Input) tACS tCLZ tCHZ tOH /OE (Input) tOE tOLZ I/O (Output) High impedance Data out tOHZ Remark In read cycle, /WE should be fixed to high level. Data Sheet M10770EJEV0DS 13 μPD43256B Write Cycle (1/2) Parameter Symbol VCC ≥ 4.5 V Unit Condition μPD43256B-70 μPD43256B-85 μPD43256B-A85/A10/A12 μPD43256B-B10/B12/B15 MIN. Write cycle time /CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup time Write recovery time /WE to output in high impedance Output active from end of write tWC tCW tAW tWP tDW tDH tAS tWR tWHZ tOW 10 70 50 50 55 30 0 0 0 MAX. MIN. 85 70 70 60 35 0 0 0 MAX. ns ns ns ns ns ns ns ns 30 ns ns Note 30 10 Note See the output load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Write Cycle (2/2) Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Con- μPD43256B -A85 μPD43256B -A10 μPD43256B -A12 μPD43256B -B10 μPD43256B -B12 μPD43256B -B15 dition MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time /CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup Write recovery /WE to output in high impedance Output active from end of write tOW 10 10 10 10 10 10 ns tDH tAS tWR tWHZ 0 0 0 30 0 0 0 35 0 0 0 40 0 0 0 35 0 0 0 40 0 0 0 50 ns ns ns ns Note tWP tDW 60 60 60 60 80 70 60 60 80 70 90 80 ns ns tWC tCW tAW 85 70 70 100 70 70 120 90 90 100 70 70 120 90 90 150 100 100 ns ns ns Note See the output load. Remark These AC characteristics are in common regardless of package types. 14 Data Sheet M10770EJEV0DS μPD43256B Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. 2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. Data Sheet M10770EJEV0DS 15 μPD43256B Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS /CS (Input) tAW tWP /WE (Input) tCW tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark Write operation is done during the overlap time of a low level /CS and a low level /WE. 16 Data Sheet M10770EJEV0DS μPD43256B Low VCC Data Retention Characteristics (TA = 0 to 70 °C) Parameter Symbol Test Condition μPD43256B-xxL μPD43256B-xxLL μPD43256B-Axx μPD43256B-Bxx Unit MIN. Data retention supply voltage Data retention supply current Chip deselection to data retention mode Operation recovery time tR 5 VCCDR ICCDR tCDR /CS ≥ VCC − 0.2 V VCC = 3.0 V, /CS ≥ VCC − 0.2 V 0 2.0 TYP. MAX. 5.5 MIN. 2.0 TYP. MAX. 5.5 V 0.5 20 Note1 0.5 0 7 Note2 μA ns 5 ms Notes 1. 3 μA (TA ≤ 40 °C) 2. 2 μA (TA ≤ 40 °C), 1 μA (TA ≤ 25 °C) Data Retention Timing Chart tCDR VCC 4.5 V Note Data retention mode tR /CS VIH (MIN.) VCCDR (MIN.) /CS ≥ VCC – 0.2 V VIL (MAX.) GND Note A version : 3.0 V, B version : 2.7 V Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state. Data Sheet M10770EJEV0DS 17 μPD43256B Package Drawings 28-PIN PLASTIC DIP (15.24 mm (600)) 28 15 1 A 14 J I K L F D H G NOTES C N M B M R 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. I TEM A B C D F G H I J K L M N R MILLIMETERS 38.10 MAX. 2.54 MAX. 2.54 (T.P.) 0.50 ± 0.10 1.2 MIN. 3.6 ± 0.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 + 0.10 − 0.05 0.25 0 - 15 ° P28C-100-600A1-2 18 Data Sheet M10770EJEV0DS μPD43256B 28-PIN PLASTIC SOP (11.43 mm (450)) 28 15 detail of lead end P 1 A F G 14 H I S J C D E NOTE N M S B K L M ITEM A B C D E F G H I J K L M N P MILLIMETERS 18.0 + 0.6 − 0.05 1.27 MAX. 1.27 (T.P.) 0.42 + 0.08 − 0.07 0.2 ± 0.1 2.95 MAX. 2.55 ± 0.1 11.8 ± 0.3 8.4 ± 0.1 1.7 ± 0.2 0.22 ± 0.05 0.7 ± 0.2 0.12 0.10 3° +7° −3° P28GU-50-450A-4 Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. Data Sheet M10770EJEV0DS 19 μPD43256B 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end S R 14 15 Q P I J S A G H L K N S D C M M B NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM A B C D G H I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.6 MAX. 0.55 (T.P.) 0.22 + 0.08 − 0.07 1.0 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 ± 0.1 0.08 0.10 13.4 ± 0.2 0.1 ± 0.05 3° +7° −3° 1.2 MAX. P28GW-55-9JL-2 20 Data Sheet M10770EJEV0DS μPD43256B 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end Q R 14 15 S K H N S L D M C M B S G I P J A NOTE 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM A B C D G H I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.6 MAX. 0.55 (T.P.) 0.22 + 0.08 − 0.07 1.0 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 ± 0.1 0.08 0.10 13.4 ± 0.2 0.1 ± 0.05 3° +7° −3° 1.2 MAX. P28GW-55-9KL-2 Data Sheet M10770EJEV0DS 21 μPD43256B Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the μPD43256B. Types of Surface Mount Device μPD43256BGU-xxL μPD43256BGU-xxLL μPD43256BGU-Axx μPD43256BGU-Bxx μPD43256BGW-xxLL-9JL μPD43256BGW-xxLL-9KL μPD43256BGW-Axx-9JL μPD43256BGW-Axx-9KL μPD43256BGW-Bxx-9JL μPD43256BGW-Bxx-9KL μPD43256BGU-xxL-A μPD43256BGU-xxLL-A μPD43256BGU-Axx-A μPD43256BGU-Bxx-A μPD43256BGW-xxLL-9JL-A μPD43256BGW-Axx-9JL-A μPD43256BGW-Axx-9KL-A μPD43256BGW-Bxx-9JL-A μPD43256BGW-Bxx-9KL-A : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) μPD43256BGW-xxLL-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) Types of Through Hole Mount Device μPD43256BCZ-xxL μPD43256BCZ-xxLL : 28-pin PLASTIC DIP (15.24 mm (600)) : 28-pin PLASTIC DIP (15.24 mm (600)) Soldering process Soldering conditions Solder temperature : 260 °C or below, Flow time : 10 seconds or below Wave soldering (only to leads) Partial heating method Terminal temperature : 300 °C or below, Time : 3 seconds or below (Per one lead) Caution Do not jet molten solder on the surface of package. 22 Data Sheet M10770EJEV0DS μPD43256B Revision History Edition/ Date This edition 14th edition/ Jun. 2006 p.1 Page Previous edition p.1 Deletion − Description of Version X and P has been deleted. Type of revision Location Description (Previous edition → This edition) Data Sheet M10770EJEV0DS 23 μPD43256B [ MEMO ] 24 Data Sheet M10770EJEV0DS μPD43256B [ MEMO ] Data Sheet M10770EJEV0DS 25 μPD43256B [ MEMO ] 26 Data Sheet M10770EJEV0DS μPD43256B N OTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet M10770EJEV0DS 27 μPD43256B • T he information in this document is current as of June, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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