UPD43256BGW-A10X-9JL

DATA SHEET MOS INTEGRATED CIRCUIT µPD43256B-X 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The µPD43256B-X is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. The µPD43256B-X is an extended-operating-temperature version of the µPD43256B (X version : TA = –25 to +85 °C). And A and B versions are low voltage operations. Battery backup is available. The µPD43256B-X is packed in 28-pin plastic TSOP (I) (8 x 13.4 mm). Features • 32,768 words by 8 bits organization • Fast access time: 70, 85, 100, 120, 150 ns (MAX.) • Operating ambient temperature: TA = –25 to +85 °C • Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) • Low VCC data retention: 2.0 V (MIN.) • /OE input for easy application Part number Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C −25 to +85 At operating mA (MAX.) 45 Supply current At standby At data retention µA (MAX.) 50 µA (MAX.) Note1 2 • µPD43256B-xxX µPD43256B-AxxX µPD43256B-BxxX Note2 70, 85 85 Note2, 100, 120 Note2 100, 120 Note2, 150 Note2 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 40 Notes 1. TA ≤ 40 °C, VCC = 3.0 V 2. 100 s (MAX.) (VCC = 4.5 to 5.5 V) Version X This Data sheet can be applied to the version X. Each version is identified with its lot number. Letter X in the fifth character position in a lot number signifies version X. JAPAN D43256B-X Lot number The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M11012EJ4V0DSJ1 (4th edition) Date Published December 2000 NS CP (K) Printed in Japan The mark 5 shows major revised points. © 1995 µPD43256B-X • Ordering Information Part number Package Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C –25 to +85 Remark µPD43256BGW-70X-9JL µPD43256BGW-85X-9JL µPD43256BGW-A85X-9JL µPD43256BGW-A10X-9JL µPD43256BGW-A12X-9JL µPD43256BGW-B10X-9JL µPD43256BGW-B12X-9JL µPD43256BGW-B15X-9JL µPD43256BGW-70X-9KL µPD43256BGW-85X-9KL µPD43256BGW-A85X-9KL µPD43256BGW-A10X-9KL µPD43256BGW-A12X-9KL µPD43256BGW-B10X-9KL µPD43256BGW-B12X-9KL µPD43256BGW-B15X-9KL 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) 70 85 85 100 120 100 120 150 4.5 to 5.5 3.0 to 5.5 A version 2.7 to 5.5 B version 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) 70 85 85 100 120 100 120 150 4.5 to 5.5 3.0 to 5.5 A version 2.7 to 5.5 B version 2 Data Sheet M11012EJ4V0DS µPD43256B-X • Pin Configurations (Marking Side) /xxx indicates active low signal. 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) [µPD43256BGW-xxX-9JL] [µPD43256BGW-AxxX-9JL] [µPD43256BGW-BxxX-9JL] /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) [µPD43256BGW-xxX-9KL] [µPD43256BGW-AxxX-9KL] [µPD43256BGW-BxxX-9KL] A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 A0 - A14 I/O1 - I/O8 /CS /WE /OE VCC GND : Address inputs : Data inputs / outputs : Chip Select : Write Enable : Output Enable : Power supply : Ground Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M11012EJ4V0DS 3 µPD43256B-X Block Diagram A0 A14 Address buffer Row decoder Memory cell array 262,144 bits I/O1 I/O8 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CS /OE /WE VCC GND Truth Table /CS H L L L /OE × H × L /WE × H L H Mode Not selected Output disable Write Read DIN DOUT I/O High impedance Supply current ISB ICCA Remark × : VIH or VIL 4 Data Sheet M11012EJ4V0DS µPD43256B-X Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition Rating –0.5 –0.5 Note Unit V V °C °C to +7.0 Note to VCC + 0.5 –25 to +85 –55 to +125 Note –3.0 V (MIN.) (Pulse width : 50 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition µPD43256B-xxX MIN. MAX. 5.5 VCC+0.5 +0.6 +85 µPD43256B-AxxX MIN. 3.0 2.4 –0.3 Note µPD43256B-BxxX MIN. 2.7 2.4 –0.3 Note Unit MAX. 5.5 VCC+0.5 +0.4 +85 MAX. 5.5 VCC+0.5 +0.4 +85 V V V °C Supply voltage High level input voltage Low level input voltage Operating ambient temperature VCC VIH VIL TA 4.5 2.4 –0.3 Note –25 –25 –25 Note –3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test conditions MIN. TYP. MAX. 5 8 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M11012EJ4V0DS 5 µPD43256B-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition µPD43256B-xxX MIN. TYP. MAX. +1.0 +1.0 Unit Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /OE = VIH or /CS = VIH or /WE = VIL –1.0 –1.0 µA µA • Operating supply current ICCA1 ICCA2 ICCA3 /CS = VIL, Minimum cycle time, II/O = 0 mA /CS = VIL, II/O = 0 mA /CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V 45 15 15 mA Standby supply current ISB ISB1 /CS = VIH /CS ≥ VCC − 0.2 V IOH = –1.0 mA IOH = –0.1 mA IOL = 2.1 mA 2.4 VCC–0.5 1.0 3 50 mA µA V High level output voltage VOH1 VOH2 Low level output voltage VOL 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. 6 Data Sheet M11012EJ4V0DS µPD43256B-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition µPD43256B-AxxX MIN. TYP. MAX. +1.0 +1.0 µPD43256B-BxxX MIN. –1.0 –1.0 TYP. MAX. +1.0 +1.0 Unit Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /OE = VIH or /CS = VIH or /WE = VIL –1.0 –1.0 µA µA Operating supply current ICCA1 /CS = VIL, µPD43256B-A85X 45 40 40 – – – – 15 – – – 40 40 40 25 15 10 15 10 3 2 1.0 50 25 2.4 2.4 VCC– 0.1 mA Minimum cycle time, µPD43256B-A10X II/O = 0 mA µPD43256B-A12X µPD43256B-B10X µPD43256B-B12X µPD43256B-B15X VCC ≤ 3.3 V ICCA2 /CS = VIL, II/O = 0 mA VCC ≤ 3.3 V – 15 – 3 ICCA3 /CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V Standby supply current ISB /CS = VIH VCC ≤ 3.3 V mA – 1.0 50 – 2.4 2.4 VCC– 0.1 ISB1 /CS ≥ VCC − 0.2 V VCC ≤ 3.3 V µA High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V IOH = –0.5 mA, VCC < 4.5 V V VOH2 IOH = –0.02 mA IOL = 2.1 mA, VCC ≥ 4.5 V IOL = 1.0 mA, VCC < 4.5 V Low level output voltage VOL 0.4 0.4 0.1 0.4 0.4 0.1 V VOL1 IOL = 0.02 mA Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. Data Sheet M11012EJ4V0DS 7 µPD43256B-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [µPD43256B-70X, µPD43256B-85X] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.4 V 1.5 V 0.6 V Test points 1.5 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics should be measured with the following output load conditions. Figure 1 (tAA, tACS, tOE, tOH) +5 V Figure 2 (tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW) +5 V 1.8 kΩ I/O (Output) 990 Ω 100 pF CL I/O (Output) 990 Ω 1.8 kΩ 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. [µPD43256B-A85X, µPD43256B-A10X, µPD43256B-A12X, µPD43256B-B10X, µPD43256B-B12X, µPD43256B-B15X] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.4 V 1.5 V 0.4 V Test points 1.5 V Output Waveform 1.5 V Test points 1.5 V • Output Load AC characteristics should be measured with the following output load conditions. tAA, tACS, tOE, tOH 1TTL + 50 pF tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW 1TTL + 5 pF 8 Data Sheet M11012EJ4V0DS µPD43256B-X Read Cycle (1/2) Parameter Symbol VCC ≥ 4.5 V Unit Condition • µPD43256B-70X µPD43256B-85X µPD43256B-AxxX µPD43256B-BxxX MIN. Read cycle time Address access time /CS access time /OE access time Output hold from address change /CS to output in low impedance /OE to output in low impedance /CS to output in high impedance /OE to output in high impedance tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 10 10 5 70 MAX. MIN. 85 MAX. MIN. 100 MAX. ns 100 100 50 ns ns ns ns ns ns 35 35 ns ns Note 70 70 35 10 10 5 30 30 85 85 40 10 10 5 30 30 Note See the output load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle (2/2) Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Con- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256BA85X A10X A12X B10X B12X B15X MIN. Read cycle time Address access time /CS access time /OE access time Output hold from address change /CS to output in low impedance /OE to output in low impedance /CS to output in high impedance /OE to output in high impedance tOHZ 35 35 40 35 40 50 ns tCHZ 35 35 40 35 40 50 ns tOLZ 5 5 5 5 5 5 ns tCLZ 10 10 10 10 10 10 ns tACS tOE tOH 10 85 50 10 100 60 10 120 60 10 100 60 10 120 60 10 150 70 ns ns ns tRC tAA 85 85 MAX. MIN. 100 100 MAX. MIN. 120 120 MAX. MIN. 100 100 MAX. MIN. 120 120 MAX. MIN. 150 150 MAX. ns ns dition Note Note See the output load. Remark These AC characteristics are in common regardless of package types. Data Sheet M11012EJ4V0DS 9 µPD43256B-X Read Cycle Timing Chart tRC Address (Input) tAA /CS (Input) tACS tCLZ tCHZ tOH /OE (Input) tOE tOLZ I/O (Output) High impedance Data out tOHZ Remark In read cycle, /WE should be fixed to high level. 10 Data Sheet M11012EJ4V0DS µPD43256B-X Write Cycle (1/2) Parameter Symbol VCC ≥ 4.5 V Unit Condition • µPD43256B-70X µPD43256B-85X µPD43256B-AxxX µPD43256B-BxxX MIN. Write cycle time /CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup time Write recovery time /WE to output in high impedance Output active from end of write tWC tCW tAW tWP tDW tDH tAS tWR tWHZ tOW 5 70 60 60 55 30 5 0 0 MAX. MIN. 85 70 70 60 35 5 0 0 MAX. MIN. 100 80 80 70 40 5 0 0 MAX. ns ns ns ns ns ns ns ns 35 ns ns Note 30 5 30 5 Note See the output load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Write Cycle (2/2) Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Con- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256BA85X A10X A12X B10X B12X B15X MIN. Write cycle time /CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup time Write recovery time /WE to output in high impedance Output active from end of write tOW 5 5 5 5 5 5 ns tDH tAS tWR tWHZ 5 0 0 35 5 0 0 35 5 0 0 40 5 0 0 35 5 0 0 40 5 0 0 40 ns ns ns ns tWP tDW 60 60 60 60 80 70 60 60 80 70 90 80 ns ns tWC tCW tAW 85 70 70 MAX. MIN. 100 70 70 MAX. MIN. 120 90 90 MAX. MIN. 100 70 70 MAX. MIN. 120 90 90 MAX. MIN. 150 100 100 MAX. ns ns ns dition Note Note See the output load. Remark These AC characteristics are in common regardless of package types. Data Sheet M11012EJ4V0DS 11 µPD43256B-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. 2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 12 Data Sheet M11012EJ4V0DS µPD43256B-X Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS /CS (Input) tAW tWP /WE (Input) tCW tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CS and a low level /WE. Data Sheet M11012EJ4V0DS 13 µPD43256B-X Low VCC Data Retention Characteristics (TA = −25 to +85 °C) Parameter Data retention supply voltage Data retention supply current Chip deselection to data retention mode Operation recovery time Symbol VCCDR ICCDR tCDR tR Test Condition /CS ≥ VCC − 0.2 V VCC = 3.0 V, /CS ≥ VCC − 0.2 V 0 5 MIN. 2.0 0.5 TYP. MAX. 5.5 20 Note Unit V µA ns ms Note 2 µA (TA ≤ 40 °C), 7 µA (TA ≤ 70 °C) Data Retention Timing Chart tCDR VCC 4.5 V Note Data retention mode tR /CS VIH (MIN.) VCCDR (MIN.) /CS ≥ VCC – 0.2 V VIL (MAX.) GND Note A version : 3.0 V, B version : 2.7 V Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state. 14 Data Sheet M11012EJ4V0DS µPD43256B-X • Package Drawings 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end S R 14 15 Q P I J S A G H L K N S D C M M B NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM A B C D G H I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.6 MAX. 0.55 (T.P.) 0.22 + 0.08 − 0.07 1.0 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 ± 0.1 0.08 0.10 13.4 ± 0.2 0.1 ± 0.05 3° +7° −3° 1.2 MAX. P28GW-55-9JL-2 Data Sheet M11012EJ4V0DS 15 µPD43256B-X 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end Q R 14 15 S K H N S L D M C M B S G I P J A NOTE 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM A B C D G H I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.6 MAX. 0.55 (T.P.) 0.22 + 0.08 − 0.07 1.0 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 ± 0.1 0.08 0.10 13.4 ± 0.2 0.1 ± 0.05 3° +7° −3° 1.2 MAX. P28GW-55-9KL-2 16 Data Sheet M11012EJ4V0DS µPD43256B-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD43256B-X. Types of Surface Mount Device µPD43256BGW-xxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) µPD43256BGW-xxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) µPD43256BGW-AxxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) µPD43256BGW-AxxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) µPD43256BGW-BxxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) µPD43256BGW-BxxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) Data Sheet M11012EJ4V0DS 17 µPD43256B-X [MEMO] 18 Data Sheet M11012EJ4V0DS µPD43256B-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M11012EJ4V0DS 19 µPD43256B-X • The information in this document is current as of December, 2000. The information is subject to change without notice. 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