UPD43257BCZ-85L

DATA SHEET MOS INTEGRATED CIRCUIT µPD43257B 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT Description The µPD43257B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available. And the µPD43257B has two chip enable pins (/CE1, CE2) to extend the capacity. The µPD43257B is packed in 28-pin plastic DIP and 28-pin plastic SOP. Features • 32,768 words by 8 bits organization • Fast access time: 70, 85 ns (MAX.) • Low VCC data retention: 2.0 V (MIN.) • Two Chip Enable inputs: /CE1, CE2 Part number Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C 0 to 70 At operating mA (MAX.) 45 45 Supply current At standby At data retention µA (MAX.) 50 15 µA (MAX.) Note 3 2 µPD43257B-xxL µPD43257B-xxLL 70, 85 4.5 to 5.5 Note TA ≤ 40 °C, VCC = 3.0 V Version X This Data sheet can be applied to the version X. This version is identified with its lot number. Letter X in the fifth character position in a lot number signifies version X. JAPAN D43257B X Lot number The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10693EJ7V0DS00 (7th edition) Date Published June 2000 NS CP (K) Printed in Japan The mark 5 shows major revised points. © 1992 µPD43257B Ordering Information Part number Package Access time ns (MAX.) Supply current µA (MAX.) At standby 50 At data retention 3 Note Remark µPD43257BCZ-70L µPD43257BCZ-85L µPD43257BCZ-70LL µPD43257BCZ-85LL µPD43257BGU-70L µPD43257BGU-85L µPD43257BGU-70LL µPD43257BGU-85LL 28-PIN PLASTIC DIP (15.24 mm (600)) 70 85 70 85 L version 15 2 LL version 28-PIN PLASTIC SOP (11.43 mm (450)) 70 85 70 85 50 3 L version 15 2 LL version Note TA ≤ 40 °C, VCC = 3.0 V 2 Data Sheet M10693EJ7V0DS00 µPD43257B Pin Configurations (Marking Side) /xxx indicates active low signal. 28-PIN PLASTIC DIP (15.24 mm (600)) [ µPD43257BCZ-xxL ] [ µPD43257BCZ-xxLL ] A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC /WE A13 A8 A9 A11 CE2 A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 A0 - A14 I/O1 - I/O8 /CE1 CE2 /WE VCC GND : Address inputs : Data inputs / outputs : Chip Enable 1 : Chip Enable 2 : Write Enable : Power supply : Ground Remark Refer to Package Drawings for the 1-pin marking. Data Sheet M10693EJ7V0DS00 3 µPD43257B 28-PIN PLASTIC SOP (11.43 mm (450)) [ µPD43257BGU-xxL ] [ µPD43257BGU-xxLL ] A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC /WE A13 A8 A9 A11 CE2 A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 A0 - A14 I/O1 - I/O8 /CE1 CE2 /WE VCC GND : Address inputs : Data inputs / outputs : Chip Enable 1 : Chip Enable 2 : Write Enable : Power supply : Ground Remark Refer to Package Drawings for the 1-pin marking. 4 Data Sheet M10693EJ7V0DS00 µPD43257B Block Diagram A0 A14 Address buffer Row decoder Memory cell array 262,144 bits I/O1 I/O8 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /WE VCC GND Truth Table /CE1 H × L L CE2 × L H H /WE × × H L Read Write DOUT DIN ICCA Mode Not selected I/O High impedance Supply current ISB Remark × : VIH or VIL Data Sheet M10693EJ7V0DS00 5 µPD43257B Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition Rating –0.5 –0.5 Note Unit V V °C °C to +7.0 Note to VCC + 0.5 0 to 70 –55 to +125 Note –3.0 V (MIN.) (Pulse width : 50 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 4.5 2.2 –0.3 0 Note TYP. 5.0 MAX. 5.5 VCC+0.5 +0.8 70 Unit V V V °C Note –3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O Test conditions VIN = 0 V VI/O = 0 V MIN. TYP. MAX. 5 8 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. 6 Data Sheet M10693EJ7V0DS00 µPD43257B DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition µPD43257B-xxL MIN. TYP. MAX. +1.0 µPD43257B-xxLL MIN. –1.0 TYP. MAX. +1.0 Unit Input leakage current I/O leakage current Operating supply current ILI VIN = 0 V to VCC –1.0 µA ILO VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL –1.0 +1.0 –1.0 +1.0 µA ICCA1 /CE1 = VIL, CE2 = VIH, Minimum cycle time, II/O = 0 mA µPD43257B-70 µPD43257B-85 45 45 10 10 45 45 10 10 mA ICCA2 ICCA3 /CE1 = VIL, CE2 = VIH, II/O = 0 mA /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB ISB1 ISB2 /CE1 = VIH or CE2 = VIL, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V CE2 ≤ 0.2 V IOH = –1.0 mA IOH = –0.1 mA IOL = 2.1 mA 2.4 VCC–0.5 1.0 1.0 3 50 50 2.4 VCC–0.5 0.4 0.5 0.5 3 15 15 mA µA High level output voltage Low level output voltage VOH1 VOH2 VOL V 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time. Data Sheet M10693EJ7V0DS00 7 µPD43257B AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD43257B-70L, µPD43257B-85L, µPD43257B-70LL, µPD43257B-85LL ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V 0.8 V Test points 1.5 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics with notes should be measured with the output load shown in Figure 1 and Figure 2. Figure 1 (tAA, tCO1, tCO2, tOH) +5 V Figure 2 (tLZ1, tLZ2, tHZ1, tHZ2, tWHZ, tOW) +5 V 1.8 kΩ I/O (Output) 990 Ω 100 pF CL I/O (Output) 990 Ω 1.8 kΩ 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. 8 Data Sheet M10693EJ7V0DS00 µPD43257B Read Cycle Parameter Symbol µPD43257B-70 MIN. MAX. µPD43257B-85 MIN. 85 MAX. Unit Condition Read cycle time Address access time /CE1 access time CE2 access time Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance tRC tAA tCO1 tCO2 tOH tLZ1 tLZ2 tHZ1 tHZ2 70 70 70 70 10 10 10 30 30 ns 85 85 85 ns ns ns ns ns ns 30 30 ns ns Note 2 Note 1 10 10 10 Notes 1. See the output load shown in Figure 1. 2. See the output load shown in Figure 2. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle Timing Chart tRC Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH CE2 (Input) tCO2 tLZ2 tHZ2 Data out I/O (Output) High impedance Remark In read cycle, /WE should be fixed to high level. Data Sheet M10693EJ7V0DS00 9 µPD43257B Write Cycle Parameter Symbol µPD43257B-70 MIN. MAX. µPD43257B-85 MIN. 85 70 70 70 0 65 0 35 0 MAX. Unit Condition Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 70 50 50 50 0 55 0 30 0 30 10 ns ns ns ns ns ns ns ns ns 30 ns ns Note 10 Note See the output load shown in Figure 2. Remark These AC characteristics are in common regardless of package types and L, LL versions. 10 Data Sheet M10693EJ7V0DS00 µPD43257B Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 5 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M10693EJ7V0DS00 11 µPD43257B Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tCW1 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 5 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 12 Data Sheet M10693EJ7V0DS00 µPD43257B Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS CE2 (Input) tAW tWP /WE (Input) tCW2 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 5 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M10693EJ7V0DS00 13 µPD43257B Low VCC Data Retention Characteristics (TA = 0 to 70 °C) Parameter Symbol Test Condition µPD43257B-xxL MIN. TYP. MAX. 5.5 µPD43257B-xxLL MIN. 2.0 TYP. MAX. 5.5 Unit Data retention supply voltage VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V CE2 ≤ 0.2 V VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V VCC = 3.0 V, CE2 ≤ 0.2 V 2.0 V VCCDR2 Data retention supply current ICCDR1 2.0 0.5 5.5 20 Note1 2.0 0.5 5.5 7 Note2 7 Note2 ns µA ICCDR2 Chip deselection to data retention mode Operation recovery time tCDR 0.5 0 20 Note1 0 0.5 tR 5 5 ms Notes 1. 3 µA (TA ≤ 40 °C) 2. 2 µA (TA ≤ 40 °C), 1 µA (TA ≤ 25 °C) 14 Data Sheet M10693EJ7V0DS00 µPD43257B Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR 5 VCC 4.5 V /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR 5 VCC 4.5 V VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE) can be in high impedance state. Data Sheet M10693EJ7V0DS00 15 µPD43257B 5 Package Drawings 28-PIN PLASTIC DIP (15.24 mm (600)) 28 15 1 A 14 J I K L F D H G NOTES C N M B M R 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 38.10 MAX. 2.54 MAX. 2.54 (T.P.) 0.50 ± 0.10 1.2 MIN. 3.6 ± 0.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 + 0.10 − 0.05 0.25 0 ∼ 15 ° P28C-100-600A1-2 16 Data Sheet M10693EJ7V0DS00 µPD43257B 28-PIN PLASTIC SOP (11.43 mm (450)) 28 15 detail of lead end P 1 A F G 14 H I S J C D E NOTE N M S B K L M ITEM A B C D E F G H I J K L M N P MILLIMETERS 18.0 + 0.6 − 0.05 1.27 MAX. 1.27 (T.P.) 0.42 + 0.08 − 0.07 0.2 ± 0.1 2.95 MAX. 2.55 ± 0.1 11.8 ± 0.3 8.4 ± 0.1 1.7 ± 0.2 0.22 ± 0.05 0.7 ± 0.2 0.12 0.10 3° +7° −3° P28GU-50-450A-4 Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. Data Sheet M10693EJ7V0DS00 17 µPD43257B Recommended Soldering Conditions The following conditions must be met when soldering µPD43257B. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Types of Surface Mount Device µPD43257BGU-xxL µPD43257BGU-xxLL : 28-PIN PLASTIC SOP (11.43 mm (450)) : 28-PIN PLASTIC SOP (11.43 mm (450)) Please consult with our sales offices. Types of Through Hole Mount Device µPD43257BCZ-xxL µPD43257BCZ-xxLL : 28-PIN PLASTIC DIP (15.24 mm (600)) : 28-PIN PLASTIC DIP (15.24 mm (600)) Soldering conditions Solder temperature : 260 °C or below, Flow time : 10 seconds or below Partial heating method Terminal temperature : 300 °C or below, Time : 3 seconds or below (Per one lead) Soldering process Wave soldering (only to leads) Caution Do not jet molten solder on the surface of package. 18 Data Sheet M10693EJ7V0DS00 µPD43257B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M10693EJ7V0DS00 19 µPD43257B • The information in this document is current as of June, 2000. The information is subject to change without notice. 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