UPD441000LGW-C12X

DATA SHEET MOS INTEGRATED CIRCUIT µPD441000L-X 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The µPD441000L-X is a high speed, low power, 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM. The µPD441000L-X has two chip enable pins (/CE1, CE2) to extend the capacity. 5 The µPD441000L-X is packed in 32-pin plastic SOP and 32-pin plastic TSOP (I) (8 ×13.4 mm) and (8×20 mm). Features • 131,072 words by 8 bits organization • Fast access time : 70, 85, 100, 120, 150 ns (MAX.) • Low voltage operation (B version : VCC = 2.7 to 3.6 V, C version : VCC = 2.2 to 3.6 V, D version : VCC = 1.8 to 3.6 V) • Low VCC data retention (B version : 2.0 V (MIN.), C version, D version : 1.5 V (MIN.)) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application • Two Chip Enable inputs : /CE1, CE2 Part number Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C −25 to +85 At operating mA (MAX.) 25 Supply current At standby At data retention µA (MAX.) 2 µA (MAX.) 2 Note µPD441000L-BxxX µPD441000L-CxxX µPD441000L-DxxX 70, 85, 100 100, 120 120, 150 2.7 to 3.6 2.2 to 3.6 1.8 to 3.6 Note 0.5 µA (TA ≤ 40 °C) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M13714EJ5V0DSJ1 (5th edition) Date Published December 2000 NS CP (K) Printed in Japan The mark • shows major revised points. © 1998 µPD441000L-X 5 Ordering Information Part number Package Access time ns (MAX.) Operating supply voltage V Operating temperature °C −25 to +85 B version Remark µPD441000LGW-B70X µPD441000LGW-B85X µPD441000LGW-B10X µPD441000LGU-B70X-9JH µPD441000LGU-B85X-9JH µPD441000LGU-B10X-9JH µPD441000LGU-B70X-9KH µPD441000LGU-B85X-9KH µPD441000LGU-B10X-9KH µPD441000LGZ-B70X-KJH µPD441000LGZ-B85X-KJH µPD441000LGZ-B10X-KJH µPD441000LGZ-B70X-KKH µPD441000LGZ-B85X-KKH µPD441000LGZ-B10X-KKH µPD441000LGW-C10X µPD441000LGW-C12X µPD441000LGU-C10X-9JH µPD441000LGU-C12X-9JH µPD441000LGU-C10X-9KH µPD441000LGU-C12X-9KH µPD441000LGZ-C10X-KJH µPD441000LGZ-C12X-KJH µPD441000LGZ-C10X-KKH µPD441000LGZ-C12X-KKH µPD441000LGW-D12X µPD441000LGW-D15X µPD441000LGU-D12X-9JH µPD441000LGU-D15X-9JH µPD441000LGU-D12X-9KH µPD441000LGU-D15X-9KH µPD441000LGZ-D12X-KJH µPD441000LGZ-D15X-KJH µPD441000LGZ-D12X-KKH µPD441000LGZ-D15X-KKH 32-pin Plastic SOP (13.34 mm (525)) 70 85 100 2.7 to 3.6 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) 70 85 100 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) 70 85 100 32-pin Plastic TSOP (I) (8×20) (Normal bent) 70 85 100 32-pin Plastic TSOP (I) (8×20) (Reverse bent) 70 85 100 32-pin Plastic SOP (13.34 mm (525)) 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) 32-pin Plastic TSOP (I) (8×20) (Normal bent) 32-pin Plastic TSOP (I) (8×20) (Reverse bent) 32-pin Plastic SOP (13.34 mm (525)) 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) 32-pin Plastic TSOP (I) (8×20) (Normal bent) 32-pin Plastic TSOP (I) (8×20) (Reverse bent) 100 120 100 120 100 120 100 120 100 120 120 150 120 150 120 150 120 150 120 150 2.2 to 3.6 C version 1.8 to 3.6 D version 2 Data Sheet M13714EJ5V0DS µPD441000L-X Pin Configurations (Marking Side) /xxx indicates active low signal. 32-pin Plastic SOP (13.34 mm (525)) [ µPD441000LGW-BxxX ] [ µPD441000LGW-CxxX ] [ µPD441000LGW-DxxX ] NC A16 A14 A12 A7 A6 A5 A4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 /WE A13 A8 A9 A11 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND A0 - A16 I/O1 - I/O8 /CE1, CE2 /WE /OE VCC GND NC : Address inputs : Data inputs / outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M13714EJ5V0DS 3 µPD441000L-X 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) [ µPD441000LGU-BxxX-9JH ] [ µPD441000LGU-CxxX-9JH ] [ µPD441000LGU-DxxX-9JH ] 32-pin Plastic TSOP (I) (8×20) (Normal bent) [ µPD441000LGZ-BxxX-KJH ] [ µPD441000LGZ-CxxX-KJH ] [ µPD441000LGZ-DxxX-KJH ] 5 A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 A0 - A16 I/O1 - I/O8 /CE1, CE2 /WE /OE VCC GND NC : Address inputs : Data inputs / outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M13714EJ5V0DS µPD441000L-X 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) [ µPD441000LGU-BxxX-9KH ] [ µPD441000LGU-CxxX-9KH ] [ µPD441000LGU-DxxX-9KH ] 32-pin Plastic TSOP (I) (8×20) (Reverse bent) [ µPD441000LGZ-BxxX-KKH ] [ µPD441000LGZ-CxxX-KKH ] [ µPD441000LGZ-DxxX-KKH ] 5 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 A0 - A16 I/O1 - I/O8 /CE1, CE2 /WE /OE VCC GND NC : Address inputs : Data inputs / outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M13714EJ5V0DS 5 µPD441000L-X Block Diagram A0 A16 Address buffer Row decoder Memory cell array 1,048,576 bits I/O1 Input data controller I/O8 Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /OE /WE VCC GND Truth Table /CE1 H × L L L CE2 × L H H H /OE × × H L × /WE × × H H L Mode Not selected Not selected Output disable Read Write I/O High impedance High impedance High impedance DOUT DIN ICCA Supply current ISB Remark × : VIH or VIL 6 Data Sheet M13714EJ5V0DS µPD441000L-X Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition Rating –0.5 –0.5 Note Unit V V °C °C to +4.6 Note to VCC+0.5 –25 to +85 –55 to +125 Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition µPD441000L-BxxX MIN. MAX. 3.6 VCC+0.5 – – Note µPD441000L-CxxX MIN. 2.2 2.4 2.0 – –0.3 Note µPD441000L-DxxX MIN. 1.8 2.4 2.0 1.6 –0.3 Note Unit MAX. 3.6 VCC+0.5 VCC+0.5 – +0.3 +85 MAX. 3.6 VCC+0.5 VCC+0.5 VCC+0.5 +0.2 +85 V °C V V Supply voltage High level input voltage VCC VIH 2.7 V ≤ VCC ≤ 3.6 V 2.2 V ≤ VCC < 2.7 V 1.8 V ≤ VCC < 2.2 V 2.7 2.4 – – –0.3 Low level input voltage Operating ambient temperature VIL TA +0.5 +85 –25 –25 –25 Note –3.0 V (MIN.) (Pulse width : 30 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O Test condition VIN = 0 V VI/O = 0 V MIN. TYP. MAX. 6 10 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M13714EJ5V0DS 7 µPD441000L-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition µPD441000L-BxxX µPD441000L-CxxX µPD441000L-DxxX Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Input leakage current I/O leakage current Operating supply current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA ILO VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA ICCA1 /CE1 = VIL, CE2 = VIH, Minimum cycle time, VCC ≤ 2.7 V II/O = 0 mA VCC ≤ 2.2 V 23 – – 25 – – 5 23 20 – 25 23 – 5 4 – 4 23 20 17 25 23 20 5 4 3 4 mA ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA VCC ≤ 2.7 V VCC ≤ 2.2 V – – 4 ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V – – 0.3 0.05 2 – – 2 – – 2.4 1.8 – 0.4 0.05 0.04 – 0.05 0.04 – 3 – 0.3 2 2 – 2 2 – 2.4 1.8 1.5 0.4 0.05 0.04 0.03 0.05 0.04 0.03 3 3 0.3 2 2 1.5 2 2 1.5 V mA Standby supply current ISB ISB1 /CE1 = VIH or CE2 = VIL /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V µA – – 0.05 ISB2 CE2 ≤ 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V – – 2.4 High level output voltage VOH IOH = –0.5 mA VCC ≤ 2.7 V VCC ≤ 2.2 V – – Low level output voltage VOL IOL = 1.0 mA 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time. 8 Data Sheet M13714EJ5V0DS µPD441000L-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD441000L-B70X, µPD441000L-B85X, µPD441000L-B10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.4 V 1.5 V 0.5 V Test Points 1.5 V Output Waveform 1.5 V Test Points 1.5 V Output Load 1TTL + 50 pF [ µPD441000L-C10X, µPD441000L-C12X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.0 V 1.1 V 0.3 V Test Points 1.1 V Output Waveform 1.1 V Test Points 1.1 V Output Load 1TTL + 30 pF [ µPD441000L-D12X, µPD441000L-D15X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 1.6 V 0.9 V 0.2 V Test Points 0.9 V Output Waveform 0.9 V Test Points 0.9 V Output Load 1TTL + 30 pF Data Sheet M13714EJ5V0DS 9 µPD441000L-X Read Cycle (1/3) (B version) Parameter Symbol µPD441000L-B70X µPD441000L-B85X µPD441000L-B10X MIN. MAX. MIN. 85 70 70 70 35 10 10 10 5 25 25 25 10 10 10 5 30 30 30 85 85 85 45 10 10 10 5 35 35 35 MAX. MIN. 100 100 100 100 50 MAX. Unit Condition Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 70 ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Read Cycle (2/3) (C version) Parameter Symbol µPD441000L-C10X MIN. MAX. µPD441000L-C12X MIN. 120 MAX. Unit Condition Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 100 100 100 100 50 10 10 10 5 35 35 35 ns 120 120 120 60 ns ns ns ns ns ns ns ns 40 40 40 ns ns ns Note 2 Note 1 10 10 10 5 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. 10 Data Sheet M13714EJ5V0DS µPD441000L-X Read Cycle (3/3) (D version) Parameter Symbol µPD441000L-D12X MIN. MAX. µPD441000L-D15X MIN. 150 MAX. Unit Condition Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 120 120 120 120 60 10 10 10 5 40 40 40 ns 150 150 150 70 ns ns ns ns ns ns ns ns 50 50 50 ns ns ns Note 2 Note 1 10 10 10 5 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Read Cycle Timing Chart tRC Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH CE2 (Input) tCO2 tLZ2 tHZ2 /OE (Input) tOE tOLZ I/O (Output) High impedance Data out tOHZ Remark In read cycle, /WE should be fixed to high level. Data Sheet M13714EJ5V0DS 11 µPD441000L-X Write Cycle (1/3) (B version) Parameter Symbol µPD441000L-B70X µPD441000L-B85X µPD441000L-B10X MIN. MAX. MIN. 85 70 70 70 0 60 0 35 0 25 5 5 30 5 MAX. MIN. 100 80 80 80 0 60 0 40 0 35 MAX. Unit Condition Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 70 55 55 55 0 50 0 35 0 ns ns ns ns ns ns ns ns ns ns ns Note Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Write Cycle (2/3) (C version) Parameter Symbol µPD441000L-C10X MIN. MAX. µPD441000L-C12X MIN. 120 100 100 100 0 85 0 60 0 MAX. Unit Condition Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 100 80 80 80 0 60 0 45 0 35 5 ns ns ns ns ns ns ns ns ns 40 ns ns Note 5 Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. 12 Data Sheet M13714EJ5V0DS µPD441000L-X Write Cycle (3/3) (D version) Parameter Symbol µPD441000L-D12X MIN. MAX. µPD441000L-D15X MIN. 150 120 120 120 0 100 0 80 0 MAX. Unit Condition Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 120 100 100 100 0 85 0 60 0 40 5 ns ns ns ns ns ns ns ns ns 50 ns ns Note 5 Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Data Sheet M13714EJ5V0DS 13 µPD441000L-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 14 Data Sheet M13714EJ5V0DS µPD441000L-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tCW1 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. Data Sheet M13714EJ5V0DS 15 µPD441000L-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS CE2 (Input) tAW tWP /WE (Input) tCW2 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. 16 Data Sheet M13714EJ5V0DS µPD441000L-X Low VCC Data Retention Characteristics (TA = –25 to +85 °C) Parameter Symbol Test Condition µPD441000L -BxxX µPD441000L -CxxX µPD441000L -DxxX Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention supply voltage VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V CE2 ≤ 0.2 V VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V VCC = 3.0 V, CE2 ≤ 0.2 V 0 5 2 3.6 1.5 3.6 1.5 3.6 V VCCDR2 Data retention supply current ICCDR1 2 3.6 0.05 2 Note 1.5 3.6 0.05 2 Note 1.5 3.6 Note 0.05 2 µA ICCDR2 Chip deselection to data retention mode Operation recovery time tCDR tR Note 0.05 2 Note 0.05 2 Note 0.05 2 0 5 0 5 ns ms Note 0.5 µA (TA ≤ 40 °C) Data Sheet M13714EJ5V0DS 17 µPD441000L-X Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR 5 VCC VCC (MIN.) Note /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. Remark (2) CE2 Controlled tCDR Data retention mode tR 5 VCC VCC (MIN.) Note VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state. 18 Data Sheet M13714EJ5V0DS µPD441000L-X Package Drawings 5 32-PIN PLASTIC SOP (13.34 mm (525)) 32 17 detail of lead end P 1 A F G H I J 16 S N C D E NOTE S B K L M M ITEM A B C D E F G H I J K L M N P MILLIMETERS 20.61 MAX. 0.78 MAX. 1.27 (T.P.) 0.40+ 0.10 − 0.05 0.15 ± 0.05 2.95 MAX. 2.7 14.1 ± 0.3 11.3 1.4 ± 0.2 0.20 + 0.10 − 0.05 0.8 ± 0.2 0.12 0.10 +7° 3 °− 3 ° P32GW-50-525A-1 Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. Data Sheet M13714EJ5V0DS 19 µPD441000L-X 5 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 S T R L 16 17 Q U P I J S A G H K C B M N S D M NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D G H I J K L M N P Q R S T U MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 1.0 ± 0.05 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 0.08 0.08 13.4 ± 0.2 0.1 ± 0.05 +5° 3° −3° 1.2 MAX. 0.25 0.6 ± 0.15 P32GU-50-9JH-2 20 Data Sheet M13714EJ5V0DS µPD441000L-X 5 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 Q R U L T 16 17 S K H N S D M C M B S G I P J A NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D G H I J K L M N P Q R S T U MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 1.0 ± 0.05 12.4 ± 0.2 11.8 ± 0.1 0.8 ± 0.2 0.145 + 0.025 − 0.015 0.5 0.08 0.08 13.4 ± 0.2 0.1 ± 0.05 3° +5° −3° 1.2 MAX. 0.25 0.6 ± 0.15 P32GU-50-9KH-2 Data Sheet M13714EJ5V0DS 21 µPD441000L-X 5 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end 1 32 F G R Q 16 17 E L S P I J A S C D K MM B N S NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D E F G I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 0.97 ± 0.08 18.4 ± 0.1 0.8 ± 0.2 0.145 ± 0.05 0.5 0.10 0.10 20.0 ± 0.2 +5° 3 °− 3 ° 0.25 0.60 ± 0.15 S32GZ-50-KJH1-2 22 Data Sheet M13714EJ5V0DS µPD441000L-X 5 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end E 1 32 Q S L R 16 17 F G D K N S S C MM B I P J A NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM A B C D E F G I J K L M N P Q R S MILLIMETERS 8.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 0.97 ± 0.08 18.4 ± 0.1 0.8 ± 0.2 0.145 ± 0.05 0.5 0.10 0.10 20.0 ± 0.2 +5° 3° −3° 0.25 0.60 ± 0.15 S32GZ-50-KKH1-2 Data Sheet M13714EJ5V0DS 23 µPD441000L-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD441000L-X. 5 Types of Surface Mount Device µPD441000LGW-BxxX µPD441000LGW-CxxX µPD441000LGW-DxxX µPD441000LGU-BxxX-9JH µPD441000LGU-CxxX-9JH µPD441000LGU-DxxX-9JH µPD441000LGU-BxxX-9KH µPD441000LGU-CxxX-9KH µPD441000LGU-DxxX-9KH µPD441000LGZ-BxxX-KJH µPD441000LGZ-CxxX-KJH µPD441000LGZ-DxxX-KJH µPD441000LGZ-BxxX-KKH µPD441000LGZ-CxxX-KKH µPD441000LGZ-DxxX-KKH : 32-pin Plastic SOP (13.34 mm (525)) : 32-pin Plastic SOP (13.34 mm (525)) : 32-pin Plastic SOP (13.34 mm (525)) : 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) : 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) : 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) : 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) : 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) : 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) : 32-pin Plastic TSOP (I) (8×20) (Normal bent) : 32-pin Plastic TSOP (I) (8×20) (Normal bent) : 32-pin Plastic TSOP (I) (8×20) (Normal bent) : 32-pin Plastic TSOP (I) (8×20) (Reverse bent) : 32-pin Plastic TSOP (I) (8×20) (Reverse bent) : 32-pin Plastic TSOP (I) (8×20) (Reverse bent) 24 Data Sheet M13714EJ5V0DS µPD441000L-X [ MEMO ] Data Sheet M13714EJ5V0DS 25 µPD441000L-X [ MEMO ] 26 Data Sheet M13714EJ5V0DS µPD441000L-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M13714EJ5V0DS 27 µPD441000L-X • The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4