UPD44164082F5-E50-EQ1

DATA SHEET MOS INTEGRATED CIRCUIT µPD44164082, 44164182, 44164362 18M-BIT DDRII SRAM 2-WORD BURST OPERATION Description The µPD44164082 is a 2,097,152-word by 8-bit, the µPD44164182 is a 1,048,576-word by 18-bit and the µPD44164362 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44164082, µPD44164182 and µPD44164362 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA. Features • 1.8 ± 0.1 V power supply and HSTL I/O • DLL circuitry for wide output data valid window and future frequency scaling • Pipelined double data rate operation • Common data input/output bus • Two-tick burst for low DDR transaction size • Two input clocks (K and /K) for precise DDR timing at clock rising edges only • Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability with µs restart • User programmable impedance output • Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz) • Simple control logic for easy depth expansion • JTAG boundary scan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M15821EJ7V2DS00 (7th edition) Date Published August 2004 NS CP(K) Printed in Japan The mark shows major revised points. 2001 µPD44164082, 44164182, 44164362 Ordering Information Part number Cycle Time ns Clock Frequency MHz 250 200 167 250 200 167 200 167 512 K x 36-bit 1 M x 18-bit 2 M x 8-bit Organization (word x bit) Core Supply Voltage V 1.8 ± 0.1 HSTL 165-pin PLASTIC BGA (13 x 15) I/O Interface Package µPD44164082F5-E40-EQ1 µPD44164082F5-E50-EQ1 µPD44164082F5-E60-EQ1 µPD44164182F5-E40-EQ1 µPD44164182F5-E50-EQ1 µPD44164182F5-E60-EQ1 µPD44164362F5-E50-EQ1 µPD44164362F5-E60-EQ1 4.0 5.0 6.0 4.0 5.0 6.0 5.0 6.0 2 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 Pin Configurations /××× indicates active low signal. 165-pin PLASTIC BGA (13 x 15) (Top View) [µPD44164082F5-EQ1] 1 A B C D E F G H J K L M N P R /CQ NC NC NC NC NC NC /DLL NC NC NC NC NC NC TDO 2 VSS NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R, /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 /NW1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 NC /NW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 VSS NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI A DQ0 to DQ7 /LD R, /W /NW0, /NW1 K, /K C, /C CQ, /CQ ZQ /DLL : Address inputs : Data inputs / outputs : Synchronous load : Read Write input : Nibble Write data select : Input clock : Output clock : Echo clock : Output impedance matching : DLL disable TMS TDI TCK TDO VREF VDD VDDQ VSS NC : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection Remark Refer to Package Drawing for the index mark. Data Sheet M15821EJ7V2DS 3 µPD44164082, 44164182, 44164362 165-pin PLASTIC BGA (13 x 15) (Top View) [µPD44164182F5-EQ1] 1 A B C D E F G H J K L M N P R /CQ NC NC NC NC NC NC /DLL NC NC NC NC NC NC TDO 2 VSS DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 A NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 A 4 R, /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 /BW1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 NC /BW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 VSS NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI A0, A DQ0 to DQ17 /LD R, /W /BW0, /BW1 K, /K C, /C CQ, /CQ ZQ /DLL : Address inputs : Data inputs / outputs : Synchronous load : Read Write input : Byte Write data select : Input clock : Output clock : Echo clock : Output impedance matching : DLL disable TMS TDI TCK TDO VREF VDD VDDQ VSS NC : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection Remark Refer to Package Drawing for the index mark. 4 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 165-pin PLASTIC BGA (13 x 15) (Top View) [µPD44164362F5-EQ1] 1 A B C D E F G H J K L M N P R /CQ NC NC NC NC NC NC /DLL NC NC NC NC NC NC TDO 2 VSS DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 NC DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A 4 R, /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 /BW2 /BW3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 /BW1 /BW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 VSS NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI A0, A DQ0 to DQ35 /LD R, /W /BW0 to /BW3 K, /K C, /C CQ, /CQ ZQ /DLL : Address inputs : Data inputs / outputs : Synchronous load : Read Write input : Byte Write data select : Input clock : Output clock : Echo clock : Output impedance matching : DLL disable TMS TDI TCK TDO VREF VDD VDDQ VSS NC : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection Remark Refer to Package Drawing for the index mark. Data Sheet M15821EJ7V2DS 5 µPD44164082, 44164182, 44164362 Pin Identification Symbol A0 A Description Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Balls 3A, 10A, and 2A are reserved for the next higher-order address inputs on future devices. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used as the lowest order address bit permitting a random starting address within the burst operation. These inputs are ignored when device is deselected. DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and /K. Output data is synchronized to the respective C and /C data clocks or to K and /K if C and /C are tied to HIGH. x8 device uses DQ0 to DQ7. x18 device uses DQ0 to DQ17. x36 device uses DQ0 to DQ35. /LD Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus activity). R, /W Synchronous Read/Write Input: When /LD is LOW, this input designates the access type (READ when R, /W is HIGH, WRITE when R, /W is LOW) for the loaded address. R, /W must meet the setup and hold times around the rising edge of K. /BWx /NWx Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data relationships. K, /K Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. C, /C Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for first output data. The rising edge of C is used as the output reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation. CQ, /CQ Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. This pin cannot be connected directly to GND or left unconnected. Also, in this product, there is no function to minimize the output impedance by connecting ZQ directly to VDDQ. /DLL TMS TDI TCK TDO VREF VDD VDDQ VSS NC DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation. IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not used in the circuit. IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the circuit. IEEE 1149.1 Test Output: 1.8V I/O level. HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range. Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics and Operating Conditions for range. Power Supply: Ground No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation. 6 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 Block Diagram CLK A0 Burst Logic D0 Q0 A0' R Address /LD E Address Register /W Compare /C C K E Write address Register A0' Input Register A0'' Output control A0''' Logic E /A0' 0 2 :1 MUX ZQ WRITE Register Output Register WRITE Driver Sense Amps A0' CLK /A0' A0' Memory Array K 1 Output Buffer E DQ 0 /K E Input Register 1 A0''' Output Enable Register C R, /W E R, /W Register Data Sheet M15821EJ7V2DS 7 µPD44164082, 44164182, 44164362 Burst Sequence Linear Burst Sequence Table [µPD44164182, µPD44164362] A0 External Address 1st Internal Burst Address 0 1 A0 1 0 Truth Table Operation WRITE cycle Load address, input write data on two consecutive K and /K rising edge READ cycle Load address, read data on two consecutive C and /C rising edge NOP (No operation) STANDBY(Clock stopped) H X X X L→H Stopped L H L→H /LD L R, /W L CLK L→H DQ Data in Input data Input clock Data out Output data Output clock High-Z Previous state Q(A1) /C(t+1) ↑ Q(A2) C(t+2) ↑ D(A1) K(t+1) ↑ D(A2) /K(t+1) ↑ Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges. 3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of K. All control inputs are registered during the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst address in accordance with the linear burst sequence. 7. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 8 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 Byte Write Operation [µPD44164082] Operation Write DQ0 to DQ7 Write DQ0 to DQ3 Write DQ4 to DQ7 Write nothing K L→H – L→H – L→H – L→H – /K – L→H – L→H – L→H – L→H /NW0 0 0 0 0 1 1 1 1 /NW1 0 0 1 1 0 0 1 1 Remark H : High level, L : Low level, → : rising edge. [µPD44164182] Operation Write DQ0 to DQ17 Write DQ0 to DQ8 Write DQ9 to DQ17 Write nothing K L→H – L→H – L→H – L→H – /K – L→H – L→H – L→H – L→H /BW0 0 0 0 0 1 1 1 1 /BW1 0 0 1 1 0 0 1 1 Remark H : High level, L : Low level, → : rising edge. [µPD44164362] Operation Write DQ0 to DQ35 Write DQ0 to DQ8 Write DQ9 to DQ17 Write DQ18 to DQ26 Write DQ27 to DQ35 Write nothing K L→H – L→H – L→H – L→H – L→H – L→H – /K – L→H – L→H – L→H – L→H – L→H – L→H /BW0 0 0 0 0 1 1 1 1 1 1 1 1 /BW1 0 0 1 1 0 0 1 1 1 1 1 1 /BW2 0 0 1 1 1 1 0 0 1 1 1 1 /BW3 0 0 1 1 1 1 1 1 0 0 1 1 Remark H : High level, L : Low level, → : rising edge. Data Sheet M15821EJ7V2DS 9 µPD44164082, 44164182, 44164362 Bus Cycle State Diagram LOAD NEW ADDRESS Count = 0 Load, Count = 2 Load, Count = 2 Read Write READ DOUBLE Count = Count + 2 WRITE DOUBLE Count = Count + 2 NOP, Count = 2 NOP, Count = 2 Load NOP NOP Power UP Supply voltage provided Remarks 1. A0 is internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 2. 2. State machine control timing sequence is controlled by K. 10 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Output supply voltage Input voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VDD VDDQ VIN VI/O TA Tstg Conditions MIN. –0.5 –0.5 –0.5 –0.5 0 –55 TYP. MAX. +2.9 VDD VDD + 0.5 (2.9 V MAX.) VDDQ + 0.5 (2.9 V MAX.) 70 +125 Unit V V V V °C °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70 °C) Parameter Supply voltage Output supply voltage High level input voltage Low level input voltage Clock input voltage Reference voltage Symbol VDD VDDQ VIH (DC) VIL (DC) VIN VREF Conditions MIN. 1.7 1.4 VREF + 0.1 –0.3 –0.3 0.68 TYP. MAX. 1.9 VDD VDDQ + 0.3 VREF – 0.1 VDDQ + 0.3 0.95 Unit V V V V V V 1 1, 2 1, 2 1, 2 Note Notes 1. During normal operation, VDDQ must not exceed VDD. 2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms Recommended AC Operating Conditions (TA = 0 to 70 °C) Parameter High level input voltage Low level input voltage Symbol VIH (AC) VIL (AC) Conditions MIN. VREF + 0.2 – TYP. MAX. – VREF – 0.2 Unit V V Note 1 1 Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2 Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2 Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than TKHKH (MIN.). Data Sheet M15821EJ7V2DS 11 µPD44164082, 44164182, 44164362 DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V) Parameter Symbol Test condition MIN. TYP. MAX. x8, x18 Input leakage current I/O leakage current Operating supply current (Read Write cycle) ILI ILO IDD VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Cycle = MAX. Standby supply current (NOP) ISB1 VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Cycle = MAX. High level output voltage VOH(Low) |IOH| ≤ 0.1 mA VOH Low level output voltage Note1 –E40 –E50 –E60 –E40 –E50 –E60 VDDQ – 0.2 VDDQ/2 – 0.12 VSS VDDQ/2 – 0.12 – – – – –2 –2 – – 650 550 480 320 270 250 VDDQ VDDQ/2 + 0.12 0.2 VDDQ/2 + 0.12 V V V V 3, 4 3, 4 3, 4 3, 4 +2 +2 – 650 570 – mA x36 Unit Note µA µA mA VOL(Low) IOL ≤ 0.1 mA VOL Note2 Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 3. AC load current is higher than the shown DC values. 4. HSTL outputs meet JEDEC HSTL Class I and Class II standards. Capacitance (TA = 25 °C, f = 1MHz) Parameter Input capacitance Input / Output capacitance Clock Input capacitance Symbol CIN CI/O Cclk Test conditions VIN = 0 V VI/O = 0 V Vclk = 0 V MIN. TYP. 4 6 5 MAX. 5 7 6 Unit pF pF pF Remark These parameters are periodically sampled and not 100% tested. 12 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 AC Characteristics (TA = 0 to 70 °C, VDD = 1.8 ± 0.1 V) AC Test Conditions Input waveform (Rise / Fall time ≤ 0.3 ns) 1.25 V 0.75 V 0.25 V Test Points 0.75 V Output waveform VDDQ / 2 Test Points VDDQ / 2 Output load condition Figure 1. External load at test VDDQ / 2 0.75 V VREF SRAM 250 Ω ZQ ZO = 50 Ω 50 Ω Data Sheet M15821EJ7V2DS 13 µPD44164082, 44164182, 44164362 Read and Write Cycle Parameter Symbol MIN. Clock Average Clock cycle time (K, /K, C, /C) Clock phase jitter (K, /K, C, /C) Clock HIGH time (K, /K, C, /C) Clock LOW time (K, /K, C, /C) Clock to /clock (K→/K., C→/C.) Clock to /clock (/K→K., /C→C.) Clock to data clock (K→C., /K→/C.) 200 to 250 MHz 167 to 200 MHz 133 to 167 MHz < 133 MHz DLL lock time (K, C) K static to DLL reset Output Times C, /C HIGH to output valid C, /C HIGH to output hold C, /C HIGH to echo clock valid C, /C HIGH to echo clock hold CQ, /CQ HIGH to output valid CQ, /CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z Setup Times Address valid to K rising edge Synchronous load input (/LD), read write input (R, /W) valid to K rising edge Data inputs and write data select inputs (/BWx, /NWx) valid to K, /K rising edge Hold Times K rising edge to address hold K rising edge to synchronous load input (/LD), read write input (R, /W) hold K, /K rising edge to data inputs and write data select inputs (/BWx, /NWx) hold TKHDX 0.35 – 0.4 – 0.5 – -E40 (250 MHz) MAX. 8.4 0.2 – – – – 1.8 2.3 2.8 3.55 – – -E50 (200 MHz) MIN. 5.0 – 2.0 2.0 2.2 2.2 – 0 0 0 1,024 30 -E60 (167 MHz) MIN. 6.0 – 2.4 2.4 2.7 2.7 – – 0 0 1,024 30 Unit MAX. 8.4 0.2 – – – – – – 2.8 3.55 – – Note MAX. 8.4 0.2 – – – – – 2.3 2.8 3.55 – – TKHKH TKC var TKHKL TKLKH TKH /KH T /KHKH TKHCH 4.0 – 1.6 1.6 1.8 1.8 0 0 0 0 ns ns ns ns ns ns ns 1 2 TKC lock TKC reset 1,024 30 Cycle ns 3 TCHQV TCHQX TCHCQV TCHCQX TCQHQV TCQHQX TCHQZ TCHQX1 – –0.45 – –0.45 – –0.3 – –0.45 0.45 – 0.45 – 0.3 – 0.45 – – –0.45 – –0.45 – –0.35 – –0.45 0.45 – 0.45 – 0.35 – 0.45 – – –0.5 – –0.5 – –0.4 – –0.5 0.5 – 0.5 – 0.4 – 0.5 – ns ns ns ns ns ns ns ns 4 4 TAVKH TIVKH 0.5 0.5 – – 0.6 0.6 – – 0.7 0.7 – – ns ns 5 5 TDVKH 0.35 – 0.4 – 0.5 – ns 5 TKHAX TKHIX 0.5 0.5 – – 0.6 0.6 – – 0.7 0.7 – – ns ns 5 5 ns 5 14 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.). 2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations. 5. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. Remarks 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.). 4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters. 5. VDDQ is 1.5 V DC. Data Sheet M15821EJ7V2DS 15 µPD44164082, 44164182, 44164362 Read and Write Timing NOP READ NOP READ (burst of 2) (burst of 2) NOP READ WRITE WRITE (burst of 2) (burst of 2) (burst of 2) 1 K 2 TKHKH 3 4 5 6 7 8 9 10 TKHKL TKLKH TKLKH TKH/KH T/KHKH /K /LD TIVKH TKHIX R, /W TAVKH TKHAX Address A0 A1 A2 A3 TKHDX TDVKH A4 TKHDX TDVKH DQ Qx2 TCHQX1 TKHCH TKHCH TCHQV Q01 Q02 Q11 Q12 D21 D22 D31 D32 Q41 Q42 TCQHQX TCHQX TCHQV TCHQZ TCHQX TCQHQV CQ TCHCQX TCHCQV /CQ TCHCQX TCHCQV C TKHKL TKLKH TKHKH TKH/KH T/KHKH /C Remarks 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disable (high impedance) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. 16 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name TCK TMS TDI Pin assignments 2R 10R 11R Test Clock Input. Description All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test Mode Select. This is the command input for the TAP controller state machine. Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP. JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted) Parameter JTAG Input leakage current JTAG I/O leakage current Symbol ILI ILO Conditions 0 V ≤ VIN ≤ VDD 0 V ≤ VIN ≤ VDDQ, Outputs disabled JTAG input high voltage JTAG input low voltage JTAG output high voltage VIH VIL VOH1 VOH2 JTAG output low voltage VOL1 VOL2 | IOHC | = 100 µA | IOHT | = 2 mA IOLC = 100 µA IOLT = 2 mA 1.3 –0.3 1.6 1.4 – – – – – – – – VDD + 0.3 +0.5 – – 0.2 0.4 V V V V V V MIN. –5.0 –5.0 TYP. – – MAX. +5.0 +5.0 Unit Note µA µA Data Sheet M15821EJ7V2DS 17 µPD44164082, 44164182, 44164362 JTAG AC Test Conditions Input waveform (Rise / Fall time ≤ 1 ns) 1.8 V 0.9 V 0V Test Points 0.9 V Output waveform 0.9 V Test Points 0.9 V Output load Figure 2. External load at test VTT = 0.9 V 50 Ω ZO = 50 Ω TDO 20 pF 18 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 JTAG AC Characteristics (TA = 0 to 70 °C) Parameter Clock Clock cycle time Clock frequency Clock high time Clock low time tTHTH fTF tTHTL tTLTH 100 – 40 40 – – – – – 10 – – ns MHz ns ns Symbol Conditions MIN. TYP. MAX. Unit Note Output time TCK low to TDO unknown TCK low to TDO valid TDI valid to TCK high TCK high to TDI invalid tTLOX tTLOV tDVTH tTHDX 0 – 10 10 – – – – – 20 – – ns ns ns ns Setup time TMS setup time Capture setup time tMVTH tCS 10 10 – – – – ns ns Hold time TMS hold time Capture hold time tTHMX tCH 10 10 – – – – ns ns JTAG Timing Diagram tTHTH TCK tMVTH tTHTL tTLTH TMS tTHMX tDVTH TDI tTHDX tTLOV tTLOX TDO Data Sheet M15821EJ7V2DS 19 µPD44164082, 44164182, 44164362 Scan Register Definition (1) Register name Instruction register Description The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit’s position in the boundary register. The second column is the name of the input or I/O at the bump and the third column is the bump number. Scan Register Definition (2) Register name Instruction register Bypass register ID register Boundary register Bit size 3 1 32 107 Unit bit bit bit bit ID Register Definition Part number Organization ID [31:28] vendor revision no. 2M x 8 1M x 18 512K x 36 XXXX XXXX XXXX ID [27:12] part no. 0000 0000 0001 0010 0000 0000 0001 0011 0000 0000 0001 0100 ID [11:1] vendor ID no. 00000010000 00000010000 00000010000 ID [0] fix bit 1 1 1 µPD44164082 µPD44164182 µPD44164362 20 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 SCAN Exit Order Bit no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC NC NC NC NC NC NC NC NC NC NC NC NC Signal name x8 x18 /C C A A A A A A A DQ0 DQ0 NC NC NC DQ9 NC NC x36 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H NC NC 10G 9G 11F 11G 9F 10F 11E 10E Bit no. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC NC NC NC NC NC NC A NC NC A Signal name x8 NC NC NC NC NC NC DQ3 NC NC NC x18 NC NC x36 NC NC Bump ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal Bit no. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 x8 NC DQ4 NC NC NC NC NC NC NC DQ5 NC NC NC NC NC NC NC DQ6 NC NC NC NC NC NC NC DQ7 NC NC NC Signal name x18 NC x36 NC Bump ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R DQ11 DQ20 NC NC NC DQ29 NC NC DQ7 DQ17 NC NC NC DQ8 NC NC NC CQ – A A A A0 /LD NC /BW1 A0 DQ16 NC NC DQ8 DQ7 NC NC DQ12 DQ30 NC NC NC DQ21 NC NC DQ13 DQ22 NC NC NC DQ31 NC NC 9A 8B 7C 6C 8A 7A 7B 6B 6A /BW3 5B 5A 4A 5C 4B NC 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D DQ1 DQ11 NC NC NC DQ10 NC NC DQ14 DQ23 NC NC NC DQ32 NC NC DQ0 DQ2 DQ2 NC NC NC NC NC NC NC NC NC NC DQ1 NC NC DQ15 DQ33 NC NC NC DQ24 NC NC /NW0 /BW0 /BW0 K /K NC DQ3 DQ3 NC NC NC DQ12 NC NC DQ16 DQ25 NC NC NC DQ34 NC NC /NW1 /BW1 /BW2 R, /W A A A /DLL /CQ DQ9 DQ27 NC NC NC DQ18 NC NC DQ1 DQ4 DQ13 NC NC ZQ NC NC DQ4 DQ17 DQ26 NC NC NC A A A A A A DQ35 NC NC DQ5 DQ5 NC NC NC DQ14 NC NC DQ10 DQ19 NC NC DQ28 NC DQ2 DQ6 DQ6 NC NC DQ15 Data Sheet M15821EJ7V2DS 21 µPD44164082, 44164182, 44164362 JTAG Instructions Instructions EXTEST Description The EXTEST instruction allows circuitry external to the component package to be tested. Boundaryscan register cells at output pins are used to apply test vectors, while those at input pins capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output pins. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are forced to an inactive drive state (high impedance) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. JTAG Instruction Coding IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED SAMPLE / PRELOAD RESERVED RESERVED BYPASS 1 Note Note 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH. 22 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 TAP Controller State Diagram 1 Test-Logic-Reset 0 1 1 Select-DR-Scan 0 1 Capture-DR 0 1 Capture-IR 0 Select-IR-Scan 0 1 0 Run-Test / Idle Shift-DR 1 1 Exit1-DR 0 0 Shift-IR 1 1 Exit1-IR 0 0 Pause-DR 1 0 Exit2-DR 1 0 Pause-IR 1 0 Exit2-IR 1 0 Update-DR 1 0 Update-IR 1 0 Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor. TDO should be left unconnected. Data Sheet M15821EJ7V2DS 23 µ µ µPD44164082, 44164182, 44164362 µ Run-Test/Idle Update-IR Exit1-IR Shift-IR Exit2-IR Exit1-IR Shift-IR Capture-IR Select-IR-Scan Select-DR-Scan Run-Test/Idle Test Logic Operation (Instruction Scan) IDCODE Pause-IR New Instruction Test-Logic-Reset TDI Controller state 24 Data Sheet M15821EJ7V2DS Instruction Register state TDO TMS TCK Output Inactive µ µ µPD44164082, 44164182, 44164362 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR Capture-DR Select-DR-Scan Instruction IDCODE Run-Test/Idle Test Logic (Data Scan) TDI Output Inactive Controller state Instruction Register state TDO TMS TCK Data Sheet M15821EJ7V2DS 25 µPD44164082, 44164182, 44164362 Package Drawing 165-PIN PLASTIC BGA (13x15) E wSB ZD B ZE A D 11 10 9 8 7 6 5 4 3 2 1 R PMM L K J H G F E D C BA INDEX MARK wSA A y1 S A2 S y S e A1 (UNIT:mm) ITEM D E w e A A1 A2 b x y y1 ZD ZE DIMENSIONS 13.00 ± 0.10 15.00 ± 0.10 0.15 1.00 1.40 ± 0.11 0.40 ± 0.05 1.00 0.50 ± 0.05 0.08 0.10 0.20 1.50 0.50 P165F5-100-EQ1 φb φx M S AB 26 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices µPD44164082F5-EQ1: 165-pin PLASTIC BGA (13 x 15) µPD44164182F5-EQ1: 165-pin PLASTIC BGA (13 x 15) µPD44164362F5-EQ1: 165-pin PLASTIC BGA (13 x 15) Data Sheet M15821EJ7V2DS 27 µPD44164082, 44164182, 44164362 Revision History Edition/ Date This edition 7th edition/ Feb. 2004 Page Previous edition Deletion Ordering Information Type of revision Location Description (Previous edition → This edition) Throughout Throughout µPD44164362F5-E40-EQ1 p.12 p.12 Modification DC Characteristics IDD (MAX.) MAX. x8, x18 -E40 -E50 -E60 600 500 430 x36 TBD 600 520 Unit MAX. x8, x18 x36 − 650 570 Unit mA -E40 -E50 -E60 650 550 480 mA DC Characteristics ISB1 (MAX.) MAX. x8, x18 -E40 -E50 -E60 250 210 190 x36 Unit MAX. x8, x18 x36 − 270 250 Unit mA -E40 -E50 -E60 320 mA p.26 p.26 Modification Package Drawing Preliminary version → Standardized version 28 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 [MEMO] Data Sheet M15821EJ7V2DS 29 µPD44164082, 44164182, 44164362 [MEMO] 30 Data Sheet M15821EJ7V2DS µPD44164082, 44164182, 44164362 N OTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet M15821EJ7V2DS 31 µPD44164082, 44164182, 44164362 • T he information in this document is current as of August, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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