DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44165082, 44165182, 44165362
18M-BIT QDRTMII SRAM 2-WORD BURST OPERATION
Description
The µPD44165082 is a 2,097,152-word by 8-bit, the µPD44165182 is a 1,048,576-word by 18-bit and the
µPD44165362 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell. The µPD44165082, µPD44165182 and µPD44165362 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply and HSTL I/O • DLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation • Two-tick burst for low DDR transaction size • Two input clocks (K and /K) for precise DDR timing at clock rising edges only • Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability with µs restart • User programmable impedance output • Fast clock cycle time : 5.0 ns (200 MHz), 6.0 ns (167 MHz), 7.5 ns (133 MHz) • Simple control logic for easy depth expansion • JTAG boundary scan
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Document No. M15824EJ7V1DS00 (7th edition) Date Published July 2004 NS CP(K) Printed in Japan
The mark
shows major revised points.
2001
µPD44165082, 44165182, 44165362
Ordering Information
Part number Cycle Time ns Clock Frequency MHz 200 167 133 200 167 133 200 167 133 512 K x 36-bit 1 M x 18-bit 2 M x 8-bit Organization Core Supply (word x bit) Voltage V 1.8 ± 0.1 HSTL 165-pin PLASTIC BGA (13 x 15) I/O Interface Package
µPD44165082F5-E50-EQ1 µPD44165082F5-E60-EQ1 µPD44165082F5-E75-EQ1 µPD44165182F5-E50-EQ1 µPD44165182F5-E60-EQ1 µPD44165182F5-E75-EQ1 µPD44165362F5-E50-EQ1 µPD44165362F5-E60-EQ1 µPD44165362F5-E75-EQ1
5.0 6.0 7.5 5.0 6.0 7.5 5.0 6.0 7.5
2
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
Pin Configurations
/××× indicates active low signal. 165-pin PLASTIC BGA (13 x 15) (Top View) [µPD44165082F5-EQ1] 1 A B C D E F G H J K L M N P R /CQ NC NC NC NC NC NC /DLL NC NC NC NC NC NC TDO 2 VSS NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A 4 /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 /NW1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 NC /NW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /R A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 VSS NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
A D0 to D7 Q0 to Q7 /R /W /NW0, /NW1 K, /K C, /C CQ, /CQ ZQ /DLL
: Address inputs : Data inputs : Data outputs : Read input : Write input : Nibble Write data select : Input clock : Output clock : Echo clock : Output impedance matching : DLL disable
TMS TDI TCK TDO VREF VDD VDDQ VSS NC
: IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection
Remark Refer to Package Drawing for the index mark.
Data Sheet M15824EJ7V1DS
3
µPD44165082, 44165182, 44165362
165-pin PLASTIC BGA (13 x 15) (Top View) [µPD44165182F5-EQ1] 1 A B C D E F G H J K L M N P R /CQ NC NC NC NC NC NC /DLL NC NC NC NC NC NC TDO 2 VSS Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 /BW1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 NC /BW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /R A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 VSS NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
A D0 to D17 Q0 to Q17 /R /W /BW0, /BW1 K, /K C, /C CQ, /CQ ZQ /DLL
: Address inputs : Data inputs : Data outputs : Read input : Write input : Byte Write data select : Input clock : Output clock : Echo clock : Output impedance matching : DLL disable
TMS TDI TCK TDO VREF VDD VDDQ VSS NC
: IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection
Remark Refer to Package Drawing for the index mark.
4
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
165-pin PLASTIC BGA (13 x 15) (Top View) [µPD44165362F5-EQ1] 1 A B C D E F G H J K L M N P R /CQ Q27 D27 D28 Q29 Q30 D30 /DLL D31 Q32 Q33 D33 D34 Q35 TDO 2 VSS Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 /BW2 /BW3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 /BW1 /BW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /R A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 NC D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 VSS Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
A D0 to D35 Q0 to Q35 /R /W /BW0 to /BW3 K, /K C, /C CQ, /CQ ZQ /DLL
: Address inputs : Data inputs : Data outputs : Read input : Write input : Byte Write data select : Input clock : Output clock : Echo clock : Output impedance matching : DLL disable
TMS TDI TCK TDO VREF VDD VDDQ VSS NC
: IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection
Remark Refer to Package Drawing for the index mark.
Data Sheet M15824EJ7V1DS
5
µPD44165082, 44165182, 44165362
Pin Identification
Symbol A Description Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of /K for WRITE cycles. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on future devices. All transactions operate on a burst of two words (one clock period of bus activity). These inputs are ignored when device is deselected. D0 to Dxx Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Configurations for ball site location of individual signals. x8 device uses D0 to D7. x18 device uses D0 to D17. x36 device uses D0 to D35. Q0 to Qxx Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site location of individual signals. x8 device uses Q0 to Q7. x18 device uses Q0 to Q17. x36 device uses Q0 to Q35. /R /W /BWx /NWx Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data relationships. K, /K Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. C, /C Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for first output data. The rising edge of C is used as the output reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation. CQ, /CQ Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. This pin cannot be connected directly to GND or left unconnected. Also, in this product, there is no function to minimize the output impedance by connecting ZQ directly to VDDQ. /DLL TMS TDI TCK TDO VREF VDD VDDQ VSS NC DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation. IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not used in the circuit. IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the circuit. IEEE 1149.1 Test Output: 1.8V I/O level. HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range. Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics and Operating Conditions for range. Power Supply: Ground No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.
6
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
Block Diagrams
[µPD44165082]
20 ADDRESS /R ADDRESS /W REGISTRY & LOGIC K /K 20
/W /NW0
WRITE REGISTER
OUTPUT REGISTER
/NW1 D0 to D7 /R 8
DATA REGISTRY & LOGIC
16
2 x 16 MEMORY ARRAY
20
OUTPUT BUFFER
WRITE DRIVER
OUTPUT SELECT
SENSE AMPS
16 MUX
16
8 Q0 to Q7 2 CQ, /CQ
K /K K K C, /C OR K, /K
[µPD44165182]
19
ADDRESS
/R
ADDRESS
19
/W
REGISTRY & LOGIC
K
/K
/W
/BW0
WRITE REGISTER
/BW1
18
DATA REGISTRY & LOGIC
36
2 x 36 MEMORY ARRAY
19
OUTPUT REGISTER
WRITE DRIVER
SENSE AMPS
OUTPUT BUFFER
OUTPUT SELECT
36
36
18
D0 to D17
MUX
Q0 to Q17
2 CQ, /CQ
/R
K
/K
K
K
C, /C OR K, /K
[µPD44165362]
18
ADDRESS
/R
ADDRESS
18
/W
REGISTRY & LOGIC
K
/K
/W
/BW0 /BW1 /BW2 /BW3
D0 to D35
36
OUTPUT REGISTER
WRITE REGISTER
DATA REGISTRY & LOGIC
72
2 x 72 MEMORY ARRAY
18
WRITE DRIVER
OUTPUT BUFFER
OUTPUT SELECT
SENSE AMPS
72
72
36
MUX
Q0 to Q35
2 CQ, /CQ
/R
K
/K
K
K
C, /C OR K, /K
Data Sheet M15824EJ7V1DS
7
µPD44165082, 44165182, 44165362
Truth Table
Operation WRITE cycle Load address, input write data on consecutive K and /K rising edge READ cycle Load address, output data on consecutive C and /C rising edge NOP (No operation) STANDBY(Clock stopped) L→H Stopped H X H X L→H L X CLK L→H /R X /W L D or Q Data in Input data Input clock Data out Output data Output clock D=X or Q=High-Z Previous state QA (A+0) /C(t+1) ↑ QA (A+1) C(t+2) ↑ DA (A+0) K( t ) ↑ DA (A+1) /K( t ) ↑
Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges. 3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of K. All control inputs are registered during the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically.
8
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
Byte Write Operation [µPD44165082]
Operation Write D0 to D7 Write D0 to D3 Write D4 to D7 Write nothing K L→H – L→H – L→H – L→H – /K – L→H – L→H – L→H – L→H /NW0 0 0 0 0 1 1 1 1 /NW1 0 0 1 1 0 0 1 1
Remarks 1. H : High level, L : Low level, → : rising edge. 2. Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
[µPD44165182]
Operation Write D0 to D17 Write D0 to D8 Write D9 to D17 Write nothing K L→H – L→H – L→H – L→H – /K – L→H – L→H – L→H – L→H /BW0 0 0 0 0 1 1 1 1 /BW1 0 0 1 1 0 0 1 1
Remarks 1. H : High level, L : Low level, → : rising edge. 2. Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. [µPD44165362]
Operation Write D0 to D35 Write D0 to D8 Write D9 to D17 Write D18 to D26 Write D27 to D35 Write nothing K L→H – L→H – L→H – L→H – L→H – L→H – /K – L→H – L→H – L→H – L→H – L→H – L→H /BW0 0 0 0 0 1 1 1 1 1 1 1 1 /BW1 0 0 1 1 0 0 1 1 1 1 1 1 /BW2 0 0 1 1 1 1 0 0 1 1 1 1 /BW3 0 0 1 1 1 1 1 1 0 0 1 1
Remarks 1. H : High level, L : Low level, → : rising edge. 2. Assumes a WRITE cycle was initiated. /BW0 to /BW3 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
Data Sheet M15824EJ7V1DS
9
µPD44165082, 44165182, 44165362
Bus Cycle State Diagram
LOAD NEW WRITE ADDRESS AT /K
LOAD NEW READ ADDRESS
Always
/W = L
/R = L
Always
WRITE DOUBLE AT /K /W = L
READ DOUBLE
/R = L
/W = H /W = H Supply voltage provided Supply voltage provided
/R = H /R = H
WRITE PORT NOP
Power UP
READ PORT NOP R_Init = 0
Remarks 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation. The address order is always fixed as: xxx...xxx+0, xxx...xxx+1. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. Read and write state machines can be active simultaneously. 3. State machine control timing sequence is controlled by K.
10
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Output supply voltage Input voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VDD VDDQ VIN VI/O TA Tstg Conditions MIN. –0.5 –0.5 –0.5 –0.5 0 –55 TYP. MAX. +2.9 VDD VDD + 0.5 (2.9 V MAX.) VDDQ + 0.5 (2.9 V MAX.) 70 +125 Unit V V V V °C °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter Supply voltage Output supply voltage High level input voltage Low level input voltage Clock input voltage Reference voltage Symbol VDD VDDQ VIH (DC) VIL (DC) VIN VREF Conditions MIN. 1.7 1.4 VREF + 0.1 –0.3 –0.3 0.68 TYP. MAX. 1.9 VDD VDDQ + 0.3 VREF – 0.1 VDDQ + 0.3 0.95 Unit V V V V V V 1 1, 2 1, 2 1, 2 Note
Notes 1. During normal operation, VDDQ must not exceed VDD. 2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms Recommended AC Operating Conditions (TA = 0 to 70 °C)
Parameter High level input voltage Low level input voltage Symbol VIH (AC) VIL (AC) Conditions MIN. VREF + 0.2 – TYP. MAX. – VREF – 0.2 Unit V V Note 1 1
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2 Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2 Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than TKHKH (MIN.).
Data Sheet M15824EJ7V1DS
11
µPD44165082, 44165182, 44165362
DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter Symbol Test condition MIN. TYP. MAX. x8, x18 Input leakage current I/O leakage current Operating supply current (Read Write cycle) ILI ILO IDD VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Cycle = MAX. Standby supply current (NOP) ISB1 VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Cycle = MAX. High level output voltage VOH(Low) |IOH| ≤ 0.1 mA VOH Low level output voltage Note1 –E50 –E60 –E75 –E50 –E60 –E75 VDDQ – 0.2 VDDQ/2 – 0.12 VSS VDDQ/2 – 0.12 – – – – –2 –2 – – 610 530 470 270 250 230 VDDQ VDDQ/2 + 0.12 0.2 VDDQ/2 + 0.12 V V 3,4 3,4 3,4 3,4 +2 +2 700 600 530 mA x36 Unit Note
µA µA
mA
VOL(Low) IOL ≤ 0.1 mA VOL Note2
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 3. AC load current is higher than the shown DC values. 4. HSTL outputs meet JEDEC HSTL Class I and Class II standards. Capacitance (TA = 25 °C, f = 1MHz)
Parameter Input capacitance(Address, Control) Input / Output capacitance(D, Q) Clock Input capacitance Symbol CIN CI/O Cclk Test conditions VIN = 0 V VI/O = 0 V Vclk = 0 V MIN. TYP. 4 6 5 MAX. 5 7 6 Unit pF pF pF
Remark These parameters are periodically sampled and not 100% tested.
12
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
AC Characteristics (TA = 0 to 70 °C, VDD = 1.8 ± 0.1 V) AC Test Conditions Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test Points
0.75 V
0.25 V
Output waveform
VDDQ / 2
Test Points
VDDQ / 2
Output load condition Figure 1. External load at test
VDDQ / 2 0.75 V
VREF
50 Ω ZO = 50 Ω 250 Ω
SRAM
ZQ
Data Sheet M15824EJ7V1DS
13
µPD44165082, 44165182, 44165362
Read and Write Cycle
Parameter Symbol -E50 (200 MHz) MIN. Clock Average Clock cycle time (K, /K, C, /C) Clock phase jitter (K, /K, C, /C) Clock HIGH time (K, /K, C, /C) Clock LOW time (K, /K, C, /C) Clock to /clock (K→/K., C→/C.) Clock to /clock (/K→K., /C→C.) Clock to data clock 167 to 200 MHz (K→C., /K→/C.) DLL lock time (K, C) K static to DLL reset Output Times C, /C HIGH to output valid C, /C HIGH to output hold C, /C HIGH to echo clock valid C, /C HIGH to echo clock hold CQ, /CQ HIGH to output valid CQ, /CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z Setup Times Address valid to K rising edge Control inputs (/R, /W) valid to K rising edge Data inputs and write data select inputs (/BWx, /NWx) valid to K, /K rising edge Hold Times K rising edge to address hold K rising edge to control inputs (/R, /W) hold K, /K rising edge to data inputs and write data select inputs (/BWx, /NWx) hold TKHAX TKHIX TKHDX 0.4 0.4 0.4 – – – 0.5 0.5 0.5 – – – 0.5 0.5 0.5 – – – ns ns ns 5 5 5 TDVKH 0.4 – 0.5 – 0.5 – ns 5 TAVKH TIVKH 0.4 0.4 – – 0.5 0.5 – – 0.5 0.5 – – ns ns 5 5 TCHQV TCHQX TCHCQV TCHCQX TCQHQV TCQHQX TCHQZ TCHQX1 – –0.45 – –0.45 – –0.35 – –0.45 0.45 – 0.45 – 0.35 – 0.45 – – –0.5 – –0.5 – –0.4 – –0.5 0.5 – 0.5 – 0.4 – 0.5 – – –0.5 – –0.5 – –0.4 – –0.5 0.5 – 0.5 – 0.4 – 0.5 – ns ns ns ns ns ns ns ns 4 4 133 to 167 MHz < 133 MHz TKC lock TKC reset TKHKH TKC var TKHKL TKLKH TKH /KH T /KHKH TKHCH 5.0 – 2.0 2.0 2.2 2.2 0 0 0 1,024 30 8.4 0.2 – – – – 2.3 2.8 3.55 – – 6.0 – 2.4 2.4 2.7 2.7 – 0 0 1,024 30 8.4 0.2 – – – – – 2.8 3.55 – – 7.5 – 3.0 3.0 3.38 3.38 – – 0 1,024 30 8.4 0.2 – – – – – – 3.55 – – Cycle ns 3 ns ns ns ns ns ns ns 1 2 MAX. -E60 (167 MHz) MIN. MAX. -E75 (133 MHz) MIN. MAX. Unit Note
14
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.). 2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations. 5. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. Remarks 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.). 4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters. 5. VDDQ is 1.5 V DC.
Data Sheet M15824EJ7V1DS
15
µPD44165082, 44165182, 44165362
Read and Write Timing
READ WRITE READ WRITE READ WRITE NOP
WRITE NOP
1
2
3
4
5
6
7
8
9
10
K
TKHKL TKLKH
TKHKH
TKH/KH T/KHKH
/K
/R
TIVKH TKHIX
/W
Address
A0
TAVKH
A1
TKHAX
A2
TAVKH
A3
TKHAX
A4
A5
A6
Data in
D10
D11
D30
D31
D50
D51
D60
D61
TDVKH TKHDX
TDVKH TKHDX
Data out
Q00
TCHQX
Q01
TCHQX
Q20
Q21
Q40
Q41
TCHQX1
TCHQV
TCQHQV
TCHQV
TCHQZ
CQ
TCHCQX TCHCQV
/CQ
TKHCH
TCHCQX TCHCQV
C
TKHKL
TKLKH
TKH/KH
T/KHKH
TKHKH
TKHCH
/C
Remarks 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following A0,i.e.,A0+1. 2. Outputs are disable (high impedance) one clock cycle after a NOP. 3. In this example, if address A0=A1, data Q00=D10, Q01=D11. Write data is forwarded immediately as read results.
16
Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins
Pin name TCK TMS TDI Pin assignments 2R 10R 11R Test Clock Input. Description All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test Mode Select. This is the command input for the TAP controller state machine. Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP. JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter JTAG Input leakage current JTAG I/O leakage current Symbol ILI ILO Conditions 0 V ≤ VIN ≤ VDD 0 V ≤ VIN ≤ VDDQ , Outputs disabled JTAG input high voltage JTAG input low voltage JTAG output high voltage VIH VIL VOH1 VOH2 JTAG output low voltage VOL1 VOL2 | IOHC | = 100 µA | IOHT | = 2 mA IOLC = 100 µA IOLT = 2 mA 1.3 –0.3 1.6 1.4 – – – – – – – – VDD + 0.3 +0.5 – – 0.2 0.4 V V V V V V MIN. –5.0 –5.0 TYP. – – MAX. +5.0 +5.0 Unit Note
µA µA
Data Sheet M15824EJ7V1DS
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µPD44165082, 44165182, 44165362
JTAG AC Test Conditions Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
Test Points
0.9 V
0V
Output waveform
0.9 V
Test Points
0.9 V
Output load Figure 2. External load at test
VTT = 0.9 V
50 Ω
ZO = 50 Ω TDO
20 pF
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Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
JTAG AC Characteristics (TA = 0 to 70 °C)
Parameter Clock Clock cycle time Clock frequency Clock high time Clock low time tTHTH fTF tTHTL tTLTH 100 – 40 40 – – – – – 10 – – ns MHz ns ns Symbol Conditions MIN. TYP. MAX. Unit Note
Output time TCK low to TDO unknown TCK low to TDO valid TDI valid to TCK high TCK high to TDI invalid tTLOX tTLOV tDVTH tTHDX 0 – 10 10 – – – – – 20 – – ns ns ns ns
Setup time TMS setup time Capture setup time tMVTH tCS 10 10 – – – – ns ns
Hold time TMS hold time Capture hold time tTHMX tCH 10 10 – – – – ns ns
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
tTHMX
tDVTH
TDI
tTHDX
tTLOX
tTLOV
TDO
Data Sheet M15824EJ7V1DS
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µPD44165082, 44165182, 44165362
Scan Register Definition (1)
Register name Instruction register Description The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit’s position in the boundary register. The second column is the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name Instruction register Bypass register ID register Boundary register Bit size 3 1 32 107 Unit bit bit bit bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no. 2M x 8 1M x 18 512K x 36 XXXX XXXX XXXX ID [27:12] part no. 0000 0000 0000 1100 0000 0000 0000 1101 0000 0000 0000 1110 ID [11:1] vendor ID no. 00000010000 00000010000 00000010000 ID [0] fix bit 1 1 1
µPD44165082 µPD44165182 µPD44165362
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Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
SCAN Exit Order
Bit no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Signal name x8 x18 /C C A A A A A A A NC NC NC NC NC NC NC NC Q0 D0 NC NC NC NC NC NC Q1 D1 Q0 D0 NC NC Q1 D1 NC NC Q2 D2 NC NC Q3 D3 NC NC Q4 D4 ZQ NC NC NC NC NC NC Q2 D2 NC NC Q5 D5 NC NC Q6 D6 D13 Q13 Q5 D5 D14 Q14 Q6 D6 Q0 D0 D9 Q9 Q1 D1 D10 Q10 Q2 D2 D11 Q11 Q3 D3 D12 Q12 Q4 D4 x36
Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E
Bit no. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A A
Signal name x8 NC NC NC NC NC NC Q3 D3 NC NC x18 NC NC Q7 D7 NC NC Q8 D8 NC NC CQ – A A A A /R NC NC /BW1 NC x36 D15 Q15 Q7 D7 D16 Q16 Q8 D8 D17 Q17
Bump ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A
Internal
Bit no. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 x8 NC Q4 D4 NC NC NC NC NC NC Q5 D5 NC NC NC NC NC NC Q6 D6 NC NC NC NC NC NC Q7 D7 NC NC
Signal name x18 NC Q11 D11 NC NC Q12 D12 NC NC Q13 D13 NC NC Q14 D14 NC NC Q15 D15 NC NC Q16 D16 NC NC Q17 D17 NC NC A A A A A A x36 Q28 Q20 D20 D29 Q29 Q21 D21 D30 Q30 Q22 D22 D31 Q31 Q23 D23 D32 Q32 Q24 D24 D33 Q33 Q25 D25 D34 Q34 Q26 D26 D35 Q35
Bump ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
9A 8B 7C 6C 8A 7A 7B 6B 6A
/NW0 /BW0 /BW0 K /K NC NC /BW3
5B 5A 4A 5C 4B
/NW1 /BW1 /BW2 /W A A NC /DLL /CQ NC NC NC NC NC NC NC Q9 D9 NC NC Q10 D10 NC Q18 D18 D27 Q27 Q19 D19 D28 NC
3A 1H 1A 2B 3B 1C 1B 3D 3C 1D
Data Sheet M15824EJ7V1DS
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µPD44165082, 44165182, 44165362
JTAG Instructions
Instructions EXTEST Description The EXTEST instruction allows circuitry external to the component package to be tested. Boundaryscan register cells at output pins are used to apply test vectors, while those at input pins capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output pins. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an inactive drive state (high impedance) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED SAMPLE / PRELOAD RESERVED RESERVED BYPASS 1 Note
Note 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
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Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
TAP Controller State Diagram
1
Test-Logic-Reset
0 1 1 1
0
Run-Test / Idle
Select-DR-Scan
0 1 1
Select-IR-Scan
0
Capture-DR
0
Capture-IR
0
Shift-DR
1 1
0
Shift-IR
1 1
0
Exit1-DR
0
Exit1-IR
0
Pause-DR
1 0
0
Pause-IR
1 0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
1 0
Update-IR
1 0
Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor. TDO should be left unconnected.
Data Sheet M15824EJ7V1DS
23
µ µ µPD44165082, 44165182, 44165362 µ
Run-Test/Idle
Update-IR Exit1-IR
Shift-IR
Exit2-IR
Exit1-IR
Shift-IR
Capture-IR Select-IR-Scan Select-DR-Scan Run-Test/Idle
Test Logic Operation (Instruction Scan)
IDCODE
Pause-IR
New Instruction
Test-Logic-Reset
Controller state
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Data Sheet M15824EJ7V1DS
Instruction Register state
TDO TMS TCK TDI
Output Inactive
µ µ µPD44165082, 44165182, 44165362
Test-Logic-Reset
Select-IR-Scan Select-DR-Scan
Run-Test/Idle
Update-DR Exit1-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR Select-DR-Scan
Instruction
IDCODE
Run-Test/Idle
Test Logic (Data Scan)
TMS
Output Inactive
Controller state
Instruction Register state
TDO
TCK
TDI
Data Sheet M15824EJ7V1DS
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µPD44165082, 44165182, 44165362
Package Drawing
165-PIN PLASTIC BGA (13x15)
E wSB ZD B
ZE
A D
11 10 9 8 7 6 5 4 3 2 1 R PMM L K J H G F E D C BA
INDEX MARK
wSA A
y1
S
A2 S
y
S
e
A1
(UNIT:mm) ITEM D E w e A A1 A2 b x y y1 ZD ZE DIMENSIONS 13.00 ± 0.10 15.00 ± 0.10 0.15 1.00 1.40 ± 0.11 0.40 ± 0.05 1.00 0.50 ± 0.05 0.08 0.10 0.20 1.50 0.50 P165F5-100-EQ1
φb
φx
M
S AB
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Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices
µPD44165082F5-EQ1: 165-pin PLASTIC BGA (13 x 15) µPD44165182F5-EQ1: 165-pin PLASTIC BGA (13 x 15) µPD44165362F5-EQ1: 165-pin PLASTIC BGA (13 x 15)
Data Sheet M15824EJ7V1DS
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µPD44165082, 44165182, 44165362
Revision History
Edition/ Date This edition 7th edition/ Feb. 2004
MAX. x8, x18 -E50 -E60 -E75 560 480 420 x36 670 570 500 mA -E50 -E60 -E75 Unit MAX. x8, x18 610 530 470 x36 700 600 530 mA Unit
Page Previous edition p.12
Type of revision
Location
Description (Previous edition → This edition)
p.12
Modification DC Characteristics IDD (MAX.)
DC Characteristics ISB1 (MAX.)
MAX. x8, x18 -E50 -E60 -E75 210 190 170 x36
Unit
MAX. x8, x18 x36
Unit
mA
-E50 -E60 -E75
270 250 230
mA
p.26
p.26
Modification Package Drawing
Preliminary version → Standardized version
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Data Sheet M15824EJ7V1DS
µPD44165082, 44165182, 44165362
[MEMO]
Data Sheet M15824EJ7V1DS
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µPD44165082, 44165182, 44165362
[MEMO]
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Data Sheet M15824EJ7V1DS
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NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.
Data Sheet M15824EJ7V1DS
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µPD44165082, 44165182, 44165362
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, Renesas, IDT, Micron Technology, Inc., NEC Electronics, and Samsung.
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