UPD442002F9-BC70X-BC2-A

DATA SHEET MOS INTEGRATED CIRCUIT µPD442002-X 2M-BIT CMOS STATIC RAM 128K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD442002-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM. The µPD442002-X is packed in 48-pin TAPE FBGA. Features • 131,072 words by 16 bits organization • Fast access time : 70, 85, 100 ns (MAX.) • Byte data control : /LB (I/O1 to I/O8), /UB (I/O9 to I/O16) • Low voltage operation : VCC = 2.7 to 3.6 V (-BB70X) VCC = 2.2 to 3.6 V (-BC70X) VCC = 1.8 to 2.2 V (-DD85X, -DD10X) • Low VCC data retention : 1.0 V (MIN.) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application µPD442002 Access time ns (MAX.) Operating supply voltage V -BB70X -BC70X -DD85X, -DD10X 70 70 85, 100 2.7 to 3.6 2.2 to 3.6 1.8 to 2.2 15 3 Operating ambient temperature °C −25 to +85 At operating mA (MAX.) 30 Supply current At standby At data retention µA (MAX.) 4 µA (MAX.) 2 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M14670EJ7V1DS00 (7th edition) Date Published July 2004 NS CP(K) Printed in Japan The mark shows major revised points. 2000 µPD442002-X Ordering Information Part number Package Access time ns (MAX.) Operating supply voltage V Operating temperature °C −25 to +85 µPD442002F9-BB70X-BC2-A Note µPD442002F9-BC70X-BC2-A Note 48-pin TAPE FBGA (8×6) 70 70 85 100 2.7 to 3.6 2.2 to 3.6 1.8 to 2.2 µPD442002F9-DD85X-BC2-A Note µPD442002F9-DD10X-BC2-A Note Note Lead-free product Marking Image Part number Marking (XX) B2 C2 D3 D4 µPD442002F9-BB70X-BC2-A µPD442002F9-BC70X-BC2-A µPD442002F9-DD85X-BC2-A µPD442002F9-DD10X-BC2-A J S2M0-XX INDEX MARK Lot No. 2 Data Sheet M14670EJ7V1DS µPD442002-X Pin Configuration /xxx indicates active low signal. 48-pin TAPE FBGA (8×6) Top View Bottom View A B C D E F G H 1 2 3 4 5 6 6 5 4 3 2 1 1 A B C D E F G H /LB I/O9 I/O10 GND VCC I/O15 I/O16 NC 2 /OE /UB I/O11 I/O12 I/O13 I/O14 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 /CS I/O2 I/O4 I/O5 I/O6 /WE A11 6 NC I/O1 I/O3 VCC GND I/O7 I/O8 NC A B C D E F G H 6 NC I/O1 I/O3 VCC GND I/O7 I/O8 NC 5 A2 /CS I/O2 I/O4 I/O5 I/O6 /WE A11 4 A1 A4 A6 A7 A16 A15 A13 A10 3 A0 A3 A5 NC NC A14 A12 A9 2 /OE /UB I/O11 I/O12 I/O13 I/O14 NC A8 1 /LB I/O9 I/O10 GND VCC I/O15 I/O16 NC A0 to A16 /CS /WE /OE /LB, /UB VCC GND NC : Address inputs : Chip Select : Write Enable : Output Enable : Byte data select : Power supply : Ground : No Connection I/O1 to I/O16 : Data inputs / outputs Remark Refer to Package Drawing for the index mark. Data Sheet M14670EJ7V1DS 3 µPD442002-X Block Diagram VCC GND A0 A16 Address buffer Row decoder Memory cell array 2,097,152 bits I/O1 to I/O8 I/O9 to I/O16 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CS /LB /UB /WE /OE 4 Data Sheet M14670EJ7V1DS µPD442002-X Truth Table /CS /OE /WE /LB /UB Mode I/O1 to I/O8 H × L × × H × × H × H L × L H L L H × L L L H × H × L L H L L H L Not selected Not selected Output disable Output disable Word read Lower byte read Upper byte read Word write Lower byte write Upper byte write High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN High-Z I/O I/O9 to I/O16 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN ICCA ISB Supply current Remark × : VIH or VIL Data Sheet M14670EJ7V1DS 5 µPD442002-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition -BB70X, -BC70X Supply voltage Input / Output voltage Operating ambient temperature Storage temperature VCC VT TA Tstg –0.5 Note Rating -DD85X, -DD10X –0.5 Note Note Unit –0.5 Note to +4.0 to +2.7 V V °C °C to VCC+0.4 (4.0 V MAX.) –0.5 –25 to +85 –55 to +125 to VCC+0.4 (2.7 V MAX.) –25 to +85 –55 to +125 Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition -BB70X MIN. Supply voltage High level input voltage VCC VIH 2.7 V ≤ VCC ≤ 3.6 V 2.2 V ≤ VCC < 2.7 V 1.8 V ≤ VCC < 2.2 V Low level input voltage Operating ambient temperature VIL TA 2.7 2.4 – – –0.3 Note -BC70X MIN. 2.2 2.4 2.0 – –0.3 Note -DD85X, -DD10X MIN. 1.8 – – 1.6 –0.2 Note Unit MAX. 3.6 VCC+0.4 – – +0.5 +85 MAX. 3.6 VCC+0.4 VCC+0.3 – +0.4 +85 MAX. 2.2 – – VCC+0.2 +0.2 +85 V °C V V –25 –25 –25 Note –1.0 V (MIN.) (Pulse width : 20 ns) Capacitance (TA = 25°C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test condition MIN. TYP. MAX. 8 10 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 6 Data Sheet M14670EJ7V1DS µPD442002-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CS = VIH or /WE = VIL or /OE = VIH Operating supply current ICCA1 ICCA2 ICCA3 /CS = VIL, II/O = 0 mA, Minimum cycle time /CS = VIL, II/O = 0 mA, Cycle time = ∞ /CS ≤ 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB ISB1 ISB2 High level output voltage Low level output voltage VOH VOL /CS = VIH or /LB = /UB = VIH /CS ≥ VCC – 0.2 V /LB = /UB ≥ VCC – 0.2 V, /CS ≤ 0.2 V IOH = –0.5 mA IOL = 1.0 mA 2.4 0.4 – 0.3 0.3 0.6 4 4 V V mA – – – 30 4 4 mA –1.0 –1.0 -BB70X TYP. MAX. +1.0 +1.0 Unit µA µA µA Remark VIN : Input voltage VI/O : Input / Output voltage Data Sheet M14670EJ7V1DS 7 µPD442002-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CS = VIH or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CS = VIL, II/O = 0 mA, Minimum cycle time VCC ≤ 2.7 V VCC ≤ 2.2 V ICCA2 /CS = VIL, II/O = 0 mA, Cycle time = ∞ VCC ≤ 2.7 V VCC ≤ 2.2 V ICCA3 /CS ≤ 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VCC ≤ 2.7 V VIH ≥ VCC – 0.2 V Standby supply current ISB VCC ≤ 2.2 V – – – – – – – – – – – – 0.3 VCC ≤ 2.7 V VCC ≤ 2.2 V ISB2 /LB = /UB ≥ VCC – 0.2 V, /CS ≤ 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V High level output voltage VOH IOH = –0.5 mA VCC ≤ 2.7 V VCC ≤ 2.2 V Low level output voltage VOL IOL = 1.0 mA VCC ≤ 2.7 V VCC ≤ 2.2 V 2.4 1.8 – 0.4 0.4 – 0.25 – 0.3 0.25 – 30 25 – 4 2 – 4 3 – 0.6 0.6 – 4 3.5 – 4 3.5 – – – 1.5 – – 0.4 V – – – – – – – – – – – – – – 0.2 – – 0.2 – – 15 – – 1 – – 3 – – 0.6 – – 3 – – 3 V mA mA –1.0 –1.0 -BC70X TYP. MAX. +1.0 +1.0 -DD85X, -DD10X MIN. –1.0 –1.0 TYP. MAX. +1.0 +1.0 Unit µA µA /CS = VIH or /LB = /UB = VIH VCC ≤ 2.7 V VCC ≤ 2.2 V ISB1 /CS ≥ VCC – 0.2 V µA Remark VIN : Input voltage VI/O : Input / Output voltage 8 Data Sheet M14670EJ7V1DS µPD442002-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 0.1 VCC Output Waveform VCC/2 Test points VCC/2 Output Load [ -BB70X ] 1TTL + 50 pF [ -BC70X, -DD85X, -DD10X ] 1TTL + 30 pF Data Sheet M14670EJ7V1DS 9 µPD442002-X Read Cycle (1/2) Parameter Symbol VCC ≥ 2.7 V -BB70X MIN. Read cycle time Address access time /CS access time /OE to output valid /LB, /UB to output valid Output hold from address change /CS to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CS to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tACS tOE tBA tOH tLZ tOLZ tBLZ tHZ tOHZ tBHZ 10 10 5 10 25 25 25 70 70 70 35 70 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Unit Condition Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/2) Parameter Symbol VCC ≥ 2.2 V -BC70X MIN. Read cycle time Address access time /CS access time /OE to output valid /LB, /UB to output valid Output hold from address change /CS to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CS to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tACS tOE tBA tOH tLZ tOLZ tBLZ tHZ tOHZ tBHZ 10 10 5 10 25 25 25 70 70 70 35 70 10 10 5 10 30 30 30 MAX. -DD85X MIN. 85 85 85 40 85 10 10 5 10 35 35 35 MAX. VCC ≥ 1.8 V -DD10X MIN. 100 100 100 50 100 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Unit Condition Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. 10 Data Sheet M14670EJ7V1DS µPD442002-X Read Cycle Timing Chart tRC Address (Input) tAA tOH /CS (Input) tACS tHZ tLZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ I/O (Output) High-Z Data out Remark In read cycle, /WE should be fixed to high level. Data Sheet M14670EJ7V1DS 11 µPD442002-X Write Cycle (1/2) Parameter Symbol VCC ≥ 2.7 V -BB70X MIN. Write cycle time /CS to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW tBW tAW tAS tWP tWR tDW tDH tWHZ tOW 5 70 55 55 55 0 50 0 30 0 25 MAX. ns ns ns ns ns ns ns ns ns ns ns Note Unit Condition Note The output load is 1TTL + 5 pF. Write Cycle (2/2) Parameter Symbol VCC ≥ 2.2 V -BC70X MIN. Write cycle time /CS to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW tBW tAW tAS tWP tWR tDW tDH tWHZ tOW 5 70 55 55 55 0 50 0 30 0 25 5 MAX. -DD85X MIN. 85 70 70 70 0 55 0 35 0 30 5 MAX. VCC ≥ 1.8 V -DD10X MIN. 100 80 80 80 0 60 0 40 0 35 MAX. ns ns ns ns ns ns ns ns ns ns ns Note Unit Condition Note The output load is 1TTL + 5 pF. 12 Data Sheet M14670EJ7V1DS µPD442002-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS /WE (Input) tWP tWR tBW /LB, /UB (Input) tOW tWHZ High-Z tDW tDH High-Z I/O (Input / Output) Indefinite data out Data in Indefinite data out Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). 2. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M14670EJ7V1DS 13 µPD442002-X Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS /CS (Input) tAW tWP /WE (Input) tCW tWR tBW /LB, /UB (Input) tDW High-Z I/O (Input) Data in tDH High-Z Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). 14 Data Sheet M14670EJ7V1DS µPD442002-X Write Cycle Timing Chart 3 (/LB, /UB Controlled) tWC Address (Input) tCW /CS (Input) tAW tWP /WE (Input) tWR tAS tBW /LB, /UB (Input) tDW High-Z I/O (Input) Data in tDH High-Z Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). Data Sheet M14670EJ7V1DS 15 µPD442002-X Low VCC Data Retention Characteristics (TA = –25 to +85°C) Parameter Symbol Test Condition -BB70X -BC70X -DD85X, -DD10X Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention supply voltage VCCDR1 VCCDR2 /CS ≥ VCC − 0.2 V /LB = /UB ≥ VCC − 0.2 V, /CS ≤ 0.2 V Data retention supply current ICCDR1 ICCDR2 VCC = 1.2 V, /CS ≥ VCC − 0.2 V VCC = 1.2 V, /LB = /UB ≥ VCC − 0.2 V, /CS ≤ 0.2 V Chip deselection to data retention mode Operation recovery time tR tRC Note 1.0 1.0 3.6 3.6 1.0 1.0 3.6 3.6 1.0 1.0 2.2 2.2 V 0.15 0.15 2 2 0.15 0.15 2 2 0.15 0.15 2 2 µA tCDR 0 0 0 ns tRC Note tRC Note ns Note tRC : Read cycle time 16 Data Sheet M14670EJ7V1DS µPD442002-X Data Retention Timing Chart (1) /CS Controlled tCDR VCC Data retention mode tR VCC (MIN.) Note /CS VIH (MIN.) VCCDR (MIN.) /CS ≥ VCC – 0.2 V VIL (MAX.) GND Note 2.7 V (-BB70X), 2.2 V (-BC70X), 1.8 V (-DD85X, -DD10X) Remark On the data retention mode by controlling /CS, the other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) /LB, /UB Controlled tCDR VCC VCC (MIN.) Note Data retention mode tR /LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB ≥ VCC – 0.2 V VIL (MAX.) GND Note 2.7 V (-BB70X), 2.2 V (-BC70X), 1.8 V (-DD85X, -DD10X) Remark On the data retention mode by controlling /LB and /UB, the input level of /CS must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M14670EJ7V1DS 17 µPD442002-X Package Drawing 48-PIN TAPE FBGA (8x6) ZE E w SB ZD B A D 6 5 4 3 2 1 HGFEDCBA INDEX MARK w SA INDEX MARK A y1 S A2 S y S e A1 M φb φx S AB ITEM D E w e A A1 A2 b x y y1 ZD ZE MILLIMETERS 6.0 ± 0.1 8.0 ± 0.1 0.2 0.75 0.94 ± 0.10 0.24 ± 0.05 0.70 0.40 ± 0.05 0.08 0.1 0.2 1.125 1.375 P48F9-75-BC2 18 Data Sheet M14670EJ7V1DS µPD442002-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD442002-X. Types of Surface Mount Device µPD442002F9-BC2-A Note : 48-pin TAPE FBGA (8x6) Note Lead-free product Data Sheet M14670EJ7V1DS 19 µPD442002-X Revision History Edition/ Date Previous edition 7th edition/ Dec. 2003 Throughout p.2, 21 Page This edition Throughout p.2, 19 Deletion Modification Addition p.2 p.2 Modification Marking image Class Package code -BB55X, -BB85X, -BC85X, -BC10X, -DD12X F9-BC1 → F9-BC2-A "Note Lead-free product" has been added. Lead-free mark has been added. Index mark has been modified. p.20 p.18 Modification Package Drawing Package drawing has been changed Type of revision Location Description (Previous edition → This edition) 20 Data Sheet M14670EJ7V1DS µPD442002-X [ MEMO ] Data Sheet M14670EJ7V1DS 21 µPD442002-X [ MEMO ] 22 Data Sheet M14670EJ7V1DS µPD442002-X NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. Data Sheet M14670EJ7V1DS 23 µPD442002-X • T he information in this document is current as of July, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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