UPD442012AGY-BC70X-MJH

DATA SHEET µPD442012A-X 2M-BIT CMOS STATIC RAM 128K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION MOS INTEGRATED CIRCUIT Description The µPD442012A-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM. The µPD442012A-X has two chip enable pins (/CE1, CE2) to extend the capacity. The µPD442012A-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent). Features • 131,072 words by 16 bits organization 5 • Fast access time : 50, 55, 70, 85, 100, 120 ns (MAX.) • Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16) • Low voltage operation (BB version : VCC = 2.7 to 3.6 V, BC version : VCC = 2.2 to 3.6 V, DD version : VCC = 1.8 to 2.2 V) • Low VCC data retention : 1.0 V (MIN.) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application • Two Chip Enable inputs : /CE1, CE2 Part number Access time ns (MAX.) Operating supply Operating ambient voltage V temperature °C −25 to +85 At operating mA (MAX.) 30 35 40 Note 2 Note 3 Note 4 Supply current At standby At data retention µA (MAX.) 4 µA (MAX.) 2 5 µPD442012A-BBxxX 50 Note 1 , 55, 70, 85 2.7 to 3.6 µPD442012A-BCxxX 70, 85, 100 85, 100, 120 2.2 to 3.6 1.8 to 2.2 30 15 3 5 5 5 5 5 µPD442012A-DDxxX Notes 1. VCC ≥ 3.0 V 2. Cycle time ≥ 70 ns 3. Cycle time = 55 ns 4. Cycle time = 50 ns The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14671EJ7V0DS00 (7th edition) Date Published July 2001 NS CP (K) Printed in Japan The mark 5 shows major revised points. © 2000 µPD442012A-X Ordering Information Part number Package Access time ns (MAX.) Operating supply voltage V Operating temperature °C −25 to +85 BB version Remark 5 µPD442012AGY-BB55X-MJH µPD442012AGY-BB70X-MJH µPD442012AGY-BB85X-MJH µPD442012AGY-BC70X-MJH µPD442012AGY-BC85X-MJH µPD442012AGY-BC10X-MJH µPD442012AGY-DD85X-MJH µPD442012AGY-DD10X-MJH µPD442012AGY-DD12X-MJH 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) 55, 50 70 85 70 85 Note 2.7 to 3.6 2.2 to 3.6 BC version 100 85 100 120 1.8 to 2.2 DD version 5 Note VCC ≥ 3.0 V 2 Data Sheet M14671EJ7V0DS µPD442012A-X Pin Configuration (Marking Side) /xxx indicates active low signal. 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) [ µPD442012AGY-BBxxX-MJH ] [ µPD442012AGY-BCxxX-MJH ] [ µPD442012AGY-DDxxX-MJH ] A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 IC /UB /LB NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 /OE GND /CE1 A0 A0 - A16 /CE1, CE2 /WE /OE /LB, /UB VCC GND NC IC Note : Address inputs : Chip Enable 1, 2 : Write Enable : Output Enable : Byte data select : Power supply : Ground : No Connection : Internal Connection I/O1 - I/O16 : Data inputs / outputs Note Leave this pin unconnected or connect to GND. Remark Refer to Package Drawing for the 1-pin index mark. Data Sheet M14671EJ7V0DS 3 µPD442012A-X Block Diagram VCC GND A0 A16 Address buffer Row decoder Memory cell array 2,097,152 bits I/O1 - I/O8 I/O9 - I/O16 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /LB /UB /WE /OE 4 Data Sheet M14671EJ7V0DS µPD442012A-X Truth Table /CE1 CE2 /OE /WE /LB /UB Mode I/O1 - I/O8 H × × L × L × H × × × H × × × H × × H L × L H L L H × L L L H × × H × L L H L L H L Not selected Not selected Not selected Output disable Output disable Word read Lower byte read Upper byte read Word write Lower byte write Upper byte write High impedance High impedance High impedance High impedance High impedance DOUT DOUT High impedance DIN DIN High impedance I/O I/O9 - I/O16 High impedance High impedance High impedance High impedance High impedance DOUT High impedance DOUT DIN High impedance DIN ICCA ISB Supply current Remark × : VIH or VIL Data Sheet M14671EJ7V0DS 5 µPD442012A-X Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol VCC Product Rating –0.5 –0.5 –0.5 –0.5 Note Note Note Note Unit V µPD442012A-BBxxX, µPD442012A-BCxxX µPD442012A-DDxxX to +4.0 to +2.7 Input / Output voltage VT µPD442012A-BBxxX, µPD442012A-BCxxX µPD442012A-DDxxX to VCC+0.4 (4.0 V MAX.) to VCC+0.4 (2.7 V MAX.) –25 to +85 –55 to +125 V Operating ambient temperature Storage temperature TA Tstg °C °C Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition µPD442012A-BBxxX µPD442012A-BCxxX µPD442012A-DDxxX MIN. MAX. 3.6 VCC+0.4 – – Note Unit MIN. 2.2 2.4 2.0 – –0.3 Note MAX. 3.6 VCC+0.4 VCC+0.3 – +0.4 +85 MIN. 1.8 – – 1.6 –0.2 Note MAX. 2.2 – – VCC+0.2 +0.2 +85 V °C V V Supply voltage High level input voltage VCC VIH 2.7 V ≤ VCC ≤ 3.6 V 2.2 V ≤ VCC < 2.7 V 1.8 V ≤ VCC < 2.2 V 2.7 2.4 – – –0.3 Low level input voltage Operating ambient temperature VIL TA +0.5 +85 –25 –25 –25 Note –1.0 V (MIN.) (Pulse width : 20 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test condition MIN. TYP. MAX. 8 10 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 6 Data Sheet M14671EJ7V0DS µPD442012A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition µPD442012A-BBxxX MIN. TYP. MAX. +1.0 +1.0 Unit Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH –1.0 –1.0 µA µA 5 Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Minimum cycle time Cycle time = 50 ns Cycle time = 55 ns Cycle time ≥ 70 ns – – – – 40 35 30 4 mA 5 ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ 5 ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V – 4 Standby supply current ISB ISB1 ISB2 ISB3 /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V CE2 ≤ 0.2 V /LB = /UB ≥ VCC – 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V – 0.3 0.3 0.3 0.6 4 4 4 mA µA High level output voltage Low level output voltage VOH VOL IOH = –0.5 mA IOL = 1.0 mA 2.4 0.4 V V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product specification. Data Sheet M14671EJ7V0DS 7 µPD442012A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition µPD442012A-BCxxX MIN. TYP. MAX. +1.0 +1.0 µPD442012A-DDxxX MIN. –1.0 –1.0 TYP. MAX. +1.0 +1.0 Unit Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH –1.0 –1.0 µA µA Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Minimum cycle time VCC ≤ 2.7 V VCC ≤ 2.2 V – – – – VCC ≤ 2.7 V VCC ≤ 2.2 V – – – 30 25 – 4 2 – 4 – – – – – – – – – 15 – – 1 – mA 5 5 5 5 5 5 ICCA3 ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, 5 5 Standby supply current ISB VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V – – – – – 0.3 3 – 0.6 0.6 – 4 3.5 – 4 3.5 – 4 3.5 – – – 1.5 0.4 – – – – – – – 0.2 – – 0.2 – – 0.2 – 3 – – 0.6 – – 3 – – 3 – – 3 V mA /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH VCC ≤ 2.7 V VCC ≤ 2.2 V ISB1 /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V µA 0.25 – 0.3 ISB2 CE2 ≤ 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V 0.25 – 0.3 ISB3 /LB = /UB ≥ VCC – 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V VCC ≤ 2.7 V VCC ≤ 2.2 V 2.4 VCC ≤ 2.7 V VCC ≤ 2.2 V 1.8 – 0.25 – High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1.0 mA VCC ≤ 2.7 V VCC ≤ 2.2 V – – 0.4 V 0.4 – Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product specification. 8 Data Sheet M14671EJ7V0DS µPD442012A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD442012A-BB55X, µPD442012A-BB70X, µPD442012A-BB85X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 0.1 VCC Test points VCC/2 Output Waveform VCC/2 Test points VCC/2 Output Load 1TTL + 50 pF [ µPD442012A-BC70X, µPD442012A-BC85X, µPD442012A-BC10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 0.1 VCC Test points VCC/2 Output Waveform VCC/2 Test points VCC/2 Output Load 1TTL + 30 pF [ µPD442012A-DD85X, µPD442012A-DD10X, µPD442012A-DD12X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 0.1 VCC Test points VCC/2 Output Waveform VCC/2 Test points VCC/2 Output Load 1TTL + 30 pF Data Sheet M14671EJ7V0DS 9 µPD442012A-X 5 Read Cycle (1/3) (BB version) Parameter Symbol µPD442012A-BB55X VCC ≥ 3.0 V MIN. MAX. MIN. 55 50 50 50 30 50 10 10 10 5 10 20 20 20 20 10 10 10 5 10 20 20 20 20 55 55 55 30 55 MAX. µPD442012A -BB70X MIN. 70 70 70 70 35 70 10 10 10 5 10 25 25 25 25 MAX. µPD442012A -BB85X MIN. 85 85 85 85 40 85 10 10 10 5 10 30 30 30 30 MAX. Unit Condition Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid /LB, /UB to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tCO1 tCO2 tOE tBA tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 tHZ2 tOHZ tBHZ 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/3) (BC version) Parameter Symbol µPD442012A -BC70X MIN. MAX. µPD442012A -BC85X MIN. 85 MAX. µPD442012A -BC10X MIN. 100 MAX. Unit Condition Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid /LB, /UB to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tCO1 tCO2 tOE tBA tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 tHZ2 tOHZ tBHZ 70 70 70 70 35 70 10 10 10 5 10 25 25 25 25 ns 100 100 100 50 100 ns ns ns ns ns ns ns ns ns ns 35 35 35 35 ns ns ns ns Note 2 Note 1 85 85 85 40 85 10 10 10 5 10 30 30 30 30 10 10 10 5 10 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. 10 Data Sheet M14671EJ7V0DS µPD442012A-X Read Cycle (3/3) (DD version) Parameter Symbol µPD442012A -DD85X MIN. MAX. µPD442012A -DD10X MIN. 100 MAX. µPD442012A -DD12X MIN. 120 MAX. Unit Condition Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid /LB, /UB to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tCO1 tCO2 tOE tBA tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 tHZ2 tOHZ tBHZ 85 85 85 85 40 85 10 10 10 5 10 30 30 30 30 ns 120 120 120 60 120 ns ns ns ns ns ns ns ns ns ns 40 40 40 40 ns ns ns ns Note 2 Note 1 100 100 100 50 100 10 10 10 5 10 35 35 35 35 10 10 10 5 10 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Read Cycle Timing Chart tRC Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH CE2 (Input) tCO2 tLZ2 tHZ2 /OE (Input) tOE tOLZ /LB, /UB (Input) tBA tBLZ I/O (Output) High impedance Data out tBHZ tOHZ Remark In read cycle, /WE should be fixed to high level. Data Sheet M14671EJ7V0DS 11 µPD442012A-X 5 Write Cycle (1/3) (BB version) Parameter Symbol µPD442012A-BB55X VCC ≥ 3.0 V MIN. MAX. MIN. 55 50 50 50 50 0 45 0 25 0 20 5 5 20 MAX. µPD442012A -BB70X MIN. 70 55 55 55 55 0 50 0 30 0 25 5 MAX. µPD442012A -BB85X MIN. 85 70 70 70 70 0 55 0 35 0 30 5 MAX. Unit Condition Write cycle time /CE1 to end of write CE2 to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tBW tAW tAS tWP tWR tDW tDH tWHZ tOW 50 45 45 45 45 0 40 0 25 0 ns ns ns ns ns ns ns ns ns ns ns ns Note Note The output load is 1TTL + 5 pF. Write Cycle (2/3) (BC version) Parameter Symbol µPD442012A -BC70X MIN. MAX. µPD442012A -BC85X MIN. 85 70 70 70 70 0 55 0 35 0 MAX. µPD442012A -BC10X MIN. 100 80 80 80 80 0 60 0 40 0 MAX. Unit Condition Write cycle time /CE1 to end of write CE2 to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tBW tAW tAS tWP tWR tDW tDH tWHZ tOW 70 55 55 55 55 0 50 0 30 0 25 5 ns ns ns ns ns ns ns ns ns ns 35 ns ns Note 30 5 5 Note The output load is 1TTL + 5 pF. 12 Data Sheet M14671EJ7V0DS µPD442012A-X Write Cycle (3/3) (DD version) Parameter Symbol µPD442012A -DD85X MIN. MAX. µPD442012A -DD10X MIN. 100 80 80 80 80 0 60 0 40 0 MAX. µPD442012A -DD12X MIN. 120 100 100 100 100 0 85 0 60 0 MAX. Unit Condition Write cycle time /CE1 to end of write CE2 to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tBW tAW tAS tWP tWR tDW tDH tWHZ tOW 85 70 70 70 70 0 55 0 35 0 30 5 ns ns ns ns ns ns ns ns ns ns 40 ns ns Note 35 5 5 Note The output load is 1TTL + 5 pF. Data Sheet M14671EJ7V0DS 13 µPD442012A-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tWP tWR tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 14 Data Sheet M14671EJ7V0DS µPD442012A-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tCW1 tWR tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. Data Sheet M14671EJ7V0DS 15 µPD442012A-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS CE2 (Input) tAW tWP /WE (Input) tCW2 tWR tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. 16 Data Sheet M14671EJ7V0DS µPD442012A-X Write Cycle Timing Chart 4 (/LB, /UB Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tWR tAS /LB, /UB (Input) tBW tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. Data Sheet M14671EJ7V0DS 17 µPD442012A-X Low VCC Data Retention Characteristics (TA = –25 to +85 °C) Parameter Symbol Test Condition µPD442012A -BBxxX µPD442012A -BCxxX µPD442012A -DDxxX Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention supply voltage VCCDR2 VCCDR3 VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V CE2 ≤ 0.2 V /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V 1.0 1.0 3.6 3.6 1.0 1.0 3.6 3.6 1.0 1.0 2.2 2.2 1.0 3.6 1.0 3.6 1.0 2.2 V 5 Data retention supply current ICCDR1 VCC = 1.2 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 0.15 2 0.15 2 0.15 2 µA ICCDR2 ICCDR3 VCC = 1.2 V, CE2 ≤ 0.2 V VCC = 1.2 V, /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V 0.15 0.15 2 2 0.15 0.15 2 2 0.15 0.15 2 2 Chip deselection to data retention mode Operation recovery time tCDR 0 0 0 ns tR tRC Note tRC Note tRC Note ns Note tRC : Read cycle time 18 Data Sheet M14671EJ7V0DS µPD442012A-X Data Retention Timing Chart (1) /CE1 Controlled tCDR VCC VCC (MIN.) Note Data retention mode tR /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) CE2 Controlled tCDR VCC VCC (MIN.) Note Data retention mode tR VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. Data Sheet M14671EJ7V0DS 19 µPD442012A-X (3) /LB, /UB Controlled tCDR VCC VCC (MIN.) Note Data retention mode tR /LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB ≥ VCC – 0.2 V VIL (MAX.) GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. 20 Data Sheet M14671EJ7V0DS µPD442012A-X Package Drawing 48-PIN PLASTIC TSOP(I) (12x18) 1 48 F G R detail of lead end Q 24 25 E P I J A L S S D K N S C MM B NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) ITEM A B C D E F G I J K L M N P Q R S MILLIMETERS 12.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 1.0 ± 0.05 16.4 ± 0.1 0.8 ± 0.2 0.145 ± 0.05 0.5 0.10 0.10 18.0 ± 0.2 3° +5° −3° 0.25 0.60 ± 0.15 S48GY-50-MJH1-1 Data Sheet M14671EJ7V0DS 21 µPD442012A-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD442012A-X. Types of Surface Mount Device µPD442012AGY-BBxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) µPD442012AGY-BCxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) µPD442012AGY-DDxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) 22 Data Sheet M14671EJ7V0DS µPD442012A-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14671EJ7V0DS 23 µPD442012A-X • The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4