UPD444012AGY-C12X-MJH

DATA SHEET MOS INTEGRATED CIRCUIT µPD444012A-X 4M-BIT CMOS STATIC RAM 256K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD444012A-X is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM. The µPD444012A-X has two chip enable pins (/CE1, CE2) to extend the capacity. The µPD444012A-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent). Features • 262,144 words by 16 bits organization 5 5 • Fast access time: 50, 55, 70, 85, 100, 120 ns (MAX.) • Byte data control: /LB (I/O1 - I/O8), /UB (I/O9 - I/O16) • Low voltage operation (B version: VCC = 2.7 to 3.6 V, C version: VCC = 2.2 to 3.6 V) • Low VCC data retention: 1.0 V (MIN.) • Operating ambient temperature: TA = –25 to +85°C • Output Enable input for easy application • Two Chip Enable inputs: /CE1, CE2 Part number Access time ns (MAX.) Operating supply Voltage V Operating ambient temperature °C −25 to +85 At operating mA (MAX.) 40 45 50 Note 2 Note 3 Note 4 Supply current At standby At data retention µA (MAX.) 7 µA (MAX.) 3 5 µPD444012A-BxxX 50 Note 1 , 55, 70, 85, 100 2.7 to 3.6 µPD444012A-CxxX 70, 85, 100, 120 2.2 to 3.6 40 5 5 5 5 Notes 1. VCC ≥ 3.0 V 2. Cycle time ≥ 70 ns 3. Cycle time = 55 ns 4. Cycle time = 50 ns The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14464EJ5V0DS00 (5th edition) Date Published July 2001 NS CP (K) Printed in Japan The mark 5 shows major revised points. © 1999 µPD444012A-X 5 Ordering Information Part number Package Access time ns (MAX.) Operating supply voltage V Operating temperature °C −25 to +85 B version Remark µPD444012AGY-B55X-MJH µPD444012AGY-B70X-MJH µPD444012AGY-B85X-MJH µPD444012AGY-B10X-MJH µPD444012AGY-C70X-MJH µPD444012AGY-C85X-MJH µPD444012AGY-C10X-MJH µPD444012AGY-C12X-MJH 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) 55, 50 70 85 Note 2.7 to 3.6 100 70 85 100 120 2.2 to 3.6 C version Note VCC ≥ 3.0 V 2 Data Sheet M14464EJ5V0DS µPD444012A-X 5 Pin Configuration (Marking Side) /xxx indicates active low signal. 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) [ µPD444012AGY-BxxX-MJH ] [ µPD444012AGY-CxxX-MJH ] A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 NC /UB /LB NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 /OE GND /CE1 A0 A0 - A17 /CE1, CE2 /WE /OE /LB, /UB VCC GND NC : Address inputs : Chip Enable 1, 2 : Write Enable : Output Enable : Byte data select : Power supply : Ground : No Connection I/O1 - I/O16 : Data inputs / outputs Remark Refer to Package Drawing for the 1-pin index mark. Data Sheet M14464EJ5V0DS 3 µPD444012A-X Block Diagram VCC GND A0 A17 Address buffer Row decoder Memory cell array 4,194,304 bits I/O1 - I/O8 I/O9 - I/O16 Input data controller Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /LB /UB /WE /OE Truth Table /CE1 CE2 × L H /OE × × H L /WE × × H H /LB × × × L L H × L L L H × × × × H /UB × × × L H L L H L H Output disable Word read Lower byte read Upper byte read Word write Lower byte write Upper byte write Not selected High impedance DOUT DOUT High impedance DIN DIN High impedance High impedance High impedance DOUT High impedance DOUT DIN High impedance DIN High impedance ISB ICCA Mode I/O1 - I/O8 H × L Not selected High impedance I/O I/O9 - I/O16 High impedance ISB Supply current Remark × : VIH or VIL 4 Data Sheet M14464EJ5V0DS µPD444012A-X Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg –0.5 Note Condition –0.5 Rating Note Unit V V °C °C to +4.0 to VCC + 0.4 (4.0 V MAX.) –25 to +85 –55 to +125 Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 5 Recommended Operating Conditions Parameter Symbol Condition µPD444012A-BxxX MIN. MAX. 3.6 VCC+0.4 – Note µPD444012A-CxxX MIN. 2.2 2.4 2.0 –0.3 Note Unit MAX. 3.6 VCC+0.4 VCC+0.3 +0.3 +85 V °C V V Supply voltage High level input voltage VCC VIH 2.7 V ≤ VCC ≤ 3.6 V 2.2 V ≤ VCC < 2.7 V 2.7 2.4 – –0.3 Low level input voltage Operating ambient temperature VIL TA +0.5 +85 –25 –25 Note –1.5 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25°C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test condition MIN. TYP. MAX. 8 10 Unit pF pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. Data Sheet M14464EJ5V0DS 5 µPD444012A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(1/2) Parameter Symbol Test condition VCC ≥ 2.7 V Unit µPD444012A-BxxX MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH –1.0 –1.0 TYP. MAX. +1.0 +1.0 µA µA 5 5 Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Cycle time = 50 ns Minimum cycle time, II/O = 0 mA Cycle time = 55 ns Cycle time ≥ 70 ns – – – – 50 45 40 4 mA 5 ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ 5 ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V – 6 Standby supply current ISB ISB1 ISB2 ISB3 /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V CE2 ≤ 0.2 V /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V – 0.5 0.5 0.5 0.6 7 7 7 mA µA High level output voltage Low level output voltage VOH VOL IOH = –0.5 mA IOL = 1.0 mA 2.4 0.4 V V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product specification. 6 Data Sheet M14464EJ5V0DS µPD444012A-X 5 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(2/2) Parameter Symbol Test condition VCC ≥ 2.2 V Unit µPD444012A-CxxX MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Minimum cycle time, II/O = 0 mA ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V ISB2 CE2 ≤ 0.2 V VCC ≤ 2.7 V ISB3 /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V High level output voltage VOH IOH = –0.5 mA VCC ≤ 2.7 V Low level output voltage VOL IOL = 1.0 mA VCC ≤ 2.7 V 2.4 1.8 0.4 V VCC ≤ 2.7 V VCC ≤ 2.7 V VCC ≤ 2.7 V – – – 0.5 0.4 0.5 0.4 0.5 0.4 5 0.6 0.6 7 6 7 6 7 6 V mA VCC ≤ 2.7 V VCC ≤ 2.7 V – – – – – 40 25 4 2 6 mA –1.0 –1.0 TYP. MAX. +1.0 +1.0 µA µA µA Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification. Data Sheet M14464EJ5V0DS 7 µPD444012A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) 5 AC Test Conditions [ µPD444012A-B55X, µPD444012A-B70X, µPD444012A-B85X, µPD444012A-B10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 0.1 VCC Test points VCC/2 Output Waveform VCC/2 Test points VCC/2 Output Load 1TTL + 50 pF [ µPD444012A-C70X, µPD444012A-C85X, µPD444012A-C10X, µPD444012A-C12X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 0.1 VCC Test points VCC/2 Output Waveform VCC/2 Test points VCC/2 Output Load 1TTL + 30 pF 8 Data Sheet M14464EJ5V0DS µPD444012A-X 5 Read Cycle (1/2) (B version) Parameter Symbol VCC ≥ 3.0 V -B55X -B55X VCC ≥ 2.7 V -B70X -B85X -B10X Unit Condition µPD444012A µPD444012A µPD444012A µPD444012A µPD444012A MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid /LB, /UB to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tCO1 tCO2 tOE tBA tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 tHZ2 tOHZ tBHZ 10 10 10 0 10 20 20 20 20 50 50 50 50 30 50 10 10 10 0 10 20 20 20 20 55 55 55 55 30 55 10 10 10 0 10 25 25 25 25 70 70 70 70 35 70 10 10 10 0 10 30 30 30 30 85 85 85 85 40 85 10 10 10 0 10 35 35 35 35 100 100 100 100 50 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/2) (C version) Parameter Symbol VCC ≥ 2.2 V Unit Condition µPD444012A -C70X MIN. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid /LB, /UB to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tCO1 tCO2 tOE tBA tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 tHZ2 tOHZ tBHZ 10 10 10 0 10 25 25 25 25 70 70 70 70 35 70 MAX. µPD444012A -C85X MIN. 85 85 85 85 40 85 10 10 10 0 10 30 30 30 30 MAX. µPD444012A -C10X MIN. 100 100 100 100 50 100 10 10 10 0 10 35 35 35 35 MAX. µPD444012A -C12X MIN. 120 120 120 120 60 120 10 10 10 0 10 40 40 40 40 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Data Sheet M14464EJ5V0DS 9 µPD444012A-X Read Cycle Timing Chart tRC Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH CE2 (Input) tCO2 tLZ2 tHZ2 /OE (Input) tOE tOLZ /LB, /UB (Input) tBA tBLZ I/O (Output) High impedance Data out tBHZ tOHZ Remark In read cycle, /WE should be fixed to high level. 10 Data Sheet M14464EJ5V0DS µPD444012A-X 5 Write Cycle (1/2) (B version) Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Condition µPD444012A µPD444012A µPD444012A µPD444012A µPD444012A -B55X MIN. Write cycle time /CE1 to end of write CE2 to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tBW tAW tAS tWP tWR tDW tDH tWHZ tOW 5 50 45 45 45 45 0 40 0 25 0 20 5 MAX. -B55X MIN. 55 50 50 50 50 0 45 0 25 0 20 5 MAX. -B70X MIN. 70 55 55 55 55 0 50 0 30 0 25 5 MAX. -B85X MIN. 85 70 70 70 70 0 55 0 35 0 30 5 MAX. -B10X MIN. 100 80 80 80 80 0 60 0 40 0 35 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note Note The output load is 1TTL + 5 pF. Write Cycle (2/2) (C version) Parameter Symbol VCC ≥ 2.2 V Unit Condition µPD444012A -C70X MIN. Write cycle time /CE1 to end of write CE2 to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tBW tAW tAS tWP tWR tDW tDH tWHZ tOW 5 70 55 55 55 55 0 50 0 30 0 25 MAX. µPD444012A -C85X MIN. 85 70 70 70 70 0 55 0 35 0 30 5 MAX. µPD444012A -C10X MIN. 100 80 80 80 80 0 60 0 40 0 35 5 MAX. µPD444012A -C12X MIN. 120 100 100 100 100 0 85 0 60 0 40 5 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note Note The output load is 1TTL + 5 pF. Data Sheet M14464EJ5V0DS 11 µPD444012A-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tWP tWR tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 12 Data Sheet M14464EJ5V0DS µPD444012A-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tCW1 tWR tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. Data Sheet M14464EJ5V0DS 13 µPD444012A-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS CE2 (Input) tAW tWP /WE (Input) tCW2 tWR tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. 14 Data Sheet M14464EJ5V0DS µPD444012A-X Write Cycle Timing Chart 4 (/LB, /UB Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tWR tAS /LB, /UB (Input) tBW tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. Data Sheet M14464EJ5V0DS 15 µPD444012A-X 5 Low VCC Data Retention Characteristics (TA = –25 to +85°C) Parameter Symbol Test Condition VCC ≥ 2.7 V VCC ≥ 2.2 V Unit µPD444012A -B××X MIN. Data retention supply voltage VCCDR1 VCCDR2 VCCDR3 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V CE2 ≤ 0.2 V /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V Data retention supply current ICCDR2 ICCDR3 ICCDR1 VCC = 1.5 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V VCC = 1.5 V, CE2 ≤ 0.2 V VCC = 1.5 V, /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V Chip deselection to data retention mode Operation recovery time tR tRC Note µPD444012A -C××X TYP. MAX. 3.6 3.6 3.6 MIN. 1.0 1.0 1.0 TYP. MAX. 3.6 3.6 3.6 V 1.0 1.0 1.0 0.3 3.0 0.3 3.0 µA 0.3 0.3 3.0 3.0 0.3 0.3 3.0 3.0 tCDR 0 0 ns tRC Note ns Note tRC : Read cycle time 16 Data Sheet M14464EJ5V0DS µPD444012A-X Data Retention Timing Chart (1) /CE1 Controlled tCDR VCC VCC (MIN.) Note Data retention mode tR /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND 5 Note B version : 2.7 V, C version : 2.2 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) CE2 Controlled tCDR VCC VCC (MIN.) Note Data retention mode tR VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND 5 Note B version : 2.7 V, C version : 2.2 V Remark On the data retention mode by controlling CE2, The other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. Data Sheet M14464EJ5V0DS 17 µPD444012A-X (3) /LB, /UB Controlled tCDR VCC VCC (MIN.) Note Data retention mode tR /LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB ≥ VCC – 0.2 V VIL (MAX.) GND 5 Note B version : 2.7 V, C version : 2.2 V Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. 18 Data Sheet M14464EJ5V0DS µPD444012A-X Package Drawing 48-PIN PLASTIC TSOP(I) (12x18) 1 48 F G R detail of lead end Q 24 25 E P I J A L S S D K N S C MM B NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) ITEM A B C D E F G I J K L M N P Q R S MILLIMETERS 12.0 ± 0.1 0.45 MAX. 0.5 (T.P.) 0.22 ± 0.05 0.1 ± 0.05 1.2 MAX. 1.0 ± 0.05 16.4 ± 0.1 0.8 ± 0.2 0.145 ± 0.05 0.5 0.10 0.10 18.0 ± 0.2 3° +5° −3° 0.25 0.60 ± 0.15 S48GY-50-MJH1-1 Data Sheet M14464EJ5V0DS 19 µPD444012A-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD444012A-X. 5 Types of Surface Mount Device µPD444012AGY-BxxX-MJH: 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) µPD444012AGY-CxxX-MJH: 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) 20 Data Sheet M14464EJ5V0DS µPD444012A-X [ MEMO ] Data Sheet M14464EJ5V0DS 21 µPD444012A-X [ MEMO ] 22 Data Sheet M14464EJ5V0DS µPD444012A-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14464EJ5V0DS 23 µPD444012A-X • The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. 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