UPD4482181GF-C85

DATA SHEET MOS INTEGRATED CIRCUIT µPD4482161, 4482181, 4482321, 4482361 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION Description The µPD4482161 is a 524,288-word by 16-bit, the µPD4482181 is a 524,288-word by 18-bit, the µPD4482321 is a 262,144-word by 32-bit and the µPD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • 3.3 V or 2.5 V core supply • Synchronous operation • Operating temperature : TA = 0 to 70 °C (-A65, -A75, -A85, -C75, -C85) TA = −40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y) • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs for flow through operation • All registers triggered off positive clock edge • 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs • Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482321, µPD4482361) /BW1, /BW2, /BWE (µPD4482161, µPD4482181) Global write enable : /GW • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M14521EJ3V0DS00 (3rd edition) Date Published December 2002 NS CP(K) Printed in Japan The mark shows major revised points. 2000 µPD4482161, 4482181, 4482321, 4482361 Ordering Information Part number Access Time ns Clock Frequency MHz 133 117 100 133 117 100 133 117 100 133 117 100 117 100 117 100 117 100 117 100 2.5 ± 0.125 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL Core Supply Voltage V 3.3 ± 0.165 3.3 V LVTTL Note (1/2) I/O Interface Operating Temperature °C 0 to 70 100-pin PLASTIC LQFP (14 × 20) Package µPD4482161GF-A65 µPD4482161GF-A75 µPD4482161GF-A85 µPD4482181GF-A65 µPD4482181GF-A75 µPD4482181GF-A85 µPD4482321GF-A65 µPD4482321GF-A75 µPD4482321GF-A85 µPD4482361GF-A65 µPD4482361GF-A75 µPD4482361GF-A85 µPD4482161GF-C75 µPD4482161GF-C85 µPD4482181GF-C75 µPD4482181GF-C85 µPD4482321GF-C75 µPD4482321GF-C85 µPD4482361GF-C75 µPD4482361GF-C85 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 3.3 V or 2.5 V LVTTL Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz). 2 Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 (2/2) Part number Access Time ns Clock Frequency MHz 133 117 100 133 117 100 133 117 100 133 117 100 117 100 117 100 117 100 117 100 2.5 ± 0.125 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL Core Supply Voltage V 3.3 ± 0.165 3.3 V LVTTL Note I/O Interface Operating Temperature °C −40 to +85 Package µPD4482161GF-A65Y µPD4482161GF-A75Y µPD4482161GF-A85Y µPD4482181GF-A65Y µPD4482181GF-A75Y µPD4482181GF-A85Y µPD4482321GF-A65Y µPD4482321GF-A75Y µPD4482321GF-A85Y µPD4482361GF-A65Y µPD4482361GF-A75Y µPD4482361GF-A85Y µPD4482161GF-C75Y µPD4482161GF-C85Y µPD4482181GF-C75Y µPD4482181GF-C85Y µPD4482321GF-C75Y µPD4482321GF-C85Y µPD4482361GF-C75Y µPD4482361GF-C85Y 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 100-pin PLASTIC LQFP (14 × 20) 3.3 V or 2.5 V LVTTL Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz). Data Sheet M14521EJ3V0DS 3 µPD4482161, 4482181, 4482321, 4482361 Pin Configurations /××× indicates active low signal. 100-pin PLASTIC LQFP (14 x 20) [µPD4482161GF, µPD4482181GF] Marking Side /BWE /BW2 /BW1 /ADV /CE2 /GW CLK CE2 VDD VSS /AC /CE /AP NC NC A6 A7 A8 A9 /G 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC VDDQ VSSQ NC NC I/O9 I/O10 VSSQ VDDQ I/O11 I/O12 NC VDD NC VSS I/O13 I/O14 VDDQ VSSQ I/O15 I/O16 I/OP2, NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A18 NC NC VDDQ VSSQ NC I/OP1, NC I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS NC VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ NC NC NC NC A17 A10 A11 A12 A13 A14 A15 MODE Remark Refer to Package Drawing for the 1-pin index mark. 4 Data Sheet M14521EJ3V0DS A16 VDD VSS A5 A4 A3 A2 A1 A0 NC NC µPD4482161, 4482181, 4482321, 4482361 Pin Identification (µPD4482161GF, µPD4482181GF) Symbol A0 to A18 Pin No. 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 80 I/O1 to I/O16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23 I/OP1, NC Note Description Synchronous Address Input Synchronous Data In, Synchronous / Asynchronous Data Out Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity) Synchronous Burst Address Advance Input Synchronous Address Status Processor Input Synchronous Address Status Controller Input Synchronous Chip Enable Input Synchronous Byte Write Enable Input Synchronous Global Write Input Asynchronous Output Enable Input Clock Input Asynchronous Burst Sequence Select Input Do not change state during normal operation 74 24 83 84 85 98, 97, 92 93, 94, 87 88 86 89 31 I/OP2, NC Note /ADV /AP /AC /CE, CE2, /CE2 /BW1, /BW2, /BWE /GW /G CLK MODE ZZ VDD VSS VDDQ VSSQ NC 64 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground No Connection Note NC (No Connection) is used in the µPD4482161GF. I/OP1 and I/OP2 are used in the µPD4482181GF. Data Sheet M14521EJ3V0DS 5 µPD4482161, 4482181, 4482321, 4482361 100-pin PLASTIC LQFP (14 x 20) [µPD4482321GF, µPD4482361GF] Marking Side /BWE /BW4 /BW3 /BW2 /BW1 /ADV /CE2 /GW CE2 CLK VDD VSS /AC /CE /AP A6 A7 A8 A9 /G 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3, NC I/O17 I/O18 VDDQ VSSQ I/O19 I/O20 I/O21 I/O22 VSSQ VDDQ I/O23 I/O24 NC VDD NC VSS I/O25 I/O26 VDDQ VSSQ I/O27 I/O28 I/O29 I/O30 VSSQ VDDQ I/O31 I/O32 I/OP4, NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/OP2, NC I/O16 I/O15 VDDQ VSSQ I/O14 I/O13 I/O12 I/O11 VSSQ VDDQ I/O10 I/O9 VSS NC VDD ZZ I/O8 I/O7 VDDQ VSSQ I/O6 I/O5 I/O4 I/O3 VSSQ VDDQ I/O2 I/O1 I/OP1, NC VDD NC A17 A10 A11 A12 A13 A14 A15 MODE Remark Refer to Package Drawing for the 1-pin index mark. 6 Data Sheet M14521EJ3V0DS A16 VSS A5 A4 A3 A2 A1 A0 NC NC µPD4482161, 4482181, 4482321, 4482361 Pin Identification (µPD4482321GF, µPD4482361GF) Symbol A0 to A17 Pin No. Description 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 43 I/O1 to I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 I/OP1, NC Note Synchronous Data In, Synchronous / Asynchronous Data Out 51 80 1 30 83 84 85 98, 97, 92 93, 94, 95, 96, 87 88 86 89 31 Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity) I/OP2, NC Note I/OP3, NC Note I/OP4, NC /ADV /AP /AC /CE, CE2, /CE2 /BW1 to /BW4, /BWE /GW /G CLK MODE Note Synchronous Burst Address Advance Input Synchronous Address Status Processor Input Synchronous Address Status Controller Input Synchronous Chip Enable Input Synchronous Byte Write Enable Input Synchronous Global Write Input Asynchronous Output Enable Input Clock Input Asynchronous Burst Sequence Select Input Do not change state during normal operation ZZ VDD VSS VDDQ VSSQ NC 64 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 14, 16, 38, 39, 42, 66 Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground No Connection Note NC (No Connection) is used in the µPD4482321GF. I/OP1 to I/OP4 are used in the µPD4482361GF. Data Sheet M14521EJ3V0DS 7 µPD4482161, 4482181, 4482321, 4482361 Block Diagrams [µPD4482161, µPD4482181] A0 to A18 MODE /ADV CLK /AC /AP /BW1 /BW2 19 Address register 19 A0, A1 17 19 Binary Q1 A1’ counter and logic CLR Q0 A0’ Byte 1 Write register Byte 2 Write register 8/9 8/9 Byte 1 Write driver Byte 2 Write driver Row and column decoders Memory cell array 1,024 rows 512 × 16 columns (8,388,608 bits) 512 × 18 columns (9,437,184 bits) /BWE /GW /CE CE2 /CE2 /G Enable register 16/18 Input register 16/18 Output buffer 2 I/O1 to I/O16 I/OP1 to I/OP2 ZZ 16/18 Power down control Burst Sequence [µPD4482161, µPD4482181] Interleaved Burst Sequence Table (MODE = VDD) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A18 to A2, A1, A0 A18 to A2, A1, /A0 A18 to A2, /A1, A0 A18 to A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0 8 Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 [µPD4482321, µPD4482361] 18 Address register 18 A0, A1 16 18 A0 to A17 MODE /ADV CLK /AC /AP /BW1 /BW2 /BW3 /BW4 /BWE /GW /CE CE2 /CE2 /G Binary Q1 A1’ counter and logic CLR Q0 A0’ Byte 1 Write register Byte 2 Write register Byte 3 Write register Byte 4 Write register 8/9 8/9 8/9 8/9 Byte 1 Write driver Byte 2 Write driver Byte 3 Write driver Row and column decoders Memory cell array 1,024 rows 256 × 32 columns (8,388,608 bits) 256 × 36 columns (9,437,184 bits) 32/36 Input register Output buffer Byte 4 Write driver 32/36 Enable register 4 I/O1 to I/O32 I/OP1 to I/OP4 ZZ 32/36 Power down control Burst Sequence [µPD4482321, µPD4482361] Interleaved Burst Sequence Table (MODE = VDD) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A17 to A2, A1, A0 A17 to A2, A1, /A0 A17 to A2, /A1, A0 A17 to A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0 Data Sheet M14521EJ3V0DS 9 µPD4482161, 4482181, 4482321, 4482361 Asynchronous Truth Table Operation Read Cycle Read Cycle Write Cycle Deselected /G L H × × I/O Dout High-Z High-Z, Din High-Z Remark × : don’t care Synchronous Truth Table Operation Deselected Deselected Deselected Deselected Deselected Note Note Note Note Note /CE H L L L L L L × H × H L × H × H CE2 × L × L × H H × × × × H × × × × /CE2 × × H × H L L × × × × L × × × × /AP × L L H H L H H × H × H H × H × /AC L × × L L × L H H H H L H H H H /ADV × × × × × × × L L H H × L L H H /WRITE × × × × × × H H H H H L L L L L CLK L→H L→H L→H L→H L→H L→H L→H L→H L→H L→H L→H L→H L→H L→H L→H L→H Address None None None None None External External Next Next Current Current External Next Next Current Current Read Cycle / Begin Burst Read Cycle / Begin Burst Read Cycle / Continue Burst Read Cycle / Continue Burst Read Cycle / Suspend Burst Read Cycle / Suspend Burst Write Cycle / Begin Burst Write Cycle / Continue Burst Write Cycle / Continue Burst Write Cycle / Suspend Burst Write Cycle / Suspend Burst Note Deselect status is held until new “Begin Burst” entry. Remarks 1. × : don’t care 2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW or /GW is LOW. /WRITE = H means the following two cases. (1) /BWE and /GW are HIGH. (2) /BW1 to /BW4 and /GW are HIGH, and /BWE is LOW. 10 Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 Partial Truth Table for Write Enables [µPD4482161, µPD4482181] Operation Read Cycle Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / All Bytes Write Cycle / All Bytes /GW H H H H H L /BWE H L L L L × /BW1 × H L H L × /BW2 × H H L L × Remark × : don’t care [µPD4482321, µPD4482361] Operation Read Cycle Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / Byte 3 (I/O [17:24], I/OP3) Write Cycle / Byte 4 (I/O [25:32], I/OP4) Write Cycle / All Bytes Write Cycle / All Bytes /GW H H H H H H H L /BWE H L L L L L L × /BW1 × H L H H H L × /BW2 × H H L H H L × /BW3 × H H H L H L × /BW4 × H H H H L L × Remark × : don’t care ZZ (Sleep) Truth Table ZZ Chip Status Active Active Sleep ≤ 0.2 V Open ≥ VDD − 0.2 V Data Sheet M14521EJ3V0DS 11 µPD4482161, 4482181, 4482321, 4482361 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol VDD Conditions -A65, -A75, -A85 -A65Y, -A75Y, -A85Y -C75, -C85 -C75Y, -C85Y Output supply voltage Input voltage Input / Output voltage Operating ambient temperature Storage temperature Tstg VDDQ VIN VI/O TA -A65, -A75, -A85, -C75, -C85 -A65Y, -A75Y, -A85Y, -C75Y, -C85Y –0.5 –0.5 –0.5 0 –40 –55 VDD VDD + 0.5 VDDQ + 0.5 70 +85 +125 °C V V V °C 1, 2 1, 2 –0.5 +3.0 V MIN. –0.5 TYP. MAX. +4.0 Unit V Notes Notes 1. –2.0 V (MIN.)(Pulse width : 2 ns) 2. VDDQ + 2.3 V (MAX.)(Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions Parameter Symbol Conditions MIN. Supply voltage 2.5 V LVTTL interface Output supply voltage High level input voltage Low level input voltage 3.3 V LVTTL interface Output supply voltage High level input voltage Low level input voltage VDDQ VIH VIL 3.135 2.0 –0.3 Note (1/2) -A65, -A75, -A85 -A65Y, -A75Y, -A85Y TYP. 3.3 MAX. 3.465 V Unit VDD 3.135 VDDQ VIH VIL 2.375 1.7 –0.3 Note 2.5 2.9 VDDQ + 0.3 +0.7 V V V 3.3 3.465 VDDQ + 0.3 +0.8 V V V Note –0.8 V (MIN.)(Pulse width : 2 ns) Recommended DC Operating Conditions Parameter Symbol Conditions MIN. Supply voltage Output supply voltage High level input voltage Low level input voltage VDD VDDQ VIH VIL 2.375 2.375 1.7 –0.3 Note (2/2) -C75, -C85 -C75Y, -C85Y TYP. 2.5 2.5 MAX. 2.625 2.625 VDDQ + 0.3 +0.7 V V V V Unit Note –0.8 V (MIN.)(Pulse width : 2 ns) 12 Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Input leakage current I/O leakage current Operating supply current Symbol ILI ILO IDD Test condition VIN (except ZZ, MODE) = 0 V to VDD VI/O = 0 V to VDDQ, Outputs are disabled. Device selected, Cycle = MAX. VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA -A65 -A65Y -A75, -C75 -A75Y, -C75Y -A85, -C85 -A85Y, -C85Y IDD1 Suspend cycle, Cycle = MAX. /AC, /AP, /ADV, /GW, /BWEs ≥ VIH VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Standby supply current ISB Device deselected, Cycle = 0 MHz VIN ≤ VIL or VIN ≥ VIH, All inputs are static. ISB1 Device deselected, Cycle = 0 MHz VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V VI/O ≤ 0.2 V, All inputs are static. ISB2 Device deselected, Cycle = MAX. VIN ≤ VIL or VIN ≥ VIH Power down supply current 2.5 V LVTTL interface High level output voltage VOH IOH = –2.0 mA IOH = –1.0 mA Low level output voltage VOL IOL = +2.0 mA IOL = +1.0 mA 3.3 V LVTTL interface High level output voltage Low level output voltage VOH VOL IOH = –4.0 mA IOL = +8.0 mA 2.4 0.4 V V 1.7 2.1 0.7 0.4 V V ISBZZ ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V 15 mA 110 15 30 mA 150 200 225 MIN. –2 –2 TYP. MAX. +2 +2 250 Unit Note µA µA mA Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Clock input capacitance Symbol CIN CI/O Cclk Test condition VIN = 0 V VI/O = 0 V Vclk = 0 V MIN. TYP. MAX. 6.0 8.0 6.0 Unit pF pF pF Remark These parameters are periodically sampled and not 100% tested. Data Sheet M14521EJ3V0DS 13 µPD4482161, 4482181, 4482321, 4482361 AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions 2.5 V LVTTL interface Input waveform (Rise / Fall time ≤ 2.4 ns) 2.4 V 1.2 V VSS Test points 1.2 V Output waveform 1.2 V Test points 1.2 V 3.3 V LVTTL interface Input waveform (Rise / Fall time ≤ 3.0 ns) 3.0 V 1.5 V VSS Test points 1.5 V Output waveform 1.5 V Test points 1.5 V Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) External load at test VT = +1.2 V / +1.5 V 50 Ω ZO = 50 Ω I/O (Output) CL Remark CL includes capacitances of the probe and jig, and stray capacitances. 14 Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 Read and Write Cycle (2.5 V LVTTL Interface) Parameter Symbol -A65, -A75, -C75 -A65Y, -A75Y, -C75Y (117 MHz) Standard Cycle time Clock access time Output enable access time Clock high to output active Clock high to output change Output enable to output active TKHKH TKHQV TGLQV TKHQX1 TKHQX2 TGLQX Alias TCYC TCD TOE TDC1 TDC2 TOLZ TOHZ TCZ TCH TCL TAS TSS TDS TWS – – TAH TSH TDH TWH – – TZZE TZZR – – 8.6 8.6 – – 10.0 10.0 ns ns 0.5 – 0.5 – ns MIN. 8.6 – – 2.5 2.5 0 0 2.5 2.5 2.5 1.5 MAX. – 7.5 3.5 – – – 3.5 5.0 – – – MIN. 10.0 – – 2.5 2.5 0 0 2.5 2.5 2.5 2.0 -A85, -C85 -A85Y, -C85Y (100MHz) MAX. – 8.5 3.5 – – – 3.5 5.0 – – – ns ns ns ns ns ns ns ns ns ns ns Unit Note Output disable to output High-Z TGHQZ Clock high to output High-Z Clock high pulse width Clock low pulse width Setup times Address Address status Data in Write enable TKHQZ TKHKL TKLKH TAVKH TADSVKH TDVKH TWVKH Address advance TADVVKH Chip enable Hold times Address Address status Data in Write enable TEVKH TKHAX TKHADSX TKHDX TKHWX Address advance TKHADVX Chip enable Power down entry time Power down recovery time TKHEX TZZE TZZR Data Sheet M14521EJ3V0DS 15 µPD4482161, 4482181, 4482321, 4482361 Read and Write Cycle (3.3 V LVTTL Interface) Parameter Symbol -A65 -A65Y (133 MHz) Standard Cycle time Clock access time Output enable access time Clock high to output active Clock high to output change Output enable to output active TKHKH TKHQV TGLQV TKHQX1 TKHQX2 TGLQX Alias TCYC TCD TOE TDC1 TDC2 TOLZ TOHZ TCZ TCH TCL TAS TSS TDS TWS – – TAH TSH TDH TWH – – TZZE TZZR – – 7.5 7.5 – – 8.6 8.6 – – 10.0 10.0 ns ns 0.5 – 0.5 – 0.5 – ns MIN. 7.5 – – 2.5 2.5 0 0 2.5 2.5 2.5 1.5 MAX. – 6.5 3.5 – – – 3.5 5.0 – – – -A75 -A75Y (117 MHz) MIN. 8.6 – – 2.5 2.5 0 0 2.5 2.5 2.5 1.5 MAX. – 7.5 3.5 – – – 3.5 5.0 – – – -A85 -A85Y (100MHz) MIN. 10.0 – – 2.5 2.5 0 0 2.5 2.5 2.5 2.0 MAX. – 8.5 3.5 – – – 3.5 5.0 – – – ns ns ns ns ns ns ns ns ns ns ns Unit Note Output disable to output High-Z TGHQZ Clock high to output High-Z Clock high pulse width Clock low pulse width Setup times Address Address status Data in Write enable TKHQZ TKHKL TKLKH TAVKH TADSVKH TDVKH TWVKH Address advance TADVVKH Chip enable Hold times Address Address status Data in Write enable TEVKH TKHAX TKHADSX TKHDX TKHWX Address advance TKHADVX Chip enable Power down entry time Power down recovery time TKHEX TZZE TZZR 16 Data Sheet M14521EJ3V0DS READ CYCLE TKHKH CLK TADSVKH /AP TADSVKH /AC TAVKH Address A1 TKHAX A2 TADVVKH Data Sheet M14521EJ3V0DS TKHADSX TKHKL TKLKH TKHADSX A3 TKHADVX /ADV µPD4482161, 4482181, 4482321, 4482361 TWVKH /BWE /BWs TWVKH /GW TEVKH /CEsNote TKHEX TKHWX TKHWX /G High-Z TGLQV TGHQZ TKHQX2 High-Z Q1(A1) Q1(A2) TKHQV Q2(A2) Q3(A2) Q4(A2) Q1(A2) TKHQZ Q1(A3) High-Z Data In TGLQX High-Z Data Out Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Remark Qn(A2) refers to output from address A2. Q1 to Q4 refer to outputs according to burst sequence. 17 18 WRITE CYCLE TKHKH CLK TADSVKH TKHADSX /AP TADSVKH TKHADSX /AC TAVKH Address A1 TKHAX A2 TADVVKH /ADV TKHADVX A3 TKHKL TKLKH Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 /BWENote1 /BWs /GWNote1 TWVKH TWVKH TKHWX TKHWX /CEsNote2 TEVKH TKHEX /G High-Z TDVKH D1(A1) TGHQZ Data Out D1(A2) D2(A2) TKHDX D2(A2) D3(A2) D4(A2) D1(A3) D2(A3) D3(A3) Data In High-Z Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. READ / WRITE CYCLE TKHKH CLK TKHKL TADSVKH TKHADSX /AP TADSVKH TKHADSX /AC TAVKH Address A1 TKHAX A2 TADVVKH Data Sheet M14521EJ3V0DS TKLKH A3 TKHADVX /ADV µPD4482161, 4482181, 4482321, 4482361 TWVKH /BWENote1 /BWs TWVKH /GWNote1 TEVKH /CEsNote2 TKHEX TKHWX TKHWX /G High-Z Data In TKHQV High-Z TKHQX1 Data Out TGHQZ TDVKH D1(A2) TGLQX Q1(A3) Q2(A3) Q3(A3) Q4(A3) TKHDX High-Z Q1(A1) High-Z High-Z Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 19 20 SINGLE READ / WRITE CYCLE TKHKH CLK TKHKL TADSVKH TKHADSX /AC TAVKH TKHAX Address A1 A2 A3 A4 A5 TWVKH TKHWX /BWE Note1 /BWs TWVKH TKHWX Data Sheet M14521EJ3V0DS TKLKH A6 A7 A8 A9 /GW Note1 TEVKH /CEs Note2 TKHEX µPD4482161, 4482181, 4482321, 4482361 /G TDVKH TKHDX Data In TGLQV TGLQX Q1(A1) Q1(A2) Q1(A3) Q1(A4) High-Z D1(A5) TGHQZ D1(A6) D1(A7) High-Z TKHQV High-Z Q1(A8) TKHQZ Note3 Data Out High-Z Q1(A9) Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. Outputs are disabled within one clock cycle after deselect. 3. Remark /AP is HIGH and /ADV is don't care. POWER DOWN (ZZ) CYCLE TKHKH CLK TKHKL /AP TKLKH /AC Address Data Sheet M14521EJ3V0DS A1 A2 µPD4482161, 4482181, 4482321, 4482361 /ADV /BWE /BWs /GW /CEs /G High-Z Data Out High-Z TZZE ZZ TZZR Q1(A1) Q1(A2) Q2(A2) Power Down (ISBZZ) State 21 22 STOP CLOCK CYCLE TKHKH CLK TKHKL /AP TKLKH /AC Address A1 A2 /ADV Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 /BWE /BWs /GW /CE /G High-Z Data In High-Z Data Out High-Z Q1(A1) High-Z Q1(A2) Q2(A2) Power Down State (ISB1)Note Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V µPD4482161, 4482181, 4482321, 4482361 Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 100 1 31 30 F G H I M J K P S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.0 ± 0.2 20.0 ± 0.2 14.0 ± 0.2 16.0 ± 0.2 0.825 0.575 0.32 + 0.08 − 0.07 0.13 0.65 (T.P.) 1.0 ± 0.2 0.5 ± 0.2 0.17 + 0.06 − 0.05 0.10 1.4 0.125 ± 0.075 3°+7° −3° 1.7 MAX. S100GF-65-8ET-1 Data Sheet M14521EJ3V0DS 23 µPD4482161, 4482181, 4482321, 4482361 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD4482161, 4482181, 4482321 and 4482361. Types of Surface Mount Devices µPD4482161GF : 100-pin PLASTIC LQFP (14 x 20) µPD4482181GF : 100-pin PLASTIC LQFP (14 x 20) µPD4482321GF : 100-pin PLASTIC LQFP (14 x 20) µPD4482361GF : 100-pin PLASTIC LQFP (14 x 20) 24 Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 Revision History Edition/ Date This edition 3rd edition/ Dec. 2002 Throughout Page Previous edition Throughout Modification Addition Type of revision Location Description (Previous edition → This edition) − − Timing Chart Preliminary Data Sheet → Data Sheet Extended operating temperature products (TA = −40 to +85 °C) p.20 − Addition SINGLE READ / WRITE CYCLE Data Sheet M14521EJ3V0DS 25 µPD4482161, 4482181, 4482321, 4482361 [MEMO] 26 Data Sheet M14521EJ3V0DS µPD4482161, 4482181, 4482321, 4482361 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14521EJ3V0DS 27 µPD4482161, 4482181, 4482321, 4482361 • The information in this document is current as of December, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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