UPD46128953F1-EB1

PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT μPD46128953-X 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION Description The μPD46128953-X is a high speed, low power, 134,217,728 bits (4,194,304 words by 32 bits) CMOS Mobile Specified RAM featuring synchronous burst read and synchronous burst write function. The μPD46128953-X realizes high performance with the SDR interface, command and data inputs / outputs are synchronized the rising edge of clock. The μPD46128953-X is fabricated with advanced CMOS technology using one-transistor memory cell. Features • 4,194,304 words by 32 bits organization • Low voltage operation: 1.7 to 2.0 V (1.85±0.15 V) • Operating ambient temperature: TA = −25 to +85 °C • Synchronous burst mode Burst length : 8 double words (Wrap) Burst sequence : Linear burst Maximum clock frequency : 83 / 66 MHz • SDR (Single Data Rate) Architecture One data transfers per one clock cycle All inputs/outputs are synchronized with the positive edge of the clock • Write data mask (DM) for write operation • Output Enable: /OE pin • Chip Enable input: /CE1 pin • Standby Mode input: CE2 pin • Standby Mode 1: Normal standby (Memory cell data hold valid) • Standby Mode 2: Density of memory cell data hold is variable μPD46128953 Clock frequency MHz (MAX.) -E12X -E15X Note Operating supply voltage V 1.7 to 2.0 Operating ambient temperature °C −25 to +85 60 55 Supply current At operating mA (MAX.) At standby μA (MAX.) 83 66 T.B.D. Note Under consideration The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M17506EJ1V1DS00 (1st edition) Date Published September 2005 CP (K) Printed in Japan 2005 μPD46128953-X Ordering Information μPD46128593-X is mainly shipping by wafer. Please consult with our sales offices for package samples and ordering information. 2 Preliminary Data Sheet M17506EJ1V1DS μPD46128953-X Pin Configuration The following is pin configuration of package sample. /xxx indicates active low signal. 127-pin PLASTIC FBGA (13.0 x 11.5) Top View 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDE FGH J K LMNP PNML K J HGF EDCB A Bottom View Top View A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NC NC NC NC NC NC NC NC NC NC NC B NC NC NC NC DQ28 DQ29 DQ30 DQ31 NC NC VSS NC DQ26 DQ27 NC NC /WE CLK DM0 NC NC NC DQ25 NC NC NC CE2 /ADV DM1 NC NC DM2 DQ24 NC NC NC NC /WAIT NC NC NC DM3 VDD NC NC NC NC NC NC NC NC VDD VSSQ NC NC DQ23 NC A/DQ15 DQ22 VSS A/DQ7 A/DQ21 NC C D E F G H J K L M N NC NC NC P NC NC NC A/DQ20 A/DQ19 A/DQ14 A/DQ18 A/DQ5 NC A/DQ11 A/DQ2 A/DQ8 NC NC A/DQ17 A/DQ16 VDDQ VSSQ NC NC NC NC NC NC NC NC NC NC NC A/DQ6 A/DQ13 A/DQ12 NC VDD A/DQ1 VSSQ NC VSS A/DQ4 A/DQ3 A/DQ9 /OE NC NC VDDQ VDDQ A/DQ10 A/DQ0 /CE1 NC A/DQ0 to A/DQ021 : Address inputs , Data inputs/ outputs DQ22 to DQ31 /CE1 CE2 /WE /OE CLK /ADV : Data inputs / outputs : Chip select input : Standby mode input : Write enable input : Output enable input : Clock input : Address valid /WAIT VDD VSS VDDQ VSSQ NC Note : Wait output : Power supply : Ground : Power supply for DQ : Ground for DQ : No Connection DM0 to DM3 : Write data mask input Note Some signals can be applied because this pin is not internally connected. Remark Refer to 10. Package Drawing for the index mark. Preliminary Data Sheet M17506EJ1V1DS 3 μPD46128953-X Pin Function (1/2) Symbol A/DQ0 to A/DQ21 Synchronous address input/data input/output These pins are used as address input pins and data input/output pins. When they are used as address input pins, the input address is latched at the rising edge of CLK. When the address is latched, the setup time and hold time must be satisfied at the rising edge of CLK. When they are used as data input/output pins, the input data is latched at the rising edge of CLK. When data is input, the setup time and hold time must be satisfied at the rising edge of CLK. Data is output from these pins at the rising edge of CLK. DQ22 to DQ31 Synchronous data input/output. While the A/DQ pins function as address input pins and data input/output pins, these pins function only as data input/output pins. The input data is latched at the rising edge of CLK. When data is input, the setup time and hold time must be satisfied at the rising edge of CLK. Data is output at the rising edge of CLK. CLK Input clock. Addresses and control signals are latched in synchronization with this signal. All the synchronous input signals must satisfy the setup time and hold time at the rising edge of CLK. /ADV Synchronous address valid input signal. An address is latched at the rising edge of CLK while /ADV is LOW. When the address is latched, the setup time and hold time must be satisfied at the rising edge of CLK. Note: This signal serves as an asynchronous signal when the mode register set or read. /CE1 Synchronous chip enable input. This device is active while /CE1 is LOW. When inputting /CE1, the setup time and hold time must be satisfied at the rising edge of CLK. Remark This signal serves as an asynchronous signal when the mode register set or read. CE2 Asynchronous power-down mode input When this signal is made LOW, the device enters the power-down mode status. CE2 is not synchronized with the clock. It is an asynchronous signal. /OE Synchronous output enable input. When this signal is made LOW, read data is output. When inputting /OE, the setup time and hold time must be satisfied at the rising edge of CLK. Remark This signal serves as an asynchronous signal when the mode register set or read. /WE Synchronous write enable input. When /WE inputs a LOW at the same time as /ADV, the device recognizes a write operation. When inputting /WE, the setup time and hold time must be satisfied at the rising edge of CLK. Remark This signal serves as an asynchronous signal when the mode register is set or read. Description 4 Preliminary Data Sheet M17506EJ1V1DS μPD46128953-X (2/2) Symbol DM0 to DM3 Synchronous write data mask input. These signals can mask write data during burst write. To input data mask, the setup time and hold time must be satisfied at the rising edge of CLK. Data mask can be controlled in byte units. DM0: A/DQ0 to ADQ7 DM1: A/DQ8 to ADQ15 DM2: A/DQ16 to ADQ21, DQ22 to DQ23 DM3: DQ24 to DQ31 /WAIT Synchronous wait output. /WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready. The wait signal is output at the rising edge of CLK. VDD Supply voltage: Usually, the supply voltage is 1.85 V. Refer to DC Characteristics and Recommended Operation Conditions. VSS VDDQ Supply voltage: Ground Supply voltage: Supply voltage for DQ. Usually, this voltage is 1.85 V. Refer to DC Characteristics and Recommended Operation Conditions. VSSQ NC Supply voltage: Ground for DQ. No connection Some signals can be applied because this pin is not internally connected. Description Preliminary Data Sheet M17506EJ1V1DS 5 μPD46128953-X Block Diagram VDD Standby mode control VSS VDDQ VSSQ Refresh control Refresh state control Refresh counter Row decoder Address buffer Memory cell array 134,217,728 bits /ADV Address latch Sense amplifier / Switching circuit Column decoder /CE1 /WAIT CE2 /WE Command control Burst counter Data control Latch circuit CLK Clock control Input / Output buffer DM0 to DM3 /OE A/DQ0 to A/DQ21 DQ22 to DQ31 6 Preliminary Data Sheet M17506EJ1V1DS μPD46128953-X Truth Table Mode Deselect (Standby Mode 1) Power Down (Standby Mode 2) Output Disable Start Address Latch Note2 Note3 Note1 /CE1 H × L CE2 H L H CLK /ADV × /OE × × H H × H H × × /WE × × × × × H L × × A/DQ0-A/DQ21 , DQ22-DQ31 High-Z High-Z High-Z High-Z Low-Z or High-Z High-Z High-Z Low-Z to High-Z High-Z × × × L H L L Start Address not Latch Read Command input Write Command input Note2 Note2 Note4 Note4 Burst Read Termination Burst Write Termination L to H × × Notes 1. 2. 3. 4. Remark CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition). Start address latch and read/write command input are performed at the next rising edge of clock when /ADV is transferred HIGH to LOW. It is impossible that Start address latch and read/write command input are performed at the first rising edge of clock during /ADV is fixed HIGH. Refer to 3.6 Burst Read Termination, 3.7 Burst Write Termination. H, HIGH: VIH, L, LOW: VIL, ×: VIH or VIL For read/write operation, refer to 7 Timing Charts. Preliminary Data Sheet M17506EJ1V1DS 7 μPD46128953-X CONTENTS 1. Initialization ................................................................................................................................................ 10 2. Partial Refresh ........................................................................................................................................... 11 2. 1 Standby Mode......................................................................................................................................................... 11 2. 2 Density Switching ................................................................................................................................................... 11 2. 3 Standby Mode Status Transition............................................................................................................................. 11 2. 4 Addresses for Which Partial Refresh Is Supported................................................................................................. 12 3. Burst Operation ......................................................................................................................................... 13 3. 1 Features of Burst Operation ................................................................................................................................... 13 3. 2 Latency ................................................................................................................................................................... 13 3. 3 Burst Length, Burst Sequence, Wrap Around ......................................................................................................... 16 3. 4 Burst Read End ...................................................................................................................................................... 17 3. 5 Burst Write End ...................................................................................................................................................... 18 3. 6 Burst Read Termination.......................................................................................................................................... 19 3. 7 Burst Write Termination .......................................................................................................................................... 20 3. 8 /WAIT signal behavior............................................................................................................................................. 21 3. 9 /WAIT output........................................................................................................................................................... 21 4. Mode Register Settings............................................................................................................................. 23 4. 1 Mode Register Setting Method ............................................................................................................................... 23 4. 1. 1 Cautions for Setting Mode Register............................................................................................................. 23 4. 1. 2 Mode Register Setting/Reading................................................................................................................... 25 4. 1. 3 Partial refresh Density ................................................................................................................................. 25 4. 1. 4 Burst length ................................................................................................................................................. 25 4. 1. 5 Function mode............................................................................................................................................. 26 4. 1. 6 Driver strength ............................................................................................................................................. 26 4. 1. 7 Read Latency .............................................................................................................................................. 26 4. 1. 8 Single Write ................................................................................................................................................. 26 4. 1. 9 Valid Clock Edge ......................................................................................................................................... 26 4. 1. 10 Reset to Asynchronous.............................................................................................................................. 26 4. 1. 11 /WE control................................................................................................................................................ 26 4. 1. 12 Setting of unused bits ................................................................................................................................ 26 4. 2 Mode Register Reading .......................................................................................................................................... 27 4. 2. 1 Cautions for Setting Mode Register............................................................................................................. 27 4. 2. 2 Data read from mode register...................................................................................................................... 27 5. Address, /OE, /WE, DM control ................................................................................................................ 29 5. 1 Relation of address inputs and /OE control ............................................................................................................ 29 5. 2 Address Latching .................................................................................................................................................... 30 5. 3 Read / Write Command Loading............................................................................................................................. 32 5. 4 /OE control during burst read operation.................................................................................................................. 34 5. 4. 1 /OE HIGH to LOW during burst read operation ........................................................................................... 34 5. 4. 2 /OE LOW to HIGH during burst read operation ........................................................................................... 35 5. 5 Write data mask signal (DM) control....................................................................................................................... 36 5. 5. 1 Controlling write data mask signal (DM) in write cycle ................................................................................. 36 5. 5. 2 Write data mask (DM) truth table................................................................................................................. 37 8 Preliminary Data Sheet M17506EJ1V1DS μPD46128953-X 6. Electrical Specifications ........................................................................................................................... 38 7. Timing Charts............................................................................................................................................. 43 8. Mode Register Setting/Read Timing........................................................................................................ 49 8. 1 Mode Register Setting Timing ................................................................................................................................ 49 8. 2 Mode Register Setting Flow Chart .......................................................................................................................... 50 8. 3 Mode Register Read Timing ................................................................................................................................... 51 8. 4 Mode Register Read Flow Chart............................................................................................................................. 52 9. Standby Mode Timing Charts................................................................................................................... 53 10. Package Drawing..................................................................................................................................... 54 11. Recommended Soldering Conditions ................................................................................................... 55 Preliminary Data Sheet M17506EJ1V1DS 9 μPD46128953-X 1. Initialization Initialize the μPD46128953-X at power application using the following sequence to stabilize internal circuits. (1) Following power application, make CE2 HIGH after fixing CE2 to LOW for the period of tVHMH. Make /CE1 HIGH before making CE2 HIGH. (2) /CE1 and CE2 are fixed HIGH for the period of tMHCL. Normal operation is possible after the completion of initialization. Figure 1-1. Initialization Timing Chart Initialization Normal Operation /CE1 (Input) tCHMH tVHMH CE2 (Input) tMHCL VDD VDD (MIN.) Cautions 1. 2. Make CE2 LOW when starting the power supply. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VDD (MIN.)). Initialization Timing Parameter Power application to CE2 LOW hold /CE1 HIGH to CE2 HIGH Following power application CE2 HIGH hold to /CE1 LOW Symbol tVHMH tCHMH tMHCL MIN. 50 0 300 MAX. Unit μs ns μs 10 Preliminary Data Sheet M17506EJ1V1DS μPD46128953-X 2. Partial Refresh 2. 1 Standby Mode In addition to the regular standby mode (Standby Mode 1) with a 128M bits density, Standby Mode 2, which performs partial refresh, is also provided. 2. 2 Density Switching In Standby Mode 2, the densities that can be selected for performing refresh are 64M bits, 32M bits, 16M bits, and 0M bit. The density for performing refresh can be set with the mode register. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. (For how to perform mode register settings, refer to section 4. Mode Register Settings.) 2. 3 Standby Mode Status Transition In Standby Mode 1, /CE1 and CE2 are HIGH. In Standby Mode 2, CE2 is LOW. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 64M bits, 32M bits, or 16M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from Standby Mode 2. For the timing charts, refer to Figure 9-1. Standby Mode 2 (data hold: 64M bits / 32M bits / 16M bits) Entry / Exit Timing Chart, Figure 9-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart. Preliminary Data Sheet M17506EJ1V1DS 11 μPD46128953-X Figure 2-1. Standby Mode State Machine Power On Initialization Mode Register Setting CE2 = V IH /CE1 = V IL Active CE2 = V IL /CE1 = V IH, CE2 = V IH CE2 = V IL /CE1 = V IL, CE2 = V IH /CE1 = V IL, CE2 = V IH Standby Mode 1 CE2 = V IL Standby Mode 2 (64M bits / 32M bits / 16M bits) CE2 = V IL Standby Mode 2 (Data not held) 2. 4 Addresses for Which Partial Refresh Is Supported Data hold density 64M bits 32M bits 16M bits Correspondence address 000000H to 1FFFFFH 000000H to 0FFFFFH 000000H to 07FFFFH 12 Preliminary Data Sheet M17506EJ1V1DS μPD46128953-X 3. Burst Operation 3. 1 Features of Burst Operation Function Burst Length Burst Wrap Burst Sequence Valid Clock Edge Latency Count Read Latency Write Latency 8 double words Wrap Linear CLK Rising Edge 6, 7, 8 5, 6, 7 Features 3. 2 Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through Mode Register Set sequence after power-up. Once RL is set through Mode Register Set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL−1. Latency Count Grade -E12X -E15X Clock Frequency