UPD63210

DATA SHEET µPD63210,63210L 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO MOS INTEGRATED CIRCUIT DESCRIPTION The µPD63210 is a 16-bit dual D/A converter IC for digital audio demodulation, which incorporates an 8-times oversampling digital filter and operational amplifiers for analog post filters. With few external parts and an easy substrate design (as to 1-bit D/A), it is suitable for multimedia terminals, MPEG audio equipment, video CDs, game machines, and electronic musical instruments, etc. To cope with sets for portable applications, a low-voltage operating version µPD63210L (lowest operating supply voltage = +3.0 V) is also available. FEATURES • 16-bit resistor string D/A converter (2-channel) adopted S/N = 104 dBTYP.; DR = 96 dBTYP. (when VDD = 5.0 V) • High-performance 8-times oversampling digital filter incorporated Pass band ripple : ±0.003 dB Stop band rejection : 90 dB • System clock 384/512fs selectable • Serial input data format selectable Format for 2’S compliment, MSB first, and backward justification data accommodated; Input can be selected between 16- and 18 bits • Full line of low-voltage operating products (µPD63210L) µPD63210 : VDD = 4.5 to 5.5 V µPD63210L : VDD = 3.0 to 5.5 V • Wide operating temperature range (TA = –40 to +85 °C) • Operational amplifier (2-channel) for D/A converter output incorporated • Operational amplifier (2-channel) for post filter (LPF) configuration incorporated • Digital de-emphasis function (fs = 32/44.1/48 kHz) incorporated • Soft mute function incorporated • CD double-speed playback function (when µPD63210: 384fs) • 28-pin plastic SOP (375 mil) adopted ORDERING INFORMATION Part Number Package 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) Quality Grade Standard µPD63210GT µPD63210LGT The information in this document is subject to change without notice. Document No. S11585EJ2V1DS00 (2nd edition) (Previous No. ID-3466) Date Published September 1996 P Printed in Japan © 1996 µPD63210, 63210L BLOCK DIAGRAM ANIR AOR + - APIR ANIL APIL AOL RO LO + LREF Resistor strings D/A converter (L-channel) RREF Resistor strings D/A converter (R-channel) XTI 8-times oversampling digital filter Timing generator XTO MCKO DSEL RST Deemphasis circuit Input interface circuit BSEL SDI LRCKI DEFS1 DEFS2 CKSEL SMUTE 2 TSEL BCKI µPD63210, 63210L PIN CONFIGURATION (Top View) TSEL RST XTO XTI MCKO CKSEL BCKI SDI LRCKI DEFS1 DEFS2 DSEL SMUTE BSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DVDD AVDD LO AOL ANIL APIL LREF RREF APIR ANIR AOR RO AGND DGND TSEL RST XTO XTI : Test selection input : Reset input : Oscillation part output pin : Oscillation part input pin DGND : Digital ground AGND : Analog ground RO AOR : D/A converter output (R channel) : Filter amplifier output (R channel) MCKO : Master clock output CKSEL : Clock selection input BCKI SDI : Bit clock input : Serial data input ANIR : Filter amplifier inverting input (R channel) APIR : Filter amplifier non-inverting input (R channel) RREF : Reference (R channel) LREF : Reference (L channel) APIL AOL LO : Filter amplifier non-inverting input (L channel) : Filter amplifier output (L channel) : D/A converter output (L channel) ANIL : Filter amplifier inverting input (L channel) LRCKI : LR clock input DEFS1 : De-emphasis select input 1 DEFS2 : De-emphasis select input 2 DSEL BSEL : Double-speed playback select input : Data bit count select input SMUTE : Soft mute control input AV DD : Analog power supply DV DD : Digital power supply 3 µPD63210, 63210L 1. PIN FUNCTIONS Table 1-1. List of Pin Functions Pin No. 1 2 Symbol TSEL RST I/O I I Function Test selection Reset pin Description Normal operation: L H: System reset “H” period > 1/128fs Example: 0.18 µs or more when fs = 44.1 kHz 3 4 5 6 7 8 9 10 XTO XTI MCKO CKSEL BCKI SDI LRCKI DEFS1 O I O I I I I I Oscillation part output pin Oscillation part input pin Master clock output Clock selection Bit clock input Data input LR clock input De-emphasis switching 1 H: 512fs, L: 384fs Refer to timing chart 11 DEFS2 I De-emphasis switching 2 L DEFS2 DEFS1 L OFF H 48.0 kHz H 44.1 kHz 32.0 kHz 12 DSEL I Double-speed playback switching H: Double speed accommodated; L: Normal “H” can be selected only when using the µPD63210GT in 384fs mode (CKSEL = L) (double-speed operation assured). Attenuated at the rising edge. Amplified at the trailing edge. MUTE OFF at “L”. H: 18 bits; L: 16 bits 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SMUTE BSEL DGND AGND RO AOR ANIR APIR RREF LREF APIL ANIL AOL LO AVDD DVDD I I O O I I I I O O - Soft mute selection Bit selection Digital GND Analog GND DAC output Rch Filter amplifier output Rch Filter amplifier inverting input Rch Filter amplifier non-inverting input Rch Rch reference pin Lch reference pin Filter amplifier non-inverting input Lch Filter amplifier inverting input Lch Filter amplifier output Lch DAC output Lch Analog VDD Digital VDD 4 µPD63210, 63210L 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A = 2 5 °C, DGND = AGND = 0V unless otherwise specified) Parameter Supply voltage Input voltage Permissive dissipation Storage temperature Symbol DVDD, AV DD V IN PD T stg Rating –0.3 to +7.0 –0.3 to DV DD + 0.3 285 (T a = 8 5 ° C) –40 to +125 Unit V V mW °C Recommended Operating Range (DGND = AGND = 0V) Parameter Supply voltage Operating temperature Output load resistance Symbol DV DD, AV DD T opt RL Condition µ PD63210 µ PD63210L MIN. 4.5 3.0 –40 5 10 TYP. 5.0 3.3 +25 MAX. 5.5 5.5 +85 Unit V °C kΩ µ PD63210; 17,18,25,26 pins µ PD63210L; 17,18,25,26 pins ELECTRICAL SPECIFICATIONS DC Characteristics ( µ PD63210: DV DD = A V DD = 4 .5 to 5.5 V, DGND = AGND = 0 V, T a = – 40 to +85 ° C unless otherwise specified) ( µ PD63210L: DV DD = A V DD = 3 .0 to 5.5 V, DGND = AGND = 0 V, T a = – 40 to +85 ° C unless otherwise specified) Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Current consumption (total) Symbol V IH V IL IL V OH V OL I DD Condition 1, 2, 6, 7, 8, 9, 10, 11, 12, 13, and 14 pins 1, 2, 6, 7, 8, 9, 10, 11, 12, 13, and 14 pins 1, 2, 6, 7, 8, 9, 10, 11, 12, 13, and 14 pins, T a = 2 5 ° C 5 pin, I OH = – 2.0 mA 5 pin, I OL = 2 .0 mA DV DD = A V DD = 5 .0 V DV DD = A V DD = 3 .3 V ( µ PD63210L) MIN. 0.7DV DD TYP. MAX. Unit V V 0.3DV DD –1.2 DV DD –0.4 24 14 +0.4 50 50 – +1.2 µA V V mA mA 5 µPD63210, 63210L AC Characteristics ( µ PD63210: DV DD = A V DD = 4 .5 to 5.5 V, DGND = AGND = 0 V, Ta = – 40 to +85 ° C unless otherwise specified) ( µ PD63210L: DV DD = A V DD = 3 .0 to 5.5 V, DGND = AGND = 0 V, T a = – 40 to +85 ° C unless otherwise specified) Parameter Oscillator frequency Master clock frequency Master clock pulse width (“H” section) Master clock pulse width (“L” section) BCK pulse width (“H” section) BCK pulse width (“L” section) BCK pulse cycle Data setup time Data hold time LRCK setup time LRCK hold time SMUTE pulse width (“H” section) Symbol fX f MCK t MWH t MWL t BWH t BWL t BW t DS t DH t LRS t LRH t SMWH Condition Crystal oscillation: 384fs; 512fs External clock input: 384fs; 512fs External clock input: 384fs; 512fs External clock input: 384fs; 512fs MIN. 10 10 10 10 25 19 25 19 150 150 310 100 100 100 100 8/fs TYP. 16.9344 22.5792 16.9344 22.5792 MAX. 19.2 25.6 19.2 25.6 Unit MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns tMWH VIH XTI VIL tMWL tBW tBWH VIH BCKI 0.5 * DVDD VIL tBWL tDS tDH SDI 0.5 * DVDD tLRH tLRS LRCKI 0.5 * DVDD 6 µPD63210, 63210L D/A Converter Characteristics µ PD63210 (T A = 2 5 ° C, DV DD = A V DD = 5 .0 V, DGND = AGND =0 V, f x = 1 6.933 MHz fs = 4 4.1 kHz, 16 bits, DAC output) Parameter Resolution Noise distortion rate Full-scale output voltage S/N ratio Crosstalk Dynamic range LPF amplifier output voltage swing LPF amplifier output voltage swing Symbol RES THD V FS S/N C.T D.R V AOH V AOL Condition f IN = 1 k Hz, 0 dB 17-/26-pins, f IN = 1 K Hz JIS-A filter Single-channel 0dB, fIN = 1 K Hz f IN = 1 k Hz, –60 dB RL ≥ 5 kΩ RL ≥ 5 kΩ MIN. TYP. 16 0.025 2.0 104 98 96 4.92 0.02 MAX. 0.09 2.3 Unit Bit % V P-P dB dB dB V V 1.7 98 93 92 4.75 0.25 µ PD63210L (T A = 2 5 ° C, DV DD = A V DD = 3 .3 V, DGND = AGND =0 V, fx = 1 6.9344 MHz f s = 4 4.1 kHz, 16 bits, DAC output) Parameter Resolution Noise distortion rate Full-scale output voltage S/N ratio Crosstalk Dynamic range LPF amplifier output voltage swing LPF amplifier output voltage swing Symbol RES THD V FS S/N C.T D.R V AOH V AOL Condition f IN = 1 k Hz, 0 dB 17-/26-pins, f IN = 1 K Hz JIS-A filter Single-channel 0dB, fIN = 1 K Hz f IN = 1 k Hz, –60 dB R L ≥ 10 kΩ R L ≥ 10 kΩ MIN. TYP. 16 0.03 1.32 100 96 94 3.22 0.02 MAX. 0.09 1.52 Unit Bit % V P-P dB dB dB V V 1.12 94 90 89 3.05 0.25 7 µPD63210, 63210L 3. OPERATION 3.1 Operation Clock (1) Selection of system clocks System clocks are selected by the CKSEL (No.6) pin. Table 3-1. Selection of System Clocks System Clock 384fs 512fs CKSEL L H (2) Generation of operation clock The clock required for internal operation can be generated by configuring a crystal oscillator circuit as shown in Figure 3-1. Figure 3-1. Crystal Oscillator Circuit Configuration To dynamic generator MCKO XTO 970 kΩ XTI Crystal 20 to 30 pF As in Figure 3-2, the clock can also be generated by supplying a system clock from outside to the XTI (No.4) pin. The system clock waveform at this time must satisfy the conditions in the electrical specifications (such as VIH, VIL under DC characteristics; and tMCK, tMWHM, tMWL under AC characteristics). Figure 3-2. Configuration When Providing System Clock Externally To dynamic generator MCKO XTO XTI (No connection required) External system clock input 8 µPD63210, 63210L 3.2 Data Input Circuit (1) Input data format Data on MSB first, 2’s compliment, and backward justification is input. (2) Selection of input data bit length An input data bit length is selected by the BSEL (No.14) pin. Table 3-2. Selection of Input Data Bit Length Input Data Bit Length 16 bits 18 bits BSEL L H (3) Data input timing chart SDI and LRCKI is incorporated in the internal shift register at the rising edge of BCKI. The SDI, LRCKI, and BCKI waveforms must satisfy the conditions in the electrical specifications (such as VIH, VIL under DC characteristics; and tBWH, tBWL, tBW, tDS, tDH, tLRS, and tLRH under AC characteristics). SDI considers the 16 bits (when BSEL = L; 18 bits when BSEL = H) preceding the change point of LRCKI to be valid data. Regarding the combination of system clock selection and input data length selection, the conditions for inputtable BCKI are shown in Table 3-3. Table 3-3. Limitations on BCKI 512fs 384fs (CKSEL = H) (CKSEL = L) 16 bits 18 bits 16 bits 18 bits (BSEL = L) (BSEL = H) (BSEL = L) (BSEL = H) - BCKI 32fs 48fs 64fs The data input timing charts are shown in Figure 3-3 and Figure 3-4. Figure 3-3. Data Input Timing Chart (when BSEL = L) BCKI Continuous MSB LSB Continuous MSB LSB SDI Invalid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Invalid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Lch data LRCKI 1/fs Rch data Figure 3-4. Data Input Timing Chart (when BSEL = H) BCKI Continuous MSB LSB Continuous MSB LSB SDI Invalid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Invalid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Lch data LRCKI 1/fs Rch data 9 µPD63210, 63210L 3.3 Digital Filter The 8-times oversampling FIR digital filter is used to attenuate the image out of band noise component, thus facilitating the analog filter designing. The configuration of the digital filter is shown in Figure 3-5. The characteristics of the digital filter are shown in Figures 3-6 and 3-7. Figure 3-5. Configuration of Digital Filter (Input) fs 1st 127th FIR filter 2fs 2nd 23rd FIR filter 4fs 3rd 11th FIR filter 8fs (Output) Figure 3-6. Frequency Characteristics of Digital Filter 0 –40 Gain (dB) –80 –120 0 1 2 3 4 5 Frequency (fS) 6 7 8 Figure 3-7. Intraband Ripple Characteristics of Digital Filter 0.005 Gain (dB) 0 –0.005 0 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 Frequency (fS) 0.5 10 µPD63210, 63210L 3.4 Digital De-emphasis Function The IIR digital filter performs de-emphasis operations. The filter can cope with three types of sampling frequencies (32/44.1/48 KHz) by using the DEFS1 (No.10) and DEFS2 (No.11) pins. Table 3-4. Selection of De-emphasis Filter De-emphasis OFF 32 kHz 44.1 kHz 48 kHz DEFS1 L H L H DEFS2 L H H L 3.5 Soft Mute Function The soft mute function can be realized by control of the SMUTE (No.13) pin. When applying the mute, set the value to SMUTE = H. By this, the output level of the D/A converter is attenuated from 0dB to negative infinity (- ∞ ) in 128 steps. The time required for a complete mute is 1024/fs. When cancelling the mute, set the value to SMUTE = L. By this, the output level of the D/A converter is increased from negative infinity (- ∞ ) to 0dB in 128 steps. Figure 3-8 shows the relationship between the control of the SMUTE pin and the output level of the D/A converter. When initializing by resetting the system, the mute is cancelled and the output level of the D/A converter reaches the maximum (0dB). Don’t input the narrower “H” pulse than 8/fs to pin 13, or analog output signal may become unstable. In this case, the unstable condition may be kept until system reset or power off. Figure 3-8. Operation of Soft Mute Function H SMUTE L 0 dB D/A converter output level -∞ 1024/fs 11 µPD63210, 63210L 3.6 CD Double-Speed Playback Function (µPD63210 only) The CD double-speed playback function can be selected by the DSEL (No.12) pin. For selection of the system clock, please set the value to 384 fs (CKSEL = L). The µ PD63210L does not have this function. Table 3-5. System Clock Selection in Normal/Double-Speed Playback Parameter XTI input clock frequency XTI frequency in CD playback MCKO output clock frequency L (Normal) 384fs 16.9344 MHz (fs = 44.1 kHz) 384fs DSEL H (Double-speed) 192fs 16.9344 MHz (fs = 88.2 kHz) 192fs 3.7 System Reset The system is reset by inputting the H pulse into the RST (No.2) pin. The high level width to be input should be at least 1/128 fs. For example, if fs = 44.1 KHz, the system reset can be executed by entering the H signal whose pulse is at least 0.18 µ s wide. 12 µPD63210, 63210L 3.8 Configuration of Analog LPF Because the stop band rejection of the built-in 8-times oversampling digital filter is large (90 dB), the configuration of the analog LPF can be simple. Furthermore, by incorporating the output buffer (BUFF) of the D/A converter and the operational amplifier for LPF configuration, an analog LPF can be configured based on an extremely small number of external components. LPF’s cutoff frequency can be set with an external constant in accordance with the sampling frequency. Figure 3-9 shows the configuration of the D/A converter output section. As such, an LPF is configured by inserting an RC circuit between the BUFF output and AMP input. This diagram shows an example of configuring a Butterworth filter whose gain is 0 dB. In this case, R1 becomes the load of the BUFF output pin; therefore, ensure that the selection satisfies the electrical specifications (RL of the recommended operation range). LPF Configuration Example Conditions Cutoff frequency : fc = 30 kHz Configuration Gain IC used : Primary Butterworth : 0 dB : µ PD63210 ¨ Parts constants R1 = 7.5 k Ω C1 = 680 pF Figure 3-9. Configuration of D/A Converter Output Section (Configuration of Analog LPF) LPF Lch DAC BUFF(L) DF LPF Rch DAC BUFF(R) RO LO ANIL APIL + AOL Lch analog out AMP(L) R1 C1 APIR ANIR + - AOP Rch analog out AMP(R) 13 µPD63210, 63210L 4. APPLICATION CIRCUIT EXAMPLE An application circuit example in using crystal oscillation circuits is shown in Figure 4-1. Figure 4-1. Application Circuit Example in Using Crystal Oscillation Circuits 1 TSEL RESET CONTROL 20 to 30 pF x 2 2 RST 3 XTO 4 XTI 5 MCKO 6 CKSEL 7 BCKI SERIAL DATA INPUT 8 SDI 9 LRCKI 10 DEFS1 11 DEFS2 MODE CONTROL 12 DSEL 13 SMUTE 14 BSEL DVDD 28 AVDD 27 LO 26 AOL 25 ANIL 24 APIL 23 LREF 22 0.1 µ F 0.1 µ F LPF + + Digital VDD Analog VDD CRYSTAL 970 kΩ SYSTEM CLOCK OUT MODE CONTROL Lch AUDIO OUT µ PD63210 Note + 47 µ F RREF 21 + APIR 20 ANIR 19 AOR 18 RO 17 AGND 16 DGND 15 LPF 47 µ F Rch AUDIO OUT Note In this example, reference capacitors (21-/22-pin external capacitors) are installed independently. Even if these are realized in a common system (one 47µF), they will not cause any operational problems. However, the crosstalk may be deteriorated slightly (by several dB); therefore, please decide after evaluating the samples provided. Analog GND Digital GND 5. CAUTIONS (1) Shock noise countermeasure It is recommended that the analog mute circuit be connected to the next stage before using the converter. Without a mute circuit, shock noises may occur when the power is turned on. (2) Resetting Reset the system when switching over the input data bit length, the system clock, the digital deemphasis, or the CD double-speed playback. System reset must be executed after both master clock and LR clock become stable. If master clock or LR clock becomes unstable after system reset, the analog output signal may be unstable. 14 µPD63210, 63210L 6. PACKAGE DRAWING 28 PIN PLASTIC SOP (375 mil) 28 15 detail of lead end 1 A 14 H 3° +7° –3° G I J F E K C D MM P28GT-50-375B-1 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 18.2 MAX. 0.845 MAX. 1.27 (T.P.) 0.40+0.10 –0.05 0.125 ± 0.075 2.9 MAX. 2.50 ± 0.2 10.3 ± 0.3 7.2 ± 0.2 1.6 ± 0.2 0.15+0.10 –0.05 0.8 ± 0.2 0.12 0.10 INCHES 0.717 MAX. 0.034 MAX. 0.050 (T.P.) 0.016+0.004 –0.003 0.005 ± 0.003 0.115 MAX. 0.098+0.009 –0.008 0.406+0.012 –0.013 0.283+0.009 –0.008 0.063 ± 0.008 0.006+0.004 –0.002 0.031+0.009 –0.008 0.005 0.004 B N L 15 µPD63210, 63210L 7. RECOMMENDED SOLDERING CONDITIONS The solder mounting of this product should be conducted under the following conditions. For details of the recommended soldering conditions, please refer to the information document “ Semiconductor Device Mounting Technology Manual” (C10535E) . For soldering methods and conditions other than those recommended, please contact an NEC salesperson. Table 7-1. Soldering Conditions µ PD63210GT : 28-pin plastic SOP (375 mil) µ PD63210LGT : 28-pin plastic SOP (375 mil) Soldering Method Infrared reflow Soldering Condition Package peak temperature: 235 ° C; time: within 30 secs (at no lower than 210 ° C); count: twice (1) The second reflow should be started after the temperature of the device, which would have changed due to the first reflow, has returned to normal. (2) Please avoid flux water washing after the first reflow. Package peak temperature: 215 ° C; time: within 40 secs (at no lower than 200 ° C); count: once (1) The second reflow should be started after the temperature of the device, which would have changed due to the first reflow, has returned to normal. (2) Please avoid flux water washing after the first reflow. Solder bath temperature: no higher than 260 ° C, time: within 10 secs; count: once Preheating temperature: up to 120 ° C (package surface temperature) Pin part temperature: no higher than 300 ° C; time: within 3 secs (per device side) Recommended Condition Symbol IR35-00-2 VPS VP15-00-2 Wave soldering WS60-00-1 Pin part heating - Caution Please avoid using two or more soldering methods at the same time (except for the pin part heating method). 16 µPD63210, 63210L NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 17 µPD63210, 63210L [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5