UPD63335

PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET Rev. 01 — 29 March 2004 Product data 1. Product profile 1.1 Description Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. 1.2 Features s Logic level threshold s Very low on-state resistance. 1.3 Applications s Motors, lamps, solenoids s DC-to-DC converters s Uninterruptible power supplies s General industrial applications. 1.4 Quick reference data s VDS ≤ 75 V s Ptot ≤ 230 W s ID ≤ 75 A s RDSon ≤ 8.5 mΩ. 2. Pinning information Table 1: 1 2 3 mb Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simplified outline and symbol Simplified outline [1] Pin Description gate (g) drain (d) source (s) mounting base; connected to drain (d) Symbol mb d mb g s MBB076 2 1 MBK106 3 MBK116 123 SOT78 (TO-220AB) [1] SOT404 (D2-PAK) It is not possible to make connection to pin 2 of the SOT404 package. Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 3. Ordering information Table 2: Ordering information Package Name PHP110NQ08LT PHB110NQ08LT TO-220AB D2-PAK Description Version Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads SOT78 Plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404 Type number 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 °C peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 75 A; tp = 0.15 ms; VDD ≤ 75 V; RGS = 50 Ω; VGS = 10 V; starting Tj = 25 °C Tmb = 25 °C; VGS = 10 V; Figure 2 and 3 Tmb = 100 °C; VGS = 10 V; Figure 2 Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 175 °C 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ Min −55 −55 Max 75 75 ±20 75 75 240 230 175 175 75 240 560 Unit V V V A A A W °C °C A A mJ Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 2 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 120 Pder (%) 80 03aa16 120 Ider (%) 80 03ap56 40 40 0 0 50 100 150 200 Tmb (°C) 0 0 50 100 150 200 Tmb (°C) P tot P der = ---------------------- × 100 % P ° tot ( 25 C ) ID I der = ------------------- × 100 % I ° D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 103 ID (A) 03ap58 Limit RDSon = VDS / ID tp = 10 µ s 102 1 ms 10 ms DC 10 100 ms 1s 1 1 10 102 VDS (V) 103 Tmb = 25 °C; IDM is single pulse; VGS = 10 V Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 3 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 5. Thermal characteristics Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ 60 50 Max 0.65 Unit K/W K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient SOT78 SOT404 vertical in still air mounted on printed-circuit board; minimum footprint; vertical in still air. Symbol Parameter 5.1 Transient thermal impedance 1 Zth(j-mb) (K/W) δ = 0.5 03ap57 0.2 10-1 0.1 0.05 0.02 P single pulse tp T 10-2 10-4 10-3 10-2 10-1 tp (s) 1 t δ= tp T Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 4 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 175 °C Tj = −55 °C IDSS drain-source leakage current VDS = 75 V; VGS = 0 V Tj = 25 °C Tj = 175 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±10 V; VDS = 0 V VGS = 10 V; ID = 25 A; Figure 7 and 8 Tj = 25 °C Tj = 175 °C VGS = 5 V; ID = 25 A; Figure 7 and 8 VGS = 4.5 V; ID = 25 A; Figure 8 Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 reverse recovery time recovered charge IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V VDD = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 ID = 25 A; VDD = 60 V; VGS = 10 V; Figure 13 127.3 12.5 54.5 6631 905 610 47 185 424 226 0.77 70 213 1.2 nC nC nC pF pF pF ns ns ns ns V ns nC 7.2 15.1 7.6 8.5 17.9 9 9.95 mΩ mΩ mΩ mΩ 2 10 500 100 µA µA nA 1 0.5 1.5 2 2.2 V V V 75 70 V V Conditions Min Typ Max Unit Source-drain diode 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 5 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 240 Tj = 25 °C ID (A) 160 03ap59 10 V 5 V 75 ID (A) 50 VDS > ID x RDSon 03ap61 3.4 V 3V 80 2.6 V 25 Tj = 175 °C 25 °C VGS = 2.2 V 0 0 1 2 3 VDS (V) 4 0 0 1 2 VGS (V) 3 Tj = 25 °C Tj = 25 °C and 175 °C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 20 RDSon (mΩ) 15 Tj = 25 °C 03ap60 2.4 a 03nb25 2.6 V VGS = 3 V 3.4 V 1.6 10 5V 10 V 5 0.8 0 0 80 160 ID (A) 240 0 -60 0 60 120 T (°C) 180 j Tj = 25 °C R DSon a = ---------------------------R DSon ( 25 °C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. Fig 7. Drain-source on-state resistance as a function of drain current; typical values. 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 6 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 2.5 VGS(th) (V) 2 max 03aa33 10-1 ID (A) 10-2 03aa36 1.5 typ 10-3 min typ max 1 min 10-4 0.5 10-5 0 -60 0 60 120 Tj (°C) 180 10-6 0 1 2 VGS (V) 3 ID = 1 mA; VDS = VGS Tj = 25 °C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 105 C (pF) 104 03ap63 Ciss 103 Coss Crss 102 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 7 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 75 IS (A) 50 VGS = 0 V 03ap62 10 VGS (V) 8 ID = 25 A Tj = 25 °C 03ap64 6 14 V 4 25 175 °C Tj = 25 °C 2 VDD = 60 V 0 0 0.3 0.6 0.9 VSD (V) 1.2 0 0 50 100 QG (nC) 150 Tj = 25 °C and 175 °C; VGS = 0 V ID = 25 A; VDD = 14 V and 60 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 8 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 7. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 E p A A1 q D1 mounting base D L1(1) L2 Q L b1 1 2 3 b c e e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1(1) 3.30 2.79 L2 max. 3.0 p 3.8 3.6 q 3.0 2.7 Q 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC 3-lead TO-220AB EIAJ SC-46 EUROPEAN PROJECTION ISSUE DATE 00-09-07 01-02-16 Fig 14. SOT78 (TO-220AB). 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 9 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A E A1 mounting base D1 D HD 2 Lp 1 3 b c Q e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-06-25 01-02-12 Fig 15. SOT404 (D2-PAK). 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 10 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 8. Revision history Table 6: Rev Date 01 20040329 Revision history CPCN Description Product data (9397 750 12924) 9397 750 12924 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 11 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET 9. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 11. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 9397 750 12924 Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 29 March 2004 12 of 13 Philips Semiconductors PHP/PHB110NQ08LT N-channel TrenchMOS™ logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 5.1 6 7 8 9 10 11 12 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 © Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 29 March 2004 Document order number: 9397 750 12924