UPD6379LGR

DATA SHEET MOS INTEGRATED CIRCUIT µPD6379, 6379A, 6379L, 6379AL 2-CHANNEL 16-BIT D/A CONVERTER FOR AUDIO APPLICATION The µPD6379 and 6379A are 2-channel 16-bit D/A converters for digital audio signal demodulation. These D/A converters employ the resistor string conversion method which has been tested by existing model µPD6376 but they are more compact and require fewer external components than the µPD6376. In addition, low-voltage models, the µPD6379L and 6379AL (minimum operating supply voltage = +3.0 V) are also available for applications in portable systems. FEATURES • Resistor string conversion method • 0-point digital shift circuit • × 4 oversampling Sampling frequency: 200 kHz MAX. • Signal processing format for 2’s complement, MSB first, and backward justification data accommodated • Left and right in-phase output • High performance (at VDD = +5.0 V) S/N ratio: 100 dB TYP. Dynamic range: 96 dB TYP. • Low-voltage models available • Bipolar LR clock (LRCK) • Low power dissipation: 10 mW TYP. (with µPD6379L, 6379AL at VDD = +3.3 V) LRCK Supply voltage +3.3 V (VDD = +3.0 to 5.5 V) +5.0 V (VDD = +4.5 to 5.5 V) LRCK = L when L-ch data is input LRCK = H when L-ch data is input µPD6379L µPD6379 µPD6379AL µPD6379A • Few external components Internal output operational amplifier Only one electrolytic capacitor required for smoothing reference voltage, instead of two capacitors required by existing D/A converters • Small package: 8-pin plastic SOP (5.72 mm (225)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S11588EJ4V0DS00 (4th edition) Date Published November 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1996 µPD6379, 6379A, 6379L, 6379AL ORDERING INFORMATION Part number Package 8-pin plastic SOP (5.72 mm (225)) 8-pin plastic SOP (5.72 mm (225)) 8-pin plastic SOP (5.72 mm (225)) 8-pin plastic SOP (5.72 mm (225)) µPD6379GR µPD6379LGR µPD6379AGR µPD6379ALGR BLOCK DIAGRAM REF L. OUT Main DAC Shift register latch LRCK CLK Timing generator Sub DAC GND Sub DAC SI Main DAC R. OUT VDD 2 Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL PIN CONFIGURATIONS (Top View) 8-pin plastic SOP (5.72 mm (225)) • µPD6379GR, 6379LGR LRCK SI CLK VDD 1 2 3 4 8 7 6 5 L. OUT GND REF R. OUT • µPD6379AGR, 6379ALGR R. OUT REF GND L. OUT 1 2 3 4 8 7 6 5 VDD CLK SI LRCK Remark The pin configuration of the µPD6379 and 6379L is different from that of the µPD6379A and 6379AL. Data Sheet S11588EJ4V0DS00 3 µPD6379, 6379A, 6379L, 6379AL 1. PIN FUNCTIONS Table 1-1 Pin Functions Pin No. µPD6379, 6379L 1 µPD6379A, 6379AL 5 Name Symbol I/O Function Left/Right Clock LRCK Input Input pin to identify left or right input data. µPD6379, 6379L: Input “L” to this pin when inputting L-ch data to SI pin. µPD6379A, 6379AL: Input “H” to this pin when inputting L-ch data to SI pin. 2 6 Serial Input SI Input Serial data input pin. Input data on 2’s complement, MSB first, and backward justification. 3 4 5 6 7 8 7 8 1 2 3 4 Clock Supply Voltage R-ch Output Reference Voltage Ground L-ch Output CLK VDD R. OUT REF GND L. OUT Input – Output – – Output Serial input data read clock (bit clock) input pin Positive power supply pin Right analog signal output pin Reference voltage pin. Connect this pin to GND through capacitor. GND pin Left analog signal output pin 4 Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL 2. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Supply voltage Input voltage Output voltage Permissible package power dissipation Operating ambient temperature Storage temperature Symbol VDD VI VO PD Ratings – 0.3 to +7.0 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 220 (TA = 75 ˚C) Unit V V V mW °C °C TA Tstg –20 to +75 –40 to +125 Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Data Sheet S11588EJ4V0DS00 5 µPD6379, 6379A, 6379L, 6379AL µPD6379, 6379A RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage Logic input voltage (HIGH) Logic input voltage (LOW) Operating ambient temperature Output load resistance Conversion frequency Clock frequency Clock pulse width SI, LRCK setup time SI, LRCK hold time Symbol VDD VIH VIL TA RL fS fCLK tSCK tDC tCD 40 12 12 R. OUT, L. OUT pins Condition MIN. 4.5 0.7 VDD 0 –20 5 200 10 +25 TYP. 5.0 MAX. 5.5 VDD 0.3 VDD +75 Unit V V V °C kΩ kHz MHz ns ns ns ELECTRICAL CHARACTERISTICS (TA = 25 °C, VDD = +5 V, fS = 176.4 kHz) Parameter Resolution Total harmonic distortion Full-scale output voltage S/N ratio Dynamic range Crosstalk Current dissipation Symbol RES THD VFS S/N D.R C.T IDD With A-weight filter fIN = 1 kHz, –60 dB One side channel = 0 dB, fIN = 1 kHz fIN = 1 kHz, 0 dB 93 89 82 fIN = 1 kHz, 0 dB Condition MIN. TYP. 16 0.04 2.0 100 96 96 5 12 0.09 2.3 MAX. Unit Bit % Vp-p dB dB dB mA 6 Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL µPD6379L, 6379AL RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage Logic input voltage (HIGH) Logic input voltage (LOW) Operating ambient temperature Output load resistance Conversion frequency Clock frequency Clock pulse width SI, LRCK setup time SI, LRCK hold time Symbol VDD VIH VIL TA RL fS fCLK tSCK tDC tCD 40 12 12 R. OUT, L. OUT pins Condition MIN. 3.0 0.7 VDD 0 –20 10 200 10 +25 TYP. 3.3 MAX. 5.5 VDD 0.3 VDD +75 Unit V V V °C kΩ kHz MHz ns ns ns ELECTRICAL CHARACTERISTICS (TA = 25 °C, VDD = +3.3 V, fS = 176.4 kHz) Parameter Resolution Total harmonic distortion Full-scale output voltage S/N ratio Dynamic range Crosstalk Current dissipation Symbol RES THD VFS S/N D.R C.T IDD With A-weight filter fIN = 1 kHz, –60 dB One side channel = 0 dB, fIN = 1 kHz fIN = 1 kHz, 0 dB 93 89 82 fIN = 1 kHz, 0 dB Condition MIN. TYP. 16 0.04 1.32 98 93 93 3 6 0.09 1.52 MAX. Unit Bit % Vp-p dB dB dB mA Data Sheet S11588EJ4V0DS00 7 µPD6379, 6379A, 6379L, 6379AL Timing Chart CLK LSB SI 16 MSB 1 2 3 4 N LRCK ( µ PD6379A, 6379AL) LRCK ( µ PD6379, 6379L) L. OUT (L-ch) (R-ch) 5 6 7 8 9 LSB 10 11 12 13 14 15 16 MSB 1 2 3 4 N 5 6 7 8 9 10 11 (L-ch) (R-ch) N–1 R. OUT N–1 t SCK t SCK CLK t DC SI t CD CLK LRCK t DC t CD 8 Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL 3. APPLICATION CIRCUIT EXAMPLE µ PD6379 µ PD6379A µ PD6379L µ PD6379AL LRCK L.OUT SI CLK VDD + VCC + – + Signal processor LRCKO SO BCKO L-ch output GND REF R.OUT 47 µ F + 1 VCC 2 VCC + + 47 µ F 0.1 µ F 1 VCC 2 – R-ch output VDD Data Sheet S11588EJ4V0DS00 9 µPD6379, 6379A, 6379L, 6379AL 4. NOTES ON USE (1) Input signal format • Input data must be input as 2’s complement, MSB first, and backward justification. 2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers. See the table below. 2’s Complement Decimal Number L.OUT, R.OUT Pin Voltage TYP. (V) (Reference Values)Note 1 VDD = 5.0 V +32767 +32766 ······ 3.0 ·················· VDD = 3.3 VNote 2 1.98 ·················· (MSB) 0111 0111 1111 1111 ······ 1111 1111 (LSB) 1111 1110 0000 0000 1111 0000 0000 1111 ······ 0000 0000 1111 0001 0000 1111 +1 0 –1 ······ 2.0 ·················· 1.32 ·················· 1000 1000 0000 0000 0000 0000 0001 0000 –32767 –32768 1.0 0.66 Notes 1. Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature. 2. µPD6379L, 6379AL • Make sure that the delimiter of each bit of the data (SI) and the changing timing of LRCK coincide with the falling edge of CLK. • It is necessary that 16 clocks be input during 1 sample data period (16 bits). Make sure that the time width of 1 bit coincides with one cycle of the clock. • In the input data, the 16 bits preceding the change point of LRCK (shown in “1 sample data period” in Fig. 4-1, and Fig. 4-2) are considered to be valid data and are incorporated for use in D/A conversion. 10 Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL • If the clock is also supplied to CLK while data is not sampled (refer to Fig. 4-1), make sure that the changing timing of LRCK coincides with the falling edge (point A) of CLK after the LSB has been input. Fig. 4-1 Input Timing Chart (1) A 1 sample data period A CLK LSB SI 16 Invalid MSB 1 2 3 4 5 6 7 8 LSB 9 10 11 12 13 14 15 16 Invalid MSB 1 2 3 4 LRCK • If the clock is supplied to CLK only while data is sampled (refer to Fig. 4-2), set the changing timing of LRCK in between the falling edge (point A) of CLK after the LSB has been input and the start of inputting the next MSB (point B) (points A and B are included). Fig. 4-2 Input Timing Chart (2) A B 1 sample data period A B CLK LSB SI 16 Invalid MSB 1 2 3 4 5 6 7 8 LSB 9 10 11 12 13 14 15 16 Invalid MSB 1 2 3 4 LRCK Changing period of LRCK Changing period of LRCK Data Sheet S11588EJ4V0DS00 11 µPD6379, 6379A, 6379L, 6379AL (2) Output signal updating timing The L.OUT and R.OUT signals are updated after the input of 3.5 clocks following the change point indicating the end of the LRCK pin R-ch data input period. Therefore, when the clock is supplied to CLK only during D/A conversion, the clock must be stopped after the L.OUT and R.OUT signals corresponding to the last input data are output. Be aware that the L.OUT and R.OUT signals corresponding to the last sample data are not output, especially when the clock is supplied to CLK only during a sample data period. Fig. 4-3 Output Timing Chart (1) (for continuous clocks) 3.5 CLK CLK MSB SI 1 2 3 4 LSB 13 14 15 16 Invalid MSB 1 2 3 4 LSB 13 14 15 16 Invalid 1 2 3 L-ch data (N) LRCK (µPD6379, 6379L) LRCK (µPD6379A, 6379AL) R-ch data (N) Delay L-ch output (N–1) L-ch output (N) L.OUT R.OUT R-ch output (N–1) R-ch output (N) Fig. 4-4 Output Timing Chart (2) (when there is an interval which the clock is stopped) 3.5 CLK CLK stop CLK MSB SI 1 2 3 4 LSB 13 14 15 16 Invalid L-ch data (N) LRCK (µPD6379, 6379L) LRCK (µPD6379A, 6379AL) MSB 1 2 3 4 LSB 13 14 15 16 Invalid 1 2 3 4 5 CLK stop R-ch data (N) Delay L-ch output (N–1) L-ch output (N) R-ch output (N) L.OUT R.OUT R-ch output (N–1) (3) Countermeasures against shock noise It is recommended that a mute circuit be connected to the next stage of the D/A converter. If a mute circuit is not provided, shock noise may occur when power is applied. 12 Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL 5. PACKAGE DRAWING 8-PIN PLASTIC SOP (5.72 mm (225)) 8 5 detail of lead end P 1 A 4 H F G I J S B C D E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 5.2 + 0.17 − 0.20 0.78 MAX. 1.27 (T.P.) 0.42 + 0.08 − 0.07 0.1 ± 0.1 1.59 ± 0.21 1.49 6.5 ± 0.3 4.4 ± 0.15 1.1 ± 0.2 0.17 + 0.08 − 0.07 0.6 ± 0.2 0.12 0.10 3°+7° −3° S8GM-50-225B-6 L K N S M M Data Sheet S11588EJ4V0DS00 13 µPD6379, 6379A, 6379L, 6379AL 6. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met for soldering conditions of the product. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. Table 6-1 Soldering Conditions µPD6379GR, 6379AGR, 6379LGR, 6379ALGR : 8-pin plastic SOP (5.72 mm (225)) Soldering Process Infrared ray reflow Soldering Conditions Peak temperature of package surface: 235 °C or below, Reflow time: 30 seconds or less (at 210 °C or higher), Number of reflow processes: MAX. 2. Peak temperature of package surface: 215 °C or below, Reflow time: 40 seconds or less (at 200 °C or higher), Number of reflow processes: MAX. 2. Solder temperature: 260 °C or below, Flow time: 10 seconds or less, Pre-heating temperature: 120 °C or below (Package surface), Number of flow processes: MAX. 1. Terminal temperature: 300 °C or below, Time: 3 seconds or less (Per one side of the device). Symbol IR35-00-2 VPS VP15-00-2 Wave soldering WS60-00-1 Partial heating method — Caution Do not apply more than one soldering method at any one time, except for “Partial heating method”. 14 Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S11588EJ4V0DS00 15 µPD6379, 6379A, 6379L, 6379AL [MEMO] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8