UPD70F3025A

DATA SHEET µPD70F3003A, 70F3025A V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER MOS INTEGRATED CIRCUIT DESCRIPTION The µPD70F3003A and µPD70F3025A have a flash memory instead of the internal mask ROM of the µPD703003A/ 703004A and µPD703025A, respectively. This model is useful for small-scale production of a variety of application sets or early start of production since the program can be written and erased by the user even with the µPD70F3003 mounted on the board. Functions in detail are described in the following user’s manuals. Be sure to read these manuals when you design your systems. V853 User’s Manual-Hardware : U10913E V850 FamilyTM User’s Manual-Architecture : U10243E FEATURES • Compatible with µPD703003A, 703004A and 703025A • Can be replaced with mask ROM model for mass production of application set µPD70F3003A → µPD703003A, 703004A µPD70F3025A → µPD703025A • Internal memory Flash memory: 128K bytes (µPD70F3003A) 256K bytes (µPD70F3025A) Remark For differences among the products, refer to 1. DIFFERENCES AMONG PRODUCT. ORDERING INFORMATION Part Number Package 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Note Maximum Operating Frequency (MHz) 25 33 25 33 µPD70F3003AGC-25-8EU µPD70F3003AGC-33-8EU µPD70F3025AGC-25-8EUNote µPD70F3025AGC-33-8EU Note Under development The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13189EJ3V0DS00 (3rd edition) Date Published May 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1998 µPD70F3003A, 70F3025A PIN CONFIGURATION (Top View) • 100-Pin Plastic LQFP (fine pitch) (14 × 1 4 mm) µ PD70F3003AGC-25-8EU µ PD70F3003AGC-33-8EU µ PD70F3025AGC-25-8EU µ PD70F3025AGC-33-8EU P30/TO130 P27/SCK1 P26/RXD1/SI1 P25/TXD1/SO1 P24/SCK0 P23/RXD0/SI0 P22/TXD0/SO0 P21/PWM1 P20/PWM0 NMI VDD VSS P17/INTP123/SCK2 P16/INTP122/SI2 P15/INTP121/SO2 P14/INTP120 P13/TI12 P12/TCLR12 P11/TO121 P10/TO120 AVDD AVSS AVREF1 P77/ANI7 P76/ANI6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Caution Connect VPP pin to VSS pin except the case that µPD70F3003A or 70F3025A is used in flash memory programming mode. 2 P43/AD3 P42/AD2 VSS VDD P41/AD1 P40/AD0 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRO WAIT VPP MODE RESET CVDD/CKSEL X2 X1 CVSS CLKOUT VSS VDD P110/TO140 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P31/TO131 P32/TCLR13 P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P63/A19 P62/A18 P61/A17 P60/A16 VSS VDD P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 ANO0 ANO1 AVREF2 AVREF3 P07/INTP113/ADTRG P06/INTP112 P05/INTP111 P04/INTP110 P03/TI11 P02/TCLR11 P01/TO111 P00/TO110 P117/INTP143 P116/INTP142 P115/INTP141 P114/INTP140 P113/TI14 P112/TCLR14 P111/TO141 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A PIN NAMES A16-A19 AD0-AD15 ADTRG ANI0-ANI7 ANO0, ANO1 ASTB AV DD AV REF1-AV REF3 AV SS CV DD CV SS CKSEL CLKOUT DSTB HLDAK HLDRQ INTP120-INTP123, INTP130-INTP133, INTP140-INTP143 LBEN MODE NMI P00-P07 P10-P17 P20-P27 P30-P37 : Lower Byte Enable : Mode : Non-maskable Interrupt Request : Port0 : Port1 : Port2 : Port3 : Address Bus : Address/Data Bus : AD Trigger Input : Analog Input : Analog Output : Address Strobe : Analog V DD : Analog Reference Voltage : Analog V SS : Power Supply for Clock Generator : Ground for Clock Generator : Clock Select : Clock Output : Data Strobe : Hold Acknowledge : Hold Request P40-P47 P50-P57 P60-P63 P70-P77 P90-P96 P110-P117 PWM0, PWM1 RESET R/W RXD0, PXD1 SCK0-SCK3 SI0-SI3 SO0-SO3 TO110, TO111, TO120, TO121, TO130, TO131, TO140, TO141 TCLR11-TCLR14 TI11-TI14 TXD0, TXD1 UBEN WAIT X1, X2 V DD V PP V SS : Timer Clear : Timer Input : Transmit Data : Upper Byte Enable : Wait : Crystal : Power Supply : Programming Power Supply : Ground : Port4 : Port5 : Port6 : Port7 : Port9 : Port11 : Pulse Width Modulation : Reset : Read/Write Status : Receive Data : Serial Clock : Serial Input : Serial Output : Timer Output INTP110-INTP113, : Interrupt Request from Peripherals Data Sheet U13189EJ3V0DS00 3 µPD70F3003A, 70F3025A INTERNAL BLOCK DIAGRAM Flash memory NMI INTP110-INTP113 INTP120-INTP123 INTP130-INTP133 INTP140-INTP143 TO110, TO111 TO120, TO121 TO130, TO131 TO140, TO141 TCLR11-TCLR14 TI11-TI14 Note 2 SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 INTC Note 1 PC 32-bit barrel shifter System register CPU Instruction queue Multiplier 16 × 16 → 32 BCU ASTB DSTB R/W UBEN LBEN WAIT A16-A19 AD0-AD15 HLDRQ HLDAK RPU RAM Generalpurpose register 32 bits × 32 ALU BRG0 SO1/TXD1 SI1/RXD1 SCK1 CKSEL CLKOUT X1 X2 MODE RESET VDD VSS CVDD SO3 SI3 SCK3 PWM0, PWM1 CSI3 CVSS VPP UART1/CSI1 A/D Converter ANI0-ANI7 AVREF1 AVSS AVDD ADTRG D/A Converter ANO0, ANO1 AVREF2, AVREF3 Ports P110-P117 P90-P96 P70-P77 P60-P63 P50-P57 P40-P47 P30-P37 P20-P27 P10-P17 P00-P07 CG BRG1 SO2 SI2 SCK2 CSI2 BRG2 PWM Notes 1. µPD70F3003A : 128K bytes µPD70F3025A: 256K bytes 2. µPD70F3003A: 4K bytes µPD70F3025A: 8K bytes 4 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A CONTENTS 1. DIFFERENCES AMONG PRODUCTS ······························································································ 6 2. PIN FUNCTIONS ································································································································ 7 2.1 Port Pins ····················································································································································· 2.2 Pins Other Than Port Pins ························································································································ 7 9 2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins ················································ 11 3. ELECTRICAL SPECIFICATIONS ······································································································· 14 3.1 Normal Operation Mode ···························································································································· 14 3.2 Flash Memory Programming Mode ·········································································································· 35 4. PACKAGE DRAWING ······················································································································· 37 5. RECOMMENDED SOLDERING CONDITIONS ················································································· 38 Data Sheet U13189EJ3V0DS00 5 µPD70F3003A, 70F3025A 1. DIFFERENCES AMONG PRODUCTS Parameter Internal ROM µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A Mask ROM 128K bytes Flash memory 96K bytes 256K bytes 128K bytes 8K bytes 4K bytes 256K bytes 8K bytes Internal RAM Operation Normal mode operation mode Single chip mode ROM-less mode 4K bytes Provided Provided None None 00H None Provided Provided Provided None Flash memory programming mode VPP pin CKC register value at reset MODE = 0: 03H MODE = 1: 00H 00H MODE = 0: 03H MODE = 1: 00H Electrical specifications Others Current consumption, etc. differs. (Refer to each product data sheets.) Noise immunity and noise radiation differ because circuit scale and mask layout differ. 6 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A 2. PIN FUNCTIONS 2.1 Port Pins (1/2) Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40-P47 I/O Port 4 8-bit I/O port. Can be set in input or output mode in 1-bit units. P50-P57 I/O Port 5 8-bit I/O port. Can be set in input or output mode in 1-bit units. AD8-AD15 I/O Port 3 8-bit I/O port. Can be set in input or output mode in 1-bit units. I/O Port 2 8-bit I/O port. Can be set in input or output mode in 1-bit units. I/O Port 1 8-bit I/O port. Can be set in input or output mode in 1-bit units. I/O I/O Port 0 8-bit I/O port. Can be set in input or output mode in 1-bit units. Function Shared with: TO110 TO111 TCLR11 TI11 INTP110 INTP111 INTP112 INTP113/ADTRG TO120 TO121 TCLR12 TI12 INTP120 INTP121/SO2 INTP122/SI2 INTP123/SCK2 PWM0 PWM1 TXD0/SO0 RXD0/SI0 SCK0 TXD1/SO1 RXD1/SI1 SCK1 TO130 TO131 TCLR13 TI13 INTP130 INTP131/SO3 INTP132/SI3 INTP133/SCK3 AD0-AD7 Data Sheet U13189EJ3V0DS00 7 µPD70F3003A, 70F3025A (2/2) Pin Name P60-P63 I/O I/O Port 6 4-bit I/O port. Can be set in input or output mode in 1-bit units. P70-P77 Input Port 7 8-bit input port. P90 P91 P92 P93 P94 P95 P96 P110 P111 P112 P113 P114 P115 P116 P117 I/O Port 11 8-bit I/O port. Can be set in input or output mode in 1-bit units. I/O Port 9 7-bit I/O port. Can be set in input or output mode in 1-bit units. LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ TO140 TO141 TCLR14 TI14 INTP140 INTP141 INTP142 INTP143 ANI0-ANI7 Function Shared with: A16-A19 8 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A 2.2 Pins Other Than Port Pins (1/2) Pin Name TO110 TO111 TO120 TO121 TO130 TO131 TO140 TO141 TCLR11 TCLR12 TCLR13 TCLR14 TI11 TI12 TI13 TI14 INTP110 INTP111 INTP112 INTP113 INTP120 INTP121 INTP122 INTP123 INTP130 INTP131 INTP132 INTP133 INTP140 INTP141 INTP142 INTP143 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 Input Serial receive data output of CSI0-CSI3 (3 wire) Output Serial transmit data output of CSI0-CSI3 (3 wire) Input External maskable interrupt reuest input and external capture trigger input of timer 14 Input External maskable interrupt reuest input and external capture trigger input of timer 13 Input External maskable interrupt reuest input and external capture trigger input of timer 12 Input External maskable interrupt reuest input and external capture trigger input of timer 11 Input External count clock of timer 11-14 Input External clear signal of timer 11-14 I/O Output Function Pulse signal output of timer 11-14 Shared with: P00 P01 P10 P11 P30 P31 P110 P111 P02 P12 P32 P112 P03 P13 P33 P113 P04 P05 P06 P07/ADTRG P14 P15/SO2 P16/S12 P17/SCK2 P34 P35/SO3 P36/SI3 P37/SCK3 P114 P115 P116 P117 P22/TXD0 P25/TXD1 P15/INTP121 P35/INTP131 P23/RXD0 P26/RXD1 P16/INTP122 P36/INTP132 Data Sheet U13189EJ3V0DS00 9 µPD70F3003A, 70F3025A (2/2) Pin Name SCK0 SCK1 SCK2 SCK3 TXD0 TXD1 RXD0 RXD1 PWM0 PWM1 AD0-AD7 AD8-AD15 A16-A19 LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ ANI0-ANI7 ANO0, ANO1 NMI CLKOUT CKSEL WAIT MODE RESET X1 X2 ADTRG AVREF1 AVREF2 AVREF3 AVDD AVSS CVDD CVSS VDD VSS VPP — — — — — — — Positive power supply for A/D converter Ground potential for A/D converter Positive power supply for internal clock generator Ground potential for internal clock generator Positive power supply Ground potential High voltage application pin when program is written/verified Output Input Input Output Input Output Input Input Input Input Input — Input Input Input Output Output Output High-order address bus when external memory is connected Low-order byte enable signal output of external data bus High-order byte enable signal output of external data bus External read/write status output External data strobe signal output External address strobe signal output Bus hold acknowledge output Bus hold request input Analog input to A/D converter Analog output of D/A converter Non-maskable interrupt request input System clock output Input specifying operation mode of clock generator Control signal input inserting wait state in bus cycle Operation mode specification System reset input System clock resonator connection. Input external clock to X1 to supply external clock. A/D converter external trigger input Reference voltage input for A/D converter Reference voltage input for D/A converter CVDD — — — — — P07/INTP113 — — — — — CKSEL — — — — I/O 16-bit multiplexed address/data bus when external memory is connected Output Pulse signal output of PWM Input Serial receive data input of UART0-UART1 Output Serial transmit data output of UART0-UART1 I/O I/O Function Serial clock I/O of CSI0-CSI3 (3 wire) Shared with: P24 P27 P17/INTP123 P37/INTP133 P22/SO0 P25/SO1 P23/SI0 P26/SI1 P20 P21 P40-P47 P50-P57 P60-P63 P90 P91 P92 P93 P94 P95 P96 P70-P77 — — — 10 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A 2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins Table 2-1 shows the I/O circuit type of each pin, and the recommended connections of the unused pins. Figure 2-1 shows a partially simplified diagram of each circuit. When connecting a pin to VDD o r V SS v ia resistor, use of a resistor of 1 to 10 kΩ i s recommended. Table 2-1. I/O Circuit Types of Each Pin and Recommended Connections of Unused Pins (1/2) Pin P00/TO110, P01/TO111 P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113/ADTRG P10-TO120, P11/TO121 P12/TCLR12, P13/TI12 P14/INTP120 P15/INTP121/SO2 P16/INTP122/SI2 P17/INTP123/SCK2 P20/PWM0, P21/PWM1 P22/TXD0/SO0 P23/RXD0/SI0, P24/SCK0 P25/TXD1/SO1 P26/RXD1/SI1, P27/SCK1 P30/TO130, P31/TO131 P32/TCLR13, P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P40/AD0-P47/AD7 P50/AD8-P57/AD15 P60/A16-P63/A19 P70/ANI0-P77/ANI7 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ P110/TO140, P111/TO141 P112/TCLR14, P113/TI14 P114/INTP140-P117/INTP143 8 9 5 Directly connect to VSS. Input: Individually connect to VDD or VSS via resistor. Output: Leave unconnected. 5 10-A 8 5 8 5 8 5 5 8 I/O Circuit Type 5 8 Input Recommended Connections : Individually connect to VDD or VSS via resistor. Output : Leave unconnected. Data Sheet U13189EJ3V0DS00 11 µPD70F3003A, 70F3025A Table 2-1. I/O Circuit Types of Each Pin and Recommended Connections of Unused Pins (2/2) Pin ANO0, ANO1 NMI CLKOUT WAIT MODE RESET CVDD/CKSEL AVREF1-AVREF3, AVSS AVDD VPP — — — Directly connect to VSS. Directly connect to VDD. Connect to VSS. — I/O Circuit Type 12 2 3 1 2 Recommended Connections Leave unconnected. Directly connect to VSS. Leave unconnected. Directly connect to VDD. — 12 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A Figure 2-1. I/O Circuits of Pins Type 1 Type 8 VDD Data P-ch IN/OUT Output disable N-ch VDD P-ch IN N-ch Type 2 Type 9 P-ch IN N-ch IN + – Comparator VREF (Threshold voltage) Input enable Schmitt trigger input with hysteresis characteristics Type 3 Type 10-A VDD VDD P-ch OUT Pullup enable Data P-ch VDD P-ch IN/OUT N-ch Open drain Output disable N-ch Type 5 VDD Data P-ch IN/OUT Type 12 Analog output voltage Output disable N-ch P-ch N-ch OUT Input enable Data Sheet U13189EJ3V0DS00 13 µPD70F3003A, 70F3025A 3. ELECTRICAL SPECIFICATIONS 3.1 Normal Operation Mode Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol VDD CVDD CVSS AVDD AVSS Input voltage VI1 VI2 VDD pin CVDD pin CVSS pin AVDD pin AVSS pin Note, VDD = 5.0 V ± 10% VPP pin in flash memory programming mode, VDD = 5.0 V ± 10% Clock input voltage Output current, low VK ICL X1 pin, VDD = 5.0 V ± 10% 1 pin Total of all pins Output current, high ICH 1 pin Total of all pins Output voltage Analog input voltage VO VIAN VDD = 5.0 V ± 10% P70/ANI0-P77/ANI7 AVDD > VDD VDD ≥ AVDD Analog reference input voltage AVREF AVREF1-AVREF3 AVDD > VDD VDD ≥ AVDD Operating ambient temperature Storage temperature TA Tstg –0.5 to VDD + 1.0 4.0 100 –4.0 –100 –0.5 to VDD + 0.3 –0.5 to VDD + 0.3 –0.5 to AVDD + 0.3 –0.5 to VDD + 0.3 –0.5 to AVDD + 0.3 –40 to +85 –65 to +125 V mA mA mA mA V V V V V °C °C Condition Ratings –0.5 to +7.0 –0.5 to VDD + 0.3 –0.5 to +0.5 –0.5 to VDD + 0.3 –0.5 to +0.5 –0.5 to VDD + 0.3 –0.5 to +11.0 Unit V V V V V V V Note Except X1, P70/AN0-P77/AN7, AVREF1-AVREF3 Cautions 1. Do not directly connect the output (or I/O) pins of two or more IC products, and do not directly connect them to VDD, VCC, or GND pin. Open-drain pins and open-collector pins may be directly connected to one another however. Moreover, an external circuit that is designed to prevent contention of output can be connected to pins that go into a high-impedance state. 2. Should the absolute maximum rating of even one of the above parameters be exceeded even momentarily, the quality of the program may be degraded. The absolute maximum ratings are, therefore, the values exceeding which the product may be physically damaged. Use the product so that these values are never exceeded. The normal operating ranges of ratings and conditions in which the quality of the product is guaranteed are specified in the following DC Characteristics and AC Characteristics. 14 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO fc = 1 MHz Pins other than tested pin: 0 V Condition MIN. TYP. MAX. 15 15 15 Unit pF pF pF Operating Conditions Operation Mode Direct mode, PLL mode Internal Operating Clock Frequency (φ) 2 to 33 MHz 5 to 33 MHz Note 1 Note 2 Operating Temperature (TA) –40 to +85°C –40 to +85°C Supply Voltage (VDD) 5.0 V ± 10% 5.0 V ± 10% Notes 1. When A/D converter not used. 2. When A/D converter used. DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ± 10%, VSS = 0 V) (1/2) Parameter Input voltage, high Symbol VIH Condition Except X1 and Note 1 Note 1 Input voltage, low VIL Except X1 and Note 1 Note 1 Clock input voltage, high Clock input voltage, low Schmitt trigger input threshold voltage VXH VXL VT VT Schmitt trigger input hysteresis width Output voltage, high + – + – MIN. 2.2 0.8 VDD –0.5 –0.5 0.8 VDD –0.5 TYP. MAX. VDD + 0.3 VDD + 0.3 +0.8 0.2 VDD VDD + 0.5 0.6 Unit V V V V V V V V V V V X1 X1 Note 1, rising Note 1, falling Note 1 IOH = –2.5 mA IOH = –100 µA 3.0 2.0 0.5 0.7 VDD VDD – 0.4 0.45 10 –10 10 –10 15 40 90 VT – VT VOH Output voltage, low Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Software pull-up resistor VOL ILIH ILIL ILOH ILOL R IOC = 2.5 mA VI = VDD VI = 0 V VO = VDD VO = 0 V P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3 V µA µA µA µA kΩ Data Sheet U13189EJ3V0DS00 15 µPD70F3003A, 70F3025A (2/2) Parameter Supply µPD70F3003A Operating current In HALT mode IDD2 Symbol IDD1 Condition Direct mode PLL mode Note 2 MIN. TYP. 2.2 × φ + 7.5 2.3 × φ + 9.5 1.2 × φ + 7.5 1.3 × φ + 9.5 8 × φ + 300 0.1 × φ + 2 2 2 30 30 2.5 × φ + 8 MAX. 2.5 × φ + 22 2.6 × φ + 25 1.3 × φ + 15 1.4 × φ + 17 10 × φ + 500 0.2 × φ + 3 50 200 200 500 2.8 × φ + 22.5 Unit mA mA mA mA Note 2 Note 2 Direct mode PLL mode Note 2 Note 2 In IDLE mode IDD3 Direct mode PLL mode µA mA Note 2 In STOP mode IDD4 CESEL = 0, Note 3 CESEL = 0, Note 4 CESEL = 1, Note 3 CESEL = 1, Note 4 µA µA µA µA mA mA mA mA µPD70F3025A Operating IDD1 Direct modeNote 2 PLL modeNote 2 2.6 × φ + 10 2.9 × φ + 25.5 1.3 × φ + 7.5 1.4 × φ + 15 In HALT mode IDD2 Direct modeNote 2 PLL modeNote 2 1.3 × φ + 12.5 1.4 × φ + 20 8 × φ + 300 0.1 × φ + 2 2 2 60 60 10 × φ + 500 0.2 × φ + 3 50 200 300 500 In IDLE mode IDD3 Direct modeNote 2 PLL modeNote 2 µA mA In STOP mode IDD4 CESEL = 0, Note 3 CESEL = 0, Note 4 CESEL = 1, Note 3 CESEL = 1, Note 4 µA µA µA µA Notes 1. P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/ SCK3, P112/TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE 2. When A/D converter used 3. –40°C ≤ TA ≤ +50°C 4. 50°C < TA ≤ 85°C Remarks 1. TYP. value is a value for your reference at TA = 25°C and VDD = 5.0 V. The supply current does not include AVREF1-AVREF3 and the current running through the software pull-up resistor. 2. φ : Internal system clock frequency : φ = 5 to 33 MHz When A/D converter not used : φ = 2 to 33 MHz 16 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A Data Retention Characteristics (TA = –40 to +85°C) Parameter Data hold voltage Data hold current Symbol VDDDR IDDDR STOP mode VDD = VDDDR –40°C ≤ TA ≤ +50°C 50°C < TA ≤ 85°C Supply voltage rise time Supply voltage fall time Supply voltage hold time (vs. STOP mode setting) STOP mode release signal input time Data hold input voltage, high Data hold input voltage, low tRVD tFVD tHVD 200 200 0 Condition MIN. 1.5 0.2 VDDDR 0.2 VDDDR TYP. MAX. 5.5 50 200 Unit V µA µA µs µs ms tDREL VIHDR VILDR Note Note 0 0.9 VDDDR 0 VDDDR 0.1 VDDDR ns V V Note P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/ TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1 Remark TYP. value is a value for your reference at TA = 25°C and VDD = 5.0 V. STOP mode is set (at fifth clock after PSC register has been set). VDD VDD tHVD tFVD VDDDR tRVD tDREL VDD RESET (input) VIHDR NMI (input) (Release by falling edge) VIHDR NMI (input) (Release by rising edge) VILDR Data Sheet U13189EJ3V0DS00 17 µPD70F3003A, 70F3025A AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ± 10%, VSS = 0 V) AC test input wave (a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112,TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1 VDD 0.8 VDD Test point 0.2 VDD 0.8 VDD 0.2 VDD 0V (b) Other than (a) 2.4 V 2.2 V Test point 0.8 V 2.2 V 0.8 V 0.4 V AC test output test point 2.2 V Test point 0.8 V 2.2 V 0.8 V Load condition DUT (tested device) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, decrease the load capacitance of this device to less then 50 pF by using a buffer. 18 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A (1) Clock timing Parameter Symbol Condition 25 MHz Model MIN. X1 input cycle tCYX Direct mode PLL mode (PLL lock status) X1 input width, high tWXH Direct mode PLL mode X1 input width, low tWXL Direct mode PLL mode X1 input rise time tXR Direct mode PLL mode X1 input fall time tXF Direct mode PLL mode CPU operating frequency CLKOUT output cycle CLKOUT width, high CLKOUT width, low CLKOUT rise time CLKOUT fall time X1 ↓→ CLKOUT delay time — 20 200 MAX. Note 1 Note 1 33 MHz Model MIN. 15 151 MAX. Note 1 Note 1 ns ns Unit 7 80 7 80 7 15 7 15 Note 2 40 0.5 T – 5 0.5 T – 5 5 5 25 Note 3 6 60 6 60 7 10 7 10 Note 2 30 0.5 T – 5 0.5 T – 5 5 5 3 17 33 Note 3 ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns φ tCYK tWKH tWKL tXR tXF tDXK Direct mode 3 17 Notes 1. When A/D converter used: 100 ns When A/D converter not used: 250 ns 2. When A/D converter used: 5 MHz When A/D converter not used: 2 MHz 3. When A/D converter used: 200 ns When A/D converter not used: 500 ns Remark T = tCYK X1 (input) CLKOUT (output) Data Sheet U13189EJ3V0DS00 19 µPD70F3003A, 70F3025A (2) Input wave (a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE Parameter Symbol Condition 25 MHz Model MIN. Input rise time Input fall time tIR2 tIF2 MAX. 20 20 33 MHz Model MIN. MAX. 20 20 ns ns Unit VDD Input signal 0V 0.8 VDD 0.2 VDD < 13 > 0.8 VDD 0.2 VDD < 12 > (b) Other than (a) Parameter Symbol Condition 25 MHz Model MIN. Input rise time Input fall time tIR1 tIF1 MAX. 10 10 33 MHz Model MIN. MAX. 10 10 ns ns Unit 2.4 V Input signal 0.4 V 2.2 V 0.8 V < 15 > 2.2 V 0.8 V < 14 > 20 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A (3) Output wave (other than CLKOUT) Parameter Symbol Condition 25 MHz Model MIN. Output rise time Output fall time tOR tOF MAX. 10 10 33 MHz Model MIN. MAX. 10 10 ns ns Unit 2.2 V Output signal 0.8 V < 16 > 2.2 V 0.8 V < 17 > (4) Reset timing Parameter Symbol Condition 25 MHz Model MIN. RESET width, high RESET width, low tWRSH tWRSL On power application, or on releasing STOP mode Except on power application, or except on releasing STOP mode 500 500 + TOST MAX. 33 MHz Model MIN. 500 500 + TOST MAX. ns ns Unit 500 500 ns Remark TOST: oscillation stabilization time < 18 > < 19 > RESET (input) Data Sheet U13189EJ3V0DS00 21 µPD70F3003A, 70F3025A (5) Read timing (1/2) Parameter Symbol Condition 25 MHz Model MIN. CLKOUT ↑→ address delay time CLKOUT ↑→ address float delay time CLKOUT ↓→ ASTB delay time CLKOUT ↓→ DSTB delay time Data input hold time (vs. CLKOUT ↑) WAIT setup time (vs. CLKOUT ↓) WAIT hold time (vs. CLKOUT ↓) Address setup time (vs. ASTB ↓) Address hold time (vs. ASTB ↓) tDKA tDKA2 tFKA tDKST tDKD tSIDK tHKID tSWTK tHKWT tHKA tSAST 70°C < TA ≤ 85°C tHSTA tFDA tSAID –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C Data input setup time (vs. DSTB ↓) ASTB ↓→ DSTB ↓ delay time Data input hold time (vs. DSTB ↑) DSTB ↑→ address output delay time DSTB ↑→ ASTB ↑ delay time DSTB ↑→ ASTB ↓ delay time DSTB width, low tSDID –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C tDSTD tHDID tDDA tDDSTH tDDSTL tWDL 70°C < TA ≤ 85°C ASTB width, high WAIT setup time (vs. address) tWSTH tSAWT1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C tSAWT2 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C WAIT hold time (vs. address) WAIT setup time (vs. ASTB ↓) tHAWT1 tHAWT2 tSSTWT1 n≥1 n≥1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C WAIT hold time (vs. ASTB ↓) tSSTWT2 tHSTWT1 tHSTWT2 n≥1 n≥1 n≥1 nT (1 + n) T (0.5 + n) T (1.5 + n) T T – 18 T – 20 (1 + n) T – 15 nT (1 + n) T 0.5 T – 10 0 (1 + i) T 0.5 T – 10 (1.5 + i) T – 10 –40°C ≤ TA ≤ +70°C (1 + n) T – 10 (1 + n) T – 13 T – 10 1.5 T – 20 1.5 T – 24 (1.5 + n) T – 20 (1.5 + n) T – 24 (0.5 + n) T (1.5 + n) T T – 18 T – 20 (1 + n) T – 15 DSTB ↓→ address float delay time Data input setup time (vs. address) 3 –2 3 3 3 5 5 5 5 0 –40°C ≤ TA ≤ +70°C 0.5 T – 10 0.5 T – 12 0.5 T – 10 0 (2 + n) T – 22 (2 + n) T – 25 (1 + n) T – 20 (1 + n) T – 24 0.5 T – 10 0 (1 + i) T 0.5 T – 10 (1.5 + i) T – 10 (1 + n) T – 10 (1 + n) T – 13 T – 10 1.5 T – 20 1.5 T – 24 (1.5 + n) T – 20 (1.5 + n) T – 24 MAX. 20 +13 15 15 15 33 MHz Model MIN. 3 –2 3 3 3 5 5 5 5 0 0.5 T – 10 0.5 T – 12 0.5 T – 10 0 (2 + n) T – 22 (2 + n) T – 25 (1 + n) T – 20 (1 + n) T – 24 MAX. 20 +13 15 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit CLKOUT ↑→ R/W, UBEN, LBEN delay time Data input setup time (vs. CLKOUT ↑) Address hold time (vs. CLKOUT ↑) Remarks 1. T = tCYK 2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when the programmable wait state is inserted. 3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle. 4. Be sure to observe at least one of data input hold times tHKID () and tHDID (). 22 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A (5) Read Timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) < 20 > < 28 > A16-A19 (output) < 78 > R/W (output) UBEN (output) LBEN (output) < 32 > < 21 > < 24 > < 25 > AD0-AD15 (I/O) A0-A15 (output) < 22 > < 29 > < 30 > D0-D15 (input) < 35 > < 22 > ASTB (output) < 37 > < 33 > < 23 > < 36 > < 40> < 23 >< 31 > < 34 > DSTB (output) < 38 > < 39 > < 45 > < 26 > < 47 > < 46 > < 27 > < 26 > < 27 > < 48 > WAIT (input) < 41 > < 43 > < 42 > < 44 > Remark The broken line indicates the high-impedance state. Data Sheet U13189EJ3V0DS00 23 µPD70F3003A, 70F3025A (6) Write timing (1/2) Parameter Symbol Condition 25 MHz Model MIN. CLKOUT ↑→ address delay time CLKOUT ↓→ ASTB delay time CLKOUT ↑→ DSTB delay time WAIT setup time (vs. CLKOUT ↓) WAIT hold time (vs. CLKOUT ↓) Address setup time (vs. ASTB ↓) Address hold time (vs. ASTB ↓) ASTB ↓→ DSTB ↓ delay time DSTB ↑→ ASTB ↑ delay time DSTB width, low tDKA tDKA2 tDKST tDKD tSWTK tHKWT tHKA tSAST 70°C < TA ≤ 85°C tHSTA tDSTD tDDSTH tWDL 70°C < TA ≤ 85°C ASTB width, high WAIT setup time (vs. address) tWSTH tSAWT1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C tSAWT2 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C WAIT hold time (vs. address) WAIT setup time (vs. ASTB ↓) tHAWT1 tHAWT2 tSSTWT1 n≥1 n≥1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C WAIT hold time (vs. ASTB ↓) CLKOUT ↑→ data output delay time DSTB ↓→ data output delay time Data output setup time (vs. DSTB ↑) tSSTWT2 tHSTWT1 tHSTWT2 tDKOD n≥1 n≥1 n≥1 –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C tDDOD tHKOD tSODD tHDOD 0 (1 + n) T – 15 T – 10 Data output hold time (vs. CLKOUT ↑) Data output hold time (vs. DSTB ↑) nT (1 + n) T 20 23 10 0 (1 + n) T – 15 T – 10 (0.5 + n) T (1.5 + n) T T – 18 T – 20 (1 + n) T – 15 nT (1 + n) T 20 23 10 3 –2 3 3 5 5 0 –40°C ≤ TA ≤ +70°C 0.5 T – 10 0.5 T – 12 0.5 T – 10 0.5 T – 10 0.5 T – 10 –40°C ≤ TA ≤ +70°C (1 + n) T – 10 (1 + n) T – 13 T – 10 1.5 T – 20 1.5 T – 24 (1.5 + n) T – 20 (1.5 + n) T – 24 (0.5 + n) T (1.5 + n) T T – 18 T – 20 (1 + n) T – 15 MAX. 20 +13 15 15 33 MHz Model MIN. 3 –2 3 3 5 5 0 0.5 T – 10 0.5 T – 12 0.5 T – 10 0.5 T – 10 0.5 T – 10 (1 + n) T – 10 (1 + n) T – 13 T – 10 1.5 T – 20 1.5 T – 24 (1.5 + n) T – 20 (1.5 + n) T – 24 MAX. 20 +13 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit CLKOUT ↑→ R/W, UBEN, LBEN delay time Address hold time (vs. CLKOUT ↑) Remarks 1. T = tCYK 2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when the programmable wait state is inserted. 24 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A (6) Write timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) < 20 > < 28 > A16-A19 (output) < 78 > R/W (output) UBEN (output) LBEN (output) < 49 > < 51 > AD0-AD15 (I/O) A0-A15 (output) < 22 > < 29 > < 30 > D0-D15 (output) < 22 > ASTB (output) < 23 > < 34 > < 50 > < 52 > < 23 > < 37 > < 53 > < 40 > DSTB (output) < 39 > < 45 > < 26 > < 47 > < 46 > < 27 > < 26 > < 27 > < 48 > WAIT (input) < 41 > < 43 > < 42 > < 44 > Remark The broken line indicates the high-impedance state. Data Sheet U13189EJ3V0DS00 25 µPD70F3003A, 70F3025A (7) Bus hold timing (1/2) Parameter Symbol Condition 25 MHz Model MIN. HLDRQ setup time (vs. CLKOUT ↓) tSHOK tHKHQ tDKHA tWHQH tWHAL –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C CLKOUT↑ → Bus float delay time HLDAK ↑→ bus output delay time HLDRQ ↓→ HLDAK ↓ delay time HLDRQ ↑→ HLDAK ↑ delay time tDKF tDHAC tDHQHA1 tDHQHA2 0.5 T –3 (2 n + 7.5) T + 20 33 MHz Model MIN. 5 5 MAX. Unit MAX. 5 5 20 T + 10 T – 10 T – 12 20 ns ns 20 ns ns ns ns 20 ns ns (2 n + 7.5) T + 20 HLDRQ hold time (vs. CLKOUT ↓) CLKOUT ↑→ HLDAK delay time HLDRQ width, high HLDAK width, low T + 10 T – 10 T – 12 –3 ns ns 1.5 T + 20 0.5 T 1.5 T + 20 Remarks 1. T = tCYK 2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when the programmable wait state is inserted. 26 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A (7) Bus hold timing (2/2) TH TH TH TH TI CLKOUT (output) < 54 > < 54 > < 55 > < 57 > HLDRQ (input) < 56 > < 61 > < 62 > < 56 > HLDAK (output) < 58 > < 60 > < 59 > A16-A19 (output) Note AD0-AD15 (I/O) D0-D15 (input or output) ASTB (output) DSTB (output) R/W (output) Note UBEN (output), LBEN (output) Remark The broken line indicates the high-impedance state. Data Sheet U13189EJ3V0DS00 27 µPD70F3003A, 70F3025A (8) Interrupt timing Parameter Symbol Condition 25 MHz Model MIN. NMI width, high NMI width, low INTPn width, high tWNIH tWNIL tWITH n = 110-113, 120-123, 130-133, 140-143 n = 110-113, 120-123, 130-133, 140-143 500 500 3 T + 10 MAX. 33 MHz Model MIN. 500 500 3 T + 10 MAX. ns ns ns Unit INTPn width, low tWITL 3 T + 10 3 T + 10 ns Remark T = tCYK < 63 > < 64 > NMI (input) < 65 > < 66> INTPn (input) Remark n = 110-113, 120-123, 130-133, 140-143 28 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A [MEMO] Data Sheet U13189EJ3V0DS00 29 µPD70F3003A, 70F3025A (9) CSI timing (1/2) (a) Master mode (i) CSI0-CSI2 timing Parameter Symbol Condition 25 MHz Model MIN. SCKn cycle SCKn width, high SCKn width, low SIn setup time (vs. SCKn ↑) SIn hold time (vs. SCKn ↑) SOn output delay time (vs. SCKn ↓) tCYSK1 tWSKH1 tWSKL1 tSSISK1 tHSKSI1 tDSKSO1 tHSKSO1 0.5 tCYSK1 – 5 Output Output Output 160 0.5 tCYSK1 – 20 0.5 tCYSK1 – 20 30 0 18 0.5 tCYSK1 – 5 MAX. 33 MHz Model MIN. 120 0.5 tCYSK1 – 20 0.5 tCYSK1 – 20 30 0 18 MAX. ns ns ns ns ns ns ns Unit SOn output hold time (vs. SCKn ↑) Remark n = 0 -2 (ii) CSI3 timing Parameter Symbol Condition 25 MHz Model MIN. SCK3 cycle SCK3 width, high SCK3 width, low SI3 setup time (vs. SCK3 ↑) SI3 hold time (vs. SCK3 ↑) SO3 output delay time (vs. SCK3 ↓) tCYSK3 tWSKH3 tWSKL3 tSSISK3 tHSKSI3 tDSKSO3 RL = 1.5 KΩ CL = 50 pF 0.5 tCYSK3 – 5 Output Output Output RL = 1.5 500 kΩ 0.5 tCYSK3 – 70 CL = 50 0.5 tCYSK3 – 70 pF 100 50 150 MAX. 33 MHz Model MIN. 500 0.5 tCYSK3 – 70 0.5 tCYSK3 – 70 100 50 150 MAX. ns ns ns ns ns ns Unit SO3 output hold time (vs. SCK3 ↑) tHSKSO3 0.5 tCYSK3 – 5 ns Remark R L a nd C L a re the load resistance and load capacitance respectively of the SCK3 and SO3 output lines. (b) Slave mode (i) CSI0-CSI2 timing Parameter Symbol Condition 25 MHz Model MIN. SCKn cycle SCKn width, high SCKn width, low SIn setup time (vs. SCKn ↑) SIn hold time (vs. SCKn ↑) SOn output delay time (vs. SCKn ↓) tCYSK2 tWSKH2 tWSKL2 tSSISK2 tHSKSI2 tDSKSO2 tHSKSO2 tWSKH2 Input Input Input 160 50 50 10 10 30 tWSKH2 MAX. 33 MHz Model MIN. 120 30 30 10 10 30 MAX. ns ns ns ns ns ns ns Unit SOn output hold time (vs. SCKn ↑) Remark n = 0 -2 30 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A (9) CSI timing (2/2) (ii) CSI3 timing Parameter Symbol Condition 25 MHz Model MIN. SCK3 cycle SCK3 width, high SCK3 width, low SI3 setup time (vs. SCK3 ↑) SI3 hold time (vs. SCK3 ↑) SO3 output delay time (vs. SCK3 ↓) tCYSK4 tWSKH4 tWSKL4 tSSISK4 tHSKSI4 tDSKSO4 tHSKSO4 RL = 1.5 kΩ CL = 50 pF tWSKH4 Input Input Input 500 180 180 100 50 150 tWSKH4 MAX. 33 MHz Model MIN. 500 180 180 100 50 150 MAX. ns ns ns ns ns ns ns Unit SO3 output hold time (vs. SCK3 ↑) Remark R L a nd C L a re the load resistance and load capacitance respectively of the SCK3 and SO3 output lines. < 67 > < 69 > < 68 > SCKn (I/O) < 70 > < 71 > SIn (input) Input data < 72 > < 73 > SOn (output) Output data Remark 1. The broken line indicates the high-impedance state. 2. n = 0-3 Data Sheet U13189EJ3V0DS00 31 µPD70F3003A, 70F3025A (10) RPU timing Parameter Symbol Condition 25 MHz Model MIN. TI1n width, high TI1n width, low TCLR1n width, high TCLR1n width, low tWTIH tWTIL tWTCH tWTCL 3 T + 10 3 T + 10 3 T + 10 3 T + 10 MAX. 33 MHz Model MIN. 3 T + 10 3 T + 10 3 T + 10 3 T + 10 MAX. ns ns ns ns Unit Remark T = tCYK TI1n (input) TCLR1n (input) Remark n = 1-4 32 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = VSS = 0 V) Parameter Symbol Conditions 25 MHz Model MIN. Resolution Overall error Note 1 33 MHz Model MIN. 10 TYP. 10 MAX. 10 ± 0.4 ± 0.7 ± 1/2 60 60 10 10 Unit TYP. 10 MAX. 10 ± 0.4 ± 0.7 ± 1/2 — — — 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD 10 bit %FSR %FSR LSB tCYK tCYK tCYK tCYK Quantize error Conversion time — tCONV 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD 48 48 8 8 ± 1.5 ± 1.5 ± 1.5 ± 1.5 ± 1.5 ± 1.5 –0.3 Sampling time tSAMP 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD Zero-scale error Note 1 — — 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD ± 3.5 ± 4.5 ± 2.5 ± 4.5 ± 2.5 ± 4.5 AVDD +0.3 AVDD –0.3 ± 1.5 ± 1.5 ± 1.5 ± 1.5 ± 1.5 ± 1.5 ± 3.5 ± 4.5 ± 2.5 ± 4.5 ± 2.5 ± 4.5 AVDD +0.3 AVDD LSB LSB LSB LSB LSB LSB V Full-scale error Note 1 — — Non-linear error Note 1 — — Analog input voltageNote 2 Reference voltage AVREF1 current AVDD supply current VIAN AVREF1 AIREF1 AIDD 3.5 1.2 2.3 3.5 1.2 2.3 V mA mA 3.0 6.0 3.0 6.0 Notes 1. Except quantize error 2. The conversion result is 000H when VIAN = 0. Converted with 10-bit resolution when 0 < VIAN < AVREF1. The conversion result is 3FFH when AVREF1 ≤ VIAN ≤ AVDD. Data Sheet U13189EJ3V0DS00 33 µPD70F3003A, 70F3025A D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V) Parameter Symbol Conditions 25 MHz Model MIN. Resolution Overall error — — Load conditions: 2 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 Load conditions: 2 MΩ, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD Load conditions: 4 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 Load conditions: 4 MΩ, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD Load conditions: 2 MΩ, 30 pF 8 0.75 VDD 0 DACS0, DACS1 = 55H 2 4 VDD 0.25 VDD 0.75 VDD 0 2 4 8 TYP. 8 MAX. 8 0.8 33 MHz Model MIN. 8 TYP. 8 MAX. 8 0.8 bit % Unit — 1.0 1.0 % — 0.6 0.6 % — 0.8 0.8 % Settling time Output resistance AVREF2 input voltage AVREF3 input voltage AVREF2-AVREF3 resistance value — RO AVREF2 AVREF3 RAIREF 10 8 10 µs kΩ VDD 0.25 VDD V V kΩ 34 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A 3.2 Flash Memory Programming Mode Basic Characteristics (TA = 10 to 40°C (when rewrifing), TA = –40 to +85°C (when not rewriting)) Parameter Operating frequency Supply voltage Symbol fX VDD VPPL VPPM VPPH VDD supply current VPP supply current Number of rewriteNote IDO IPP CWRT VPP = 10.3 V 20 VPP low level detection VPP, VDD level detection VPP high voltage detection Conditions MIN. 10 4.5 –0.5 0.8 VDD 9.7 10.3 TYP. MAX. 33 5.5 0.2 VDD 1.2 VDD 10.6 3.0 × φ + 25 200 Unit MHz V V V V mA mA times Note Operation is not guaranteed when rewrite is performed more than 20 times. Cautions 1. VPP pull-down resistance value (RVPP) is recommended to be in the range 5 kΩ to 15 kΩ. 2. Set the transfer rate between programmer and device as follows. CSI0 : 0.2 to 1 MHz UART0: 4800 to 76800 bps Remark φ: Internal system clock frequency Data Sheet U13189EJ3V0DS00 35 µPD70F3003A, 70F3025A Serial Write Operation Characteristics Parameter VDD ↑→ RESET ↑ setup time VPP ↑→ RESET ↑ setup time RESET ↑→ VPP count start time Count end time VPP counter width, high VPP counter width, low Symbol tDRRR tPSRR tRRCF tCOUNT tCH tCL 1.0 1.0 Conditions MIN. 10 1.0 5T + 500 10 TYP. MAX. Unit ms µs ns ms µs µs Remark T = t CYK VDD VDD 0V VPPH VPP VPPM VPPL VDD RESET (input) 0V 36 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A 4. PACKAGE DRAWING 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S CD Q R 100 1 26 25 F G P H I M J K S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.00 ± 0.20 14.00 ± 0.20 14.00 ± 0.20 16.00 ± 0.20 1.00 1.00 0.22 + 0.05 − 0.04 0.08 0.50 (T.P.) 1.00 ± 0.20 0.50 ± 0.20 0.17 + 0.03 − 0.07 0.08 1.40 ± 0.05 0.10 ± 0.05 3°+7° −3° 1.60 MAX. S100GC-50-8EU, 8EA-2 Data Sheet U13189EJ3V0DS00 37 µPD70F3003A, 70F3025A 5. RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document S emiconductor Device Mounting Technology Manual (C10535E) . For soldering methods and conditions other than those recommended, consult NEC. Table 5-1. Soldering Conditions µ PD70F3003AGC-25-8EU : 100-pin plastic LQFP (fine pitch) (14 × 1 4 mm) µ PD70F3003AGC-33-8EU : 100-pin plastic LQFP (fine pitch) (14 × 1 4 mm) µ PD70F3025AGC-25-8EU : 100-pin plastic LQFP (fine pitch) (14 × 1 4 mm) µ PD70F3025AGC-33-8EU : 100-pin plastic LQFP (fine pitch) (14 × 1 4 mm) Soldering Method Soldering Condition Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Number of times: 3 max., Number of days: 3Note (after that, prebaking is necessary at 125°C for 10 hours.) Package peak temperature: 215°C, Time: 40 seconds max. (200°C min.), Number of times: 3 max., Number of days: 3Note (after that, prebaking is necessary at 125°C for 10 hours.) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) — Symbol of Recommended Soldering Condition IR35-103-3 Infrared reflow VPS VP15-103-3 Note The number of days for storage at 25°C, 65% RH MAX after the dry pack has been opened. Do not use two or more soldering methods in combination (except partial heating method). Caution 38 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A [MEMO] Data Sheet U13189EJ3V0DS00 39 µPD70F3003A, 70F3025A [MEMO] 40 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A [MEMO] Data Sheet U13189EJ3V0DS00 41 µPD70F3003A, 70F3025A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Related document : µ PD703003 Data Sheet (U12261E) µ PD703003A, 703004A, 703025A Data Sheet (U13188E) µ PD70F3003 Data Sheet (U12036E) Reference document : Concept of Electrical Characteristics - Microcomputers (IEI-601) (Japanese version) The related documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. V850 Family and V853 are trademarks of NEC Corporation. 42 Data Sheet U13189EJ3V0DS00 µPD70F3003A, 70F3025A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U13189EJ3V0DS00 43 µPD70F3003A, 70F3025A [MEMO] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8