UPD720100A

DATA SHEET MOS INTEGRATED CIRCUIT µPD720100A USB2.0 HOST CONTROLLER The µPD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The µPD720100A is integrated three host controller cores with PCI interface and USB2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. µPD720100A User’s Manual: S15534E FEATURES • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) • Compliant with Open Host Controller Interface Specification for USB Rev 1.0a • Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95 • PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling. • Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core • All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. • Configurable number of downstream facing ports (2 to 5) • 32-bit 33 MHz host interface compliant to PCI Specification release 2.2. • Supports PCI Mobile Design Guide Revision 1.1. • Supports PCI-Bus Power Management Interface Specification release 1.1. • PCI Bus bus-master access • System clock is generated by 30 MHz X’tal or 48 MHz clock input. • Operational registers direct-mapped to PCI memory space • Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation. • 3.3 V power supply, PCI signal pins have 5 V tolerant circuit. ORDERING INFORMATION Part Number Package 160-pin plastic LQFP (Fine pitch) (24 × 24) 160-pin plastic LQFP (Fine pitch) (24 × 24) 176-pin plastic FBGA (15 × 15) µPD720100AGM-8ED µPD720100AGM-8EY µPD720100AS1-2C The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15535EJ2V0DS00 (2nd edition) Date Published October 2002 NS CP (K) Printed in Japan The mark shows major revised points. © 2001 µPD720100A BLOCK DIAGRAM PCI Bus PME0 INTA0 INTB0 INTC0 PCI Bus Interface WakeUp_Event WakeUp_Event WakeUp_Event Arbiter OHCI Host Controller #1 OHCI Host Controller #2 EHCI Host Controller SMI0 Root Hub PHY Port 1 Port 2 Port 3 Port 4 Port 5 USB Bus 2 Data Sheet S15535EJ2V0DS µPD720100A PCI Bus Interface :handles 32-bits 33 MHz PCI Bus master and target function which comply with PCI specification release 2.2. The number of enabled ports are set by bit in configuration space. Arbiter OHCI Host Controller #1 OHCI Host Controller #2 EHCI Host Controller Root Hub PHY INTA0 INTB0 INTC0 SMI0 :arbitrates among two OHCI Host controller cores and one EHCI Host controller core. :handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5. :handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4. :handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5. :handles USB hub function in Host controller and controls connection (routing) between Host controller core and port. :consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, etc :is the PCI interrupt signal for OHCI Host Controller #1. :is the PCI interrupt signal for OHCI Host Controller #2. :is the PCI interrupt signal for EHCI Host Controller. :is the interrupt signal which is specified by Open Host Controller Interface Specification for USB Rev 1.0a. The SMI signal of each OHCI Host Controller appears at this signal. PME0 :is the interrupt signal which is specified by PCI-Bus Power Management Interface Specification release 1.1. Wakeup signal of each host controller core appears at this signal. Data Sheet S15535EJ2V0DS 3 µPD720100A PIN CONFIGURATION • 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AGM-8ED µPD720100AGM-8EY Top View VSS VSS RSDP4 DP4 VDD DM4 RSDM4 VSS RSDP3 DP3 VDD DM3 RSDM3 VSS VDD AVSS RREF AVSS(R) AVDD N.C. PC1 AVSS PC2 AVDD AVSS VDD VSS RSDP2 DP2 VDD DM2 RSDM2 VSS RSDP1 DP1 VDD DM1 RSDM1 VSS VSS 150 140 130 160 155 VDD NTEST1 NTEST2 TEST XT1/SCLK XT2 LEGC VDD VSS VCCRST0 SMI0 IRI1 IRI2 IRO1 IRO2 A20S PME0 PCLK VBBRST0 VDD VSS VDD_PCI INTA0 INTB0 INTC0 PIN_EN GNT0 REQ0 AD31 AD30 VSS AD29 AD28 AD27 AD26 AD25 AD24 CBE30 IDSEL VDD 145 135 125 121 1 120 5 115 10 110 15 105 20 100 25 95 30 90 35 85 40 81 60 65 70 41 45 4 VSS VSS AD23 SMC SIN/TIN SOT/TOUT AD22 AD21 AD20 AD19 VDD AD18 AD17 AD16 CBE20 FRAME0 IRDY0 TRDY0 DEVSEL0 VDD_PCI STOP0 PERR0 SERR0 PAR CBE10 VSS AD15 AD14 AD13 VDD AD12 AD11 AD10 AD9 AD8 CBE00 AD7 AD6 VSS VSS 50 Data Sheet S15535EJ2V0DS 55 75 80 VDD SELCLK N.C. SELDAT VSS RSDP5 DP5 VDD DM5 RSDM5 VSS CLKSEL VSS PPON5 TEB PPON4 SCK/TCLK PPON3 PPON2 VSS VDD OCI3 AMC OCI4 OCI2 OCI5 PPON1 OCI1 SRMOD SRCLK SRDTA VDD_PCI CRUN0 AD0 AD1 AD2 AD3 AD4 AD5 VDD µPD720100A Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name VDD NTEST1 NTEST2 TEST XT1/SCLK XT2 LEGC VDD VSS VCCRST0 SMI0 IRI1 IRI2 IRO1 IRO2 A20S PME0 PCLK VBBRST0 VDD VSS VDD_PCI INTA0 INTB0 INTC0 PIN_EN GNT0 REQ0 AD31 AD30 VSS AD29 AD28 AD27 AD26 AD25 AD24 CBE30 IDSEL VDD Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name VSS VSS AD23 SMC SIN/TIN SOT/TOUT AD22 AD21 AD20 AD19 VDD AD18 AD17 AD16 CBE20 FRAME0 IRDY0 TRDY0 DEVSEL0 VDD_PCI STOP0 PERR0 SERR0 PAR CBE10 VSS AD15 AD14 AD13 VDD AD12 AD11 AD10 AD9 AD8 CBE00 AD7 AD6 VSS VSS Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name VDD AD5 AD4 AD3 AD2 AD1 AD0 CRUN0 VDD_PCI SRDTA SRCLK SRMOD OCI1 PPON1 OCI5 OCI2 OCI4 AMC OCI3 VDD VSS PPON2 PPON3 SCK/TCLK PPON4 TEB PPON5 VSS CLKSEL VSS RSDM5 DM5 VDD DP5 RSDP5 VSS SELDAT N.C. SELCLK VDD Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name VSS VSS RSDM1 DM1 VDD DP1 RSDP1 VSS RSDM2 DM2 VDD DP2 RSDP2 VSS VDD AVSS AVDD PC2 AVSS PC1 N.C. AVDD AVSS (R) RREF AVSS VDD VSS RSDM3 DM3 VDD DP3 RSDP3 VSS RSDM4 DM4 VDD DP4 RSDP4 VSS VSS Remark AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Data Sheet S15535EJ2V0DS 5 µPD720100A • 176-pin plastic FBGA (15 × 15) µPD720100AS1-2C Bottom View 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 15 U T 32 90 141 140 139 138 137 136 135 134 133 132 131 130 129 74 14 R 128 73 13 P 127 72 12 N 126 71 11 M 125 70 10 L 167 124 69 9 K 166 123 68 8 J 165 122 67 7 H 121 66 6 G 120 65 5 F 119 64 4 E 118 63 3 D 170 169 168 174 175 176 33 91 142 34 92 143 35 93 144 36 94 145 37 95 146 171 38 96 147 172 39 97 148 173 40 98 149 41 99 150 42 100 151 43 101 152 44 102 153 154 155 156 157 158 159 160 161 162 163 164 117 62 2 C 45 103 104 105 106 107 108 109 110 111 112 113 114 115 116 61 1 B A 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 6 Data Sheet S15535EJ2V0DS µPD720100A Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name VSS VSS SMC AD20 AD18 CBE20 DEVSEL0 VDD_PCI SERR0 VSS AD14 AD11 CBE00 AD6 VSS AD5 N.C. AD3 VDD_PCI SRMOD OCI5 OCI3 VDD PPON3 TEB VSS DM5 VSS N.C. N.C. VSS N.C. DM1 RSDM2 DP2 VDD AVSS PC1 AVSS (R) VDD RSDM3 RSDP3 N.C.(VDD) RSDP4 Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Pin Name VDD NTEST1 NANDTEST TEST VSS IRI1 IRO2 VBBRST0 VDD INTA0 PIN_EN REQ0 AD29 AD25 CBE30 N.C. IDSEL VSS AD23 AD22 AD19 AD17 FRAME0 TRDY0 CBE10 AD13 AD12 AD9 AD7 VSS VSS VDD AD4 AD0 SRDTA OCI1 OCI2 AMC PPON4 CLKSEL RSDM5 DP5 SELDAT VDD Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Pin Name SELCLK VSS RSDM1 RSDP1 DM2 RSDP2 AVSS PC2 AVSS DM3 DP3 RSDM4 DP4 VSS VSS VDD NTEST2 LEGC VCCRST0 IRI2 A20S PCLK INTC0 AD31 VSS AD27 AD24 VDD SIN/TIN SOT/TOUT AD21 VDD AD16 IRDY0 STOP0 PAR AD15 VDD AD10 AD8 AD2 AD1 CRUN0 SRCLK Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pin Name PPON1 OCI4 VSS SCK/TCLK PPON5 VSS VDD RSDP5 VDD DP1 VSS VDD VSS AVDD N.C. RREF VSS VDD VSS DM4 XT1/SCLK XT2 VDD SMI0 IRO1 PME0 VSS INTB0 GNT0 AD30 AD28 AD26 VSS VDD PERR0 VSS VSS PPON2 VSS VSS AVDD VSS VDD VDD_PCI Remarks 1. Pin 43 can be opened. But this signal is connected to pin 45 in the package. Should not be connected to GND. 2. AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Data Sheet S15535EJ2V0DS 7 µPD720100A 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Level AD (31 : 0) CBE (3 : 0)0 PAR FRAME0 IRDY0 TRDY0 STOP0 IDSEL DEVSEL0 REQ0 GNT0 PERR0 SERR0 INTA0 INTB0 INTC0 PCLK VBBRST0 CRUN0 PME0 VCCRST0 SMI0 PIN_EN XT1/SCLK XT2 DP (5 : 1) DM (5 : 1) RSDP (5 : 1) RSDM (5 : 1) OCI (5 : 1) PPON (5 : 1) LEGC IRI1 IRI2 IRO1 IRO2 A20S I/O I/O I/O I/O I/O I/O I/O I I/O O I I/O O O O O I I I/O O I O I I O I/O I/O O O I (I/O) O (I/O) I (I/O) I (I/O) I (I/O) O O O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI Input 5 V PCI I/O 5 V PCI Output 5 V PCI Input 5 V PCI I/O 5 V PCI N-ch Open Drain 5 V PCI N-ch Open Drain 5 V PCI N-ch Open Drain 5 V PCI N-ch Open Drain 5 V PCI Input 5 V PCI Input 5 V PCI I/O 5 V PCI N-ch Open Drain 5 V tolerant Input 5 V tolerant N-ch Open Drain 5 V tolerant Input Input Output USB high speed D+I/O USB high speed D−I/O USB full speed D+ O USB full speed D− O 5 V tolerant Input 5 V tolerant Output Input 5 V tolerant Input 5 V tolerant Input 5 V tolerant Output 5 V tolerant Output 5 V tolerant 3-state Output Low High High High High High High Low Low Low High Low Low Low Low PCI “AD [31 : 0]” signal PCI “C/BE [3 : 0]” signal PCI “PAR ” signal PCI “FRAME#” s ignal PCI “IRDY#” signal PCI “TRDY#” signal PCI “STOP#” signal PCI “IDSEL” signal PCI “DEVSEL#” signal PCI “REQ#” signal PCI “GNT#” signal PCI “PERR#” signal PCI “SERR#” signal PCI “INTA#” signal PCI “INTB#” signal PCI “INTC#” signal PCI “CLK” signal Hardware Reset for Chip PCI “CLKRUN#” signal PCI “PME#” signal RESET for Power Management System management interrupt output PCI Interface enable System clock input or Oscillator In Oscillator Out USB’s high speed D+ signal USB’s high speed D − signal USB’s full speed D+ signal USB’s full speed D− signal USB Root Hub Port’s overcurrent status input USB Root Hub Port’s power supply control output Legacy support switch INT input from keyboard INT input from mouse INT output from keyboard INT output from mouse GateA20 State output Function 8 Data Sheet S15535EJ2V0DS µPD720100A (2/2) Pin Name I/O Buffer Type Active Level RREF PC1 PC2 NTEST(2:1) SMC SIN/TIN SOT/TOUT TEB AMC SCK/TCLK CLKSEL TEST NANDTEST SELDAT SELCLK SRCLK SRDTA SRMOD AVDD VDD VDD_PCI AVSS VSS N.C. A A A I I I O I I I I I I O O O I/O I Analog Analog Analog Input with 12 kΩ Pull down R Input with 50 kΩ Pull down R Input with 50 kΩ Pull down R Output Input with 50 kΩ Pull down R Input with 50 kΩ Pull down R Input with 50 kΩ Pull down R Input with 50 kΩ Pull down R Input with 50 kΩ Pull down R Input with 50 kΩ Pull down R Output Output Output I/O Input with 50 kΩ Pull down R High High High High High High High Reference resistor Capacitor for PLL Capacitor for PLL Test pin Scan mode control Scan input or RAM BIST input Scan output or RAM BIST output BIST enable ATG mode control Scan clock or RAM BIST clock Clock select signal Test Control NAND Tree Test enable Test signal Test signal Serial ROM Clock Out Serial ROM Data Serial ROM Input Enable VDD for Analog circuit VDD 5 V (5 V PCI) or 3.3 V (3.3 V PCI) VSS for Analog circuit VSS Not connect Function Remarks 1. “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit. 2. “5 V PCI” indicates a PCI buffer, which complies with the 3 V PCI standard, has a 5 V tolerant circuit. It does not indicate a buffer that fully complies with 5 V PCI standard. However, this function can be used for evaluating the operation of a device on a 5V add-in card. 3. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use. Data Sheet S15535EJ2V0DS 9 µPD720100A 2. 2.1 • • • • • • • • • • • ELECTRICAL SPECIFICATIONS Buffer List 3 V input buffer with Pull down resister NTEST1, NTEST2, TEST, SMC, SIN/TIN, SRMOD, AMC, SCK/TCLK, CLKSEL, TEB 3 V output buffer SOT/TOUT (IOL = 9 mA), SRCLK (IOL = 3 mA) 3 V bi-directional buffer LEGC (IOL = 9 mA), SRDTA (IOL = 3 mA) 3 V Oscillator interface XT1/SCLK, XT2 5 V input buffer VCCRST0, PIN_EN 5 V IOL = 12 mA N-ch Open Drain buffer SMI0, PME0, INTA0, INTB0, INTC0, SERR0 5 V IOL = 6 mA 3-state Output buffer A20S 5 V IOL = 12 mA 3-state Output buffer IRO1, IRO2 5 V PCI Input buffer with enable (OR type) PCLK, VBBRST0, GNT0, IDSEL 5 V PCI IOL = 12 mA 3-state Output buffer REQ0 5 V PCI IOL = 12 mA bi-directional buffer with input enable (OR-type) AD(31:0), CBE(3:0)0, PAR, FRAME0, IRDY0, TRDY0, STOP0, DEVSEL0, PERR0, CRUN0, IRI(1:2), PPON(1:5), OCI(1:5) • USB interface DP(1:5), DM(1:5), RSDP(1:5), RSDM(1:5), PC1, PC2, RREF, SELDAT, SELCLK Above, “5 V” refers to a 3-V buffer with 5-V tolerant circuit. Therefore, it is possible to have a 5-V connection for an external bus, but the output level will be only up to 3 V, which is the VDD voltage. Similarly, “5 V PCI” above refers to a PCI buffer that has a 5-V tolerant circuit, which meets the 3-V PCI standard; it does not refer to a PCI buffer that meets the 5-V PCI standard. 10 Data Sheet S15535EJ2V0DS µPD720100A 2.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Symbol VDD Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Operating temperature Storage temperature TA Tstg Indicates the ambient temperature range for normal logic operations. Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. Terms Used in Recommended Operating Range Parameter Power supply voltage High-level input voltage Symbol VDD VIH Meaning Indicates the voltage range for normal logic operations occur when VSS = 0V. Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “MIN.” v alue is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “ MAX.” value is applied, the input voltage is guaranteed as low level voltage. Terms Used in DC Characteristics Parameter Off-state output leakage current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Output short circuit current IOS Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that flows from the output pins when the rated highlevel output voltage is being applied. Data Sheet S15535EJ2V0DS 11 µPD720100A 2.3 Electrical Specifications Absolute Maximum Ratings Parameter Power supply voltage Input voltage, 5 V buffer Symbol VDD VI 3.0 V ≤ VDD ≤ 3.6 V VI < VDD + 3.0 V Input voltage, 3.3 V buffer VI 3.0 V ≤ VDD ≤ 3.6 V VI < VDD + 0.5 V Output voltage, 5 V buffer VO 3.0 V ≤ VDD ≤ 3.6 V VO < VDD + 3.0 V Output voltage, 3.3 V buffer VO 3.0 V ≤ VDD ≤ 3.6 V VO < VDD + 0.5 V Operating temperature Storage temperature TA Tstg 0 to +70 −65 to +150 °C °C −0.5 to +4.6 V −0.5 to +6.6 V −0.5 to +4.6 V Condition Rating −0.5 to +4.6 −0.5 to +6.6 Unit V V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges Parameter Operating voltage High-level input voltage 3.3 V High-level input voltage 5.0 V High-level input voltage Low-level input voltage 3.3 V Low-level input voltage 5.0 V Low-level input voltage VIL 0 0 0.8 0.8 V V Symbol VDD VIH 2.0 2.0 VDD 5.5 V V Condition MIN. 3.0 TYP. 3.3 MAX. 3.6 Unit V 12 Data Sheet S15535EJ2V0DS µPD720100A DC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°C) Control Pin Block Parameter Off-state output current Output short circuit current Low-level output current 3.3 V Low-level output current 3.3 V Low-level output current 5.0 V Low-level output current 5.0 V Low-level output current High-level output current 3.3 V High-level output current 3.3 V High-level output current 5.0 V High-level output current 5.0 V High-level output current Input leakage current 3.3 V buffer 3.3 V buffer with 50 kΩ PD 5.0 V buffer II VI = VDD or VSS VI = VDD VI = VDD or VSS ±10 191 ±10 IOH VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V −9.0 −3.0 −2.0 −2.0 mA mA mA mA Symbol IOZ IOS IOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 9.0 3.0 12.0 6.0 mA mA mA mA Note Condition VO = VDD or VSS MIN. MAX. ±10 −250 Unit µA mA µA µA µA Note The output short circuit time is one second or less and is only for one pin on the LSI. PCI Interface Block Parameter High-level input voltage Low-level input voltage Low-level output current High-level output current Input high leakage current Input low leakage current PME0 leakage current Symbol Vih Vil IOL IOH Iih Iil Ioff VOL = 0.4 V VOH = 2.4 V Vin = 2.7 Vin = 0.5 VO < 3.6 V VCC off or floating Condition MIN. 2.0 0 12.0 −2.0 70 −70 1 MAX. 5.25 0.8 Unit V V mA mA µA µA µA Data Sheet S15535EJ2V0DS 13 µPD720100A USB Interface Block Parameter Serial Resistor between DP (DM) and RSDP (RSDM). Output pin impedance Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential Common mode Range Output Levels for Low-/full-speed: High-level output voltage Low-level output voltage SE1 Output signal crossover point voltage Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling level Output Levels for High-speed: High-speed idle state High-speed data signaling high High-speed data signaling low Chirp J level (different signal) Chirp K level (different signal) VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK −10.0 360 −10.0 700 −900 +10 440 +10 1100 −500 mV mV mV mV mV See Figure 2-4. VHSCM −50 +500 mV VHSDSC 525 625 mV VHSSQ 100 150 mV VOH VOL VOSE1 VCRS RL of 14.25 kΩ to GND RL of 1.425 kΩ to 3.6 V 2.8 0.0 0.8 1.3 2.0 3.6 0.3 V V V V VIH VIHZ VIL VDI VCM (D+) − (D−) Includes VDI range 0.2 0.8 2.5 2.0 2.7 3.6 0.8 V V V V ZHSDRV Includes RS resistor 40.5 49.5 Ω Symbol RS Conditions MIN 35.64 MAX 36.36 Unit Ω 14 Data Sheet S15535EJ2V0DS µPD720100A Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range -1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6 Input Voltage Range (Volts) Figure 2-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver VDD-3.3 VDD-2.8 VDD-2.3 VDD-1.8 VDD-1.3 VDD-0.8 VDD-0.3 VDD 0 -20 Iout (mA) -40 Min. -60 Max. -80 Vout (V) Figure 2-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver 80 Max. 60 Iout (mA) Min. 40 20 0 0 0.5 1 1.5 Vout (V) 2 2.5 3 Data Sheet S15535EJ2V0DS 15 µPD720100A Figure 2-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 + 400 mV Differential Point 3 Point 4 Point 1 Point 2 0V Differential Point 5 Point 6 Level 2 − 400 mV Differential 0% Unit Interval 100% Figure 2-5. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 15.8 Ω 143 Ω 143 Ω Pin Capacitance Parameter Input capacitance Output capacitance I/O capacitance PCI input pin capacitance PCI clock input pin capacitance PCI IDSEL input pin capacitance Symbol CI CO CIO Cin Cclk CIDSEL Condition VDD = 0 V, TA = 25°C fC = 1 MHz Unmeasured pins returned to 0 V 6 MIN. 6 10 10 MAX. 8 12 12 8 8 8 Unit pF pF pF pF pF pF 16 Data Sheet S15535EJ2V0DS µPD720100A Power Consumption Parameter Power Consumption Symbol PWD0-0 Condition The power consumption under the state without suspend. Device state = D0, All the ports does not connect to any Note 1 function. PWD0-2 The power consumption under the state without suspend. Device state = D0, The number of active ports is 2. EHCI host controller is inactive. EHCI host controller is active. PWD0-3 The power consumption under the state without suspend. Note 2 Device state = D0, The number of active ports is 3. EHCI host controller is inactive. EHCI host controller is active. PWD0-4 The power consumption under the state without suspend. Device state = D0, The number of active ports is 4. EHCI host controller is inactive. EHCI host controller is active. PWD0-5 The power consumption under the state without suspend. Note 2 Device state = D0, The number of active ports is 5. EHCI host controller is inactive. EHCI host controller is active. PWD0_S The power consumption under suspend state. Device state = D0, The internal clock is stopped. PWD0_C N ote 3 Note 2 Note 2 TYP. 168.0 Unit mA 186.2 301.6 mA mA 195.3 368.4 mA mA 204.4 435.2 mA mA 213.5 502.0 136.2 mA mA mA The power consumption under suspend state during PCI clock is stopped by CRUN0. Device state = D0, Note 3 The internal clock is stopped. 113.0 mA PWD1 PWD2 PWD3H Device state = D1, Analog PLL output is stopped. Device state = D2, Analog PLL output is stopped. Device state = D3hot, PIN_EN = High Analog PLL output is stopped. Note 3, 4 N ote 3, 4 24.7 10.9 10.9 mA mA mA N ote 3, 4 PWD3C Device state = D3cold , PIN_EN = Low Note 3, 4, 5 Oscillator output is stopped. 650 µA Notes 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend on the number of active ports. 2. The number of active ports is set by the value of Port No field in PCI configuration space EXT register. 3. For the condition of clock stop, see µPD720100A User’s Manual 7.3 Control for System Clock Operation. 4. When the device state = D1, PCI clock is defined as it is running. When the device state = D2 or D3, PCI clock is defined as it is stopped. 5. If 48 MHz oscillator clock-in is used, power consumption for oscillator block + HC chip will be more than 15 mA. Data Sheet S15535EJ2V0DS 17 µPD720100A System Clock Ratings Parameter Clock frequency Symbol fCLK X’tal Condition MIN. −500 ppm Oscillator block −500 ppm Clock Duty cycle tDUTY 40 50 48 TYP. 30 MAX. +500 ppm +500 ppm 60 % MHz Unit MHz Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or Oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply voltage, temperature, and aging, etc. 18 Data Sheet S15535EJ2V0DS µPD720100A AC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°C) PCI Interface Block Parameter PCI clock cycle time PCI clock pulse, high-level width PCI clock pulse, low-level width PCI clock, rise slew rate PCI clock, fall slew rate PCI reset active time (vs. power supply stability) PCI reset active time (vs. CLK Start) Output float delay time (vs. RST0↓) PCI reset rise slew rate PCI bus signal output time (vs. PCLK↑) PCI point-to-point signal output time (vs. PCLK↑) Output delay time (vs. PCLK↑) Output float delay time (vs. PCLK↑) Input setup time (vs. PCLK↑ ) Point-to-point input setup time (vs. PCLK↑) Input hold time ton toff tsu tsu (ptp) th GNT0 7 10 0 2 28 ns ns ns ns ns trst-clk trst-off Srr tval tval (ptp) REQ0 50 2 2 11 12 100 40 Symbol tcyc thigh tlow Scr Scf trst 0.2 VDD to 0.6 VDD 0.2 VDD to 0.6 VDD Conditions MIN. 30 11 11 1 1 1 4 4 MAX. Unit ns ns ns V/ns V/ns ms µs ns mV/ns ns ns Data Sheet S15535EJ2V0DS 19 µPD720100A USB Interface Block (1/2) Parameter Low Source Electrical Characteristics Rise time (10% - 90%) tLR CL = 50 pF – 150 pF, RS = 3 6 Ω Fall time (90% - 10%) tLF CL = 50 pF – 150 pF, RS = 3 6 Ω Differential Rise and Fall Time matching Low-speed Data Rate Source Jitter Total (including frequency tolerance): To Next Transition For Paired Transitions Source Jitter for Differential Transition to SE0 transition Receiver Jitter: To Next Transition For Paired Transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition Full-speed Source Electrical Characteristics Rise time (10% - 90%) tFR CL = 50 pF, RS = 3 6 Ω Fall time (90% - 10%) tFF CL = 50 pF, RS = 3 6 Ω Differential Rise and Fall Time matching Full-speed Data Rate Frame Interval Consecutive Frame Interval Jitter Source Jitter Total (including frequency tolerance): To Next Transition For Paired Transitions Source Jitter for Differential Transition to SE0 transition Receiver Jitter: To Next Transition For Paired Transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition tJR1 tJR2 tFEOPT tFEOPR tFST −18.5 −9 160 82 14 +18.5 +9 175 ns ns ns ns ns tDJ1 tDJ2 tFDEOP −3.5 −4.0 −2 +3.5 +4.0 +5 ns ns ns tFRFM tFDRATHS tFRAME tRFI No clock adjustment (tFR/tFF) Average bit rate 90 11.9940 0.9995 111.11 12.0060 1.0005 42 % Mbps ms ns 4 20 ns 4 20 ns tUJR1 tUJR2 tLEOPT tLEOPR tFST −152 −200 1.25 670 210 +152 +200 1.50 ns ns tDDJ1 tDDJ2 tLDEOP −25 −14 -40 +25 +14 +100 ns ns ns tLRFM tLDRATHS (tLR/tLF) Average bit rate 80 1.49925 125 1.50075 % Mbps 75 300 ns 75 300 ns Symbol Conditions MIN. MAX. Unit µs ns ns 20 Data Sheet S15535EJ2V0DS µPD720100A (2/2) Parameter Symbol Conditions MIN. MAX. Unit High-speed Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Driver waveform High-speed Data Rate Microframe Interval Consecutive Microframe Interval Difference tHSR tHSF See Figure 2-6. tHSDRAT tHSFRAM tHSRFI 479.760 124.9375 480.240 125.0625 4 highspeed Data source jitter Receiver jitter tolerance Hub event Timings Time to detect a downstream facing port connect event Time to detect a disconnect event at a downstream facing port: Duration of driving resume to a downstream port Time from detecting downstream resume to rebroadcast. Inter-packet Delay for packets traveling in same direction for high-speed Inter-packet Delay for packets traveling in opposite direction for high-speed Inter-packet delay for root hub response for high-speed Time for which a Chirp J or Chirp K must be continuously detected during Reset handshake Time after end of device Chirp K by which hub must start driving first Chirp K Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream during reset Time before end of reset by which a hub must end its downstream chirp sequence tDCHSE0 100 500 tDCHBIT 40 60 tWTDCH 100 tFILT 2.5 tHSRSPIPD1 192 tHSIPDOD 8 tHSIPDSD 88 Bit times Bit times Bit times tURSM 1.0 ms tDRSMDN Nominal 20 ms tDDIS 2.0 2.5 tDCNN 2.5 2000 See Figure 2-6. See Figure 2-4. Mbps 500 500 ps ps µs Bit times µs µs µs µs µs µs Data Sheet S15535EJ2V0DS 21 µPD720100A Figure 2-6. Transmit Waveform for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 Point 2 0V Differential Point 5 Level 2 Point 6 −400 mV Differential Unit Interval 0% 100% Figure 2-7. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 15.8 Ω 143 Ω 143 Ω 22 Data Sheet S15535EJ2V0DS µPD720100A Timing Diagram PCI Clock tcyc thigh 0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD tlow 0.4VDD(ptp:min) PCI Reset PCLK 100 ms (typ.) PWR_GOOD trst-clk trst VBBRST0 trst-off PCI Signals Valid PCI Output Timing Measurement Condition 0.6VDD PCLK 0.4VDD tval , tval(ptp) 0.2VDD output delay 0.615VDD (for falling edge) 0.285VDD (for falling edge) output ton toff Data Sheet S15535EJ2V0DS 23 µPD720100A PCI Input Timing Measurement Condition 0.6VDD PCLK 0.4VDD 0.2VDD tsu, tsu(ptp) th 0.6VDD input 0.4VDD 0.2VDD USB Differential Data Jitter for Low-/full-speed tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N × tPERIOD + tDJ1, tDDJ1 Paired Transitions N × tPERIOD + tDJ2, tDDJ2 USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed tPERIOD Differential Data Lines Crossover Point Crossover Point Extended Diff. Data-toSE0 Skew N × tPERIOD + tFDEOP, tLDEOP Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR 24 Data Sheet S15535EJ2V0DS µPD720100A USB Receiver Jitter Tolerance for Low-/full-speed tPERIOD Differential Data Lines tJR, tUJR tJR1, tUJR1 tJR2, tUJR2 Consecutive Transitions N × tPERIOD + tJR1, tUJR1 Paired Transitions N × tPERIOD + tJR2, tUJR2 Low-/full-speed Disconnect Detection D+/DVIZH (min) VIL D-/D+ VSS tDDIS Device Disconnected Full-/high-speed Device Connect Detection Disconnect Detected D+ VIH DVSS tDCNN Device Connected Connect Detected Data Sheet S15535EJ2V0DS 25 µPD720100A Low-speed Device Connect Detection DVIH D+ VSS tDCNN Device Connected Connect Detected 26 Data Sheet S15535EJ2V0DS µPD720100A 3. PACKAGE DRAWING 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) A B 120 121 81 80 detail of lead end S C D R Q 160 1 41 40 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 26.0 ± 0.2 24.0 ± 0.2 24.0 ± 0.2 26.0 ± 0.2 2.25 2.25 0.22 + 0.05 − 0.04 0.10 0.5 (T.P.) 1.0 ± 0.2 0.5 ± 0.2 0.145+ 0.055 − 0.045 0.10 1.4 ± 0.1 0.125 ± 0.075 3°+7° −3° 1.7 MAX. S160GM-50-8ED-3 Data Sheet S15535EJ2V0DS 27 µPD720100A 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) A B 120 121 81 80 detail of lead end S P C D T R Q 160 1 41 40 L U F G H I M J K S ITEM MILLIMETERS 26.0 ± 0.2 24.0 ± 0.2 24.0 ± 0.2 26.0 ± 0.2 2.25 2.25 0.22 + 0.05 − 0.04 0.08 0.5 (T.P.) 1.0 ± 0.2 0.5 0.17 + 0.03 − 0.07 0.08 1.4 ± 0.05 0.10 ± 0.05 3° +4° −3° 1.6 MAX. 0.25 (T.P.) 0.16 ± 0.15 P160GM-50-8EY A B C D F G H I J K L M N P Q R S T U N NOTE S M Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 28 Data Sheet S15535EJ2V0DS µPD720100A 176-PIN PLASTIC FBGA (15x15) A B W SB B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U T RP NM L K J H G F E D C B A A CD Q Index mark W P SA J I Y1 R S S H ITEM A B C D MILLIMETERS 15.00 ± 0.10 14.40 14.40 15.00 ± 0.10 1.10 0.8 (T.P.) 0.35 ± 0.1 0.36 1.16 1.51 ± 0.15 0.10 K S L F E G E F G H I J K L M P Q R W Y1 φM M SAB φ 0.50+ 0.05 − 0.10 0.08 C1.0 R0.3 25 ° 0.20 0.20 S176S1-80-2C-1 Data Sheet S15535EJ2V0DS 29 µPD720100A 4. RECOMMENDED SOLDERING CONDITIONS The µPD720100A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. µPD720100AGM-8ED: 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AGM-8EY: 160-pin plastic LQFP (Fine pitch) (24 × 24) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Three times or less Exposure limit: 3 days Partial heating Note Symbol IR35-103-3 (after that, prebake at 125°C for 10 hours) – Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. µPD720100AS1-2C: Soldering Method Infrared reflow 176-pin plastic FBGA (15 × 15) Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Three times or less Exposure limit: 7 days Note Symbol IR35-107-3 (after that, prebake at 125°C for 10 hours) – Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. 30 Data Sheet S15535EJ2V0DS µPD720100A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC l2C components conveys a license under the Philips l2C Patent Rights to use these components in an l2C system, provided that the system conforms to the l 2C Standard Specification as defined by Philips. Data Sheet S15535EJ2V0DS 31 µPD720100A USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of October, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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