UPD72107CW

DATA SHEET MOS INTEGRATED CIRCUIT µPD72107 LAP-B CONTROLLER Link Access Procedure Balanced mode The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single chip. FEATURES • Complied with ITU-T recommended X.25 (LAP-B84 edition) HDLC frame control Sequence control Flow control • ITU-T recommended X.75 supported • TTC standard JT-T90 supported • Optional functions Option frame Global address frame Error check deletion frame • Powerful test functions Data loopback function Loopback test link function Frame trace function • Abundant statistical information • Detailed mode setting function • Modem control function • On-chip DMAC (Direct Memory Access Controller) 24-bit address Byte/word transfer enabled (switch with external pin) • Memory-based interface Memory-based command Memory-based status Memory-based transmit/receive data • MAX.4 Mbps serial transfer rate • NRZ, NRZI coding ORDERING INFORMATION Part Number Package 64-pin plastic shrink DIP (750 mils) 80-pin plastic QFP (14 x 14 mm) 68-pin plastic QFJ (950 x 950 mils) µPD72107CW µPD72107GC-3B9 µPD72107L The information in this document is subject to change without notice. Document No. S12962EJ5V0DS00 (5th edition) Date Published October 1998 N CP(K) Printed in Japan © 1998 µPD72107 BLOCK DIAGRAM D0-D7 A16D8 -A23D15 A0-A15 IORD IOWR MRD MWR UBE CS ASTB AEN READY HLDRQ HLDAK CRQ INT CLRINT B/W PU VCC GND RESET CLK TxC TxD Internal controller TxFIFO Transmitter RTS CTS Bus interface Internal bus CD Receiver RxFIFO DMAC RxC RxD Name Bus interface Internal controller DMAC (Direct Memory Access Controller) TxFIFO RxFIFO Transmitter Receiver Internal bus Function An interface between the µPD72107 and external memory or external host processor Manages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block Controls the transfer of data on the external memory to the internal controller or transmitter block, and controls the writing of data in the internal controller or receiver block to the external memory A 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block A 32-byte buffer for when receive data is sent from the receiver block to the DMAC Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data Receives HDLC frame and writes internal data to RxFIFO An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block, and bus interface block 2 µPD72107 PIN CONFIGURATION (Top View) 64-pin plastic shrink DIP (750 mils) µ PD72107CW IC RxC RxD TxC TxD CTS IC RESET NC IC B/W PU CLK GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16D8 A17D9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RTS CD CRQ AEN ASTB READY HLDAK HLDRQ CLRINT INT UBE MWR MRD GND IOWR IORD CS VCC D7 D6 D5 D4 D3 D2 D1 D0 A23D15 A22D14 A21D13 A20D12 A19D11 A18D10 3 µPD72107 80-pin plastic QFP (14 × 14 mm) µ PD72107GC-3B9 CLRINT GND IOWR IORD UBE MWR MRD INT VCC NC VCC D7 D6 NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NC HLDRQ HLDAK READY ASTB AEN NC CRQ CD RTS NC IC RxC RxD NC TxC TxD CTS IC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D1 D0 A23D15 A22D14 A21D13 NC A20D12 A19D11 A18D10 NC NC A17D9 A16D8 A15 A14 A13 A12 A11 A10 NC NC RESET IC B/W PU CLK GND GND NC 4 NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 NC CS D5 D4 D3 D2 µPD72107 68-pin plastic QFJ (950 × 950 mils) µ PD72107L 9 RESET IC B/W PU CLK GND GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 HLDRQ READY HLDAK ASTB CRQ AEN CTS RTS RxD RxC TxD TxC NC NC CD IC IC CLRINT INT UBE MWR MRD GND IOWR IORD CS VCC VCC D7 D6 D5 D4 D3 D2 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A10 A11 A12 A13 A14 A15 A16D8 A17D9 NC D0 A18D10 A19D11 A20D12 A21D13 A22D14 A23D15 D1 5 µPD72107 1. PINS 1.1 Pin Functions SDIP Pin Name Pin No. VCC 47 Pin No. 68 70 GND 14 51 27 28 74 CLK (Clock) RESET (Reset) 8 22 10 I L 13 26 Pin No. 50 51 15 16 55 14 I – System clock input Input clock of 1 MHz to 8.2 MHz. Initializes the internal µ PD72107. Active width of more than 7 CLK clock cycles is required (clock input is required). After reset, this pin becomes a bus slave. PU (Pull Up) CS (Chip Select) 48 71 52 I L When bus master Set to disable. When bus slave Read/write operation from the host processor at low level is enabled. MRD (Memory Read) 52 75 56 O 3-state L When bus master Reads the data of the external memory at low level. When bus slave High impedance MWR (Memory Write) 53 76 57 O 3-state L When bus master Writes the data to the external memory at low level. When bus slave High impedance IORD (I/O Read) 49 72 53 I L This pin is used when the external host processor reads the contents of the internal registers of the 12 25 13 I – Pull up to high level when using in normal operation. – – Ground (0 V) Note that there is more than one ground pin. – QFP QFJ I/O Level – +5 V power supply Active Function µ PD72107. IOWR (I/O Write) 50 73 54 I L This pin is used when the external host processor writes the data to the internal registers of the µ PD72107. ASTB (Address Strobe) 60 5 64 O H This pin is used to latch the address output from the µ PD72107 externally. 6 µPD72107 SDIP Pin Name Pin No. NC (No Connection) 9 Pin No. 1, 7, 11, 15, 20, 21, 29, 40, 41, 50, 51, 55, 61, 69, 80 IC (Internally Connected) UBE (Upper Byte Enable) 1 7 10 54 12 19 23 77 2 9 11 58 I/O 3-state L/H When bus master (output) The signal output from this pin changes according to the input value of the B/W pin. • Byte transfer mode (B/W = 0) UBE is always high impedance. • Word transfer mode (B/W = 1) Indicates that valid data is either in pins D0 to D7 or pins A16D8 to A23D15 (or both). UBE 0 0 1 1 A0 0 1 0 1 × × × × D0 to D7 A16D8 to A23D15 – – Do not connect anything to this pin. Pin No. 1 5 35 – QFP QFJ I/O Level – Use this pin open. Active Function When bus slave (input) UBE pin becomes input, and indicates that valid data is either in pins D0 to D7 or pins A16D8 to A23D15. UBE 0 0 1 1 A0 0 1 0 1 × × × D0 to D7 A16D8 to A23D15 × 7 µPD72107 SDIP Pin No. B/W (Byte/Word) 11 QFP Pin No. 24 QFJ Pin No. 12 I Active Level L/H Specifies the data bus that accesses the external memory when bus master. B/W = 0 B/W = 1 Byte units (8 bits) Word units (16 bits) Pin Name I/O Function After power-on, fix the status of the B/W pin. In the case of word access, the lower data bus is the contents data of even addresses. READY (Ready) 59 4 63 I H An input signal that is used to extend the MRD and MWR signal widths output by the µPD72107 to adapt to low-speed memory. When the READY signal is low level, the MRD and MWR signals maintain active low. Do not change the READY signal at any time other than the specified setup/ hold time. HLDRQ (Hold Request) 57 2 61 O H A hold request signal to the external host processor. When a DMA operation is performed in the µPD72107, this signal is activated to switch from bus slave to bus master. HLDAK (Hold Acknowledge) 58 3 62 I H A hold acknowledge signal from the external host processor. When the µPD72107 detects that this signal is active, the bus slave switches to bus master, and a DMA operation is started. AEN (Address Enable) 61 6 65 O H When bus master, this signal enables the latched higher addresses and outputs them to system address bus. This signal is also used for disabling other system bus drivers. A0, A1 15, 16 30, 31 17, 18 I/O 3-state – Bidirectional 3-state address lines. When bus master (output) Indicate the lower 2-bit addresses of memory access. When bus slave (input) Input addresses when the external host processor I/O accesses the µPD72107. A2 to A15 17 to 30 32 to 47 (except 40, 41) 19 to 32 O 3-state – When bus master Output bit 2 to bit 15 of memory access addresses. When bus slave Become high impedance. 8 µPD72107 SDIP Pin Name A16D8 to A23D15 Pin No. 31 to 38 QFP Pin No. 48 to 58 QFJ Pin No. 33 to 41 I/O I/O Active Level – Function Bidirectional 3-state address/data buses. Multiplex pins of the higher 16 bits to 23 bits of addresses and the higher 8 bits to 15 bits of data. 42 to 49 I/O 3-state – Bidirectional 3-state data buses. When bus master When writing to external memory, these pins become input if reading at output. When bus slave Usually, these pins become high impedance. When the external host processor reads I/O of the µPD72107, the internal register data is output. CRQ (Command Request) 62 8 66 I H A signal requesting command execution to the (except 50, (except 35) 3-state 51, 55) D0 to D7 39 to 46 59 to 67 (except 61) µPD72107 by the external host processor. The µPD72107 starts fetching commands from on the external memory at the rising edge of this signal. An interrupt signal from the µ PD72107 to the external host processor. 56 79 60 I H A signal inactivating the INT signal being output by the µPD72107. The µPD72107 generates the CLRINT signal in the LSI internal circuit at the rising edge of this signal, and forcibly makes the INT output signal low. INT (Interrupt) CLRINT (Clear Interrupt) 55 78 59 O H CTS (Clear To Send) 6 18 8 I – A general-purpose input pin. The µPD72107 reports the “CTS pin change detection status” to the external host processor when the input level of this pin is changed in the generalpurpose input/output pin support (setting RSSL to 1 by the “system initialization command”). The change of input level is recognized only when the same level is sampled twice in succession after sampling in 8-ms cycles and detecting the change. Moreover, when the external host processor issues a “general-purpose input/output pin read command” to the µPD72107, the µPD72107 reports the pin information of this pin to the external host processor by a “general-purpose input/output pin read response status”. The change can be detected even in the clock input stop status of TxC and RxC. 9 µPD72107 SDIP Pin Name RTS (Request To Send) Pin No. 64 QFP Pin No. 10 QFJ Pin No. 68 I/O O Active Level – Function A general-purpose output pin. The output value of this pin can be changed by issuing an “RTS pin write command” from the external host processor to the µPD72107. Moreover, when the external host processor issues a “general-purpose input/output pin read command” to the µPD72107, the µPD72107 reports the pin information of this pin to the external host processor by a “general-purpose input/output pin read response status”. CD (Carrier Detect) 63 9 67 I – A general-purpose input pin. The µPD72107 reports the “CD pin change detection status” to the external host processor when the input level of this pin is changed in the generalpurpose input/output pin support (setting RSSL to 1 by the “system initialization command”). The change of input level is recognized only when the same level is sampled twice in succession after sampling in 8-ms cycles and detecting the change. Moreover, when the external host processor issues a “general-purpose input/output pin read command” to the µPD72107, the µPD72107 reports the pin information of this pin to the external host processor by a “general-purpose input/output pin read response status”. The change can be detected even in the clock input stop status of TxC and RxC. TxD (Transmit Data) TxC (Transmit Clock) 4 16 6 I/O 3-state – When CLK is set to 01 or 10 by “operation mode setting LCW” (output) Outputs a clock that divides by 16 the input signal of the RxC pin or CLK pin made by the µPD72107. Caution TxC becomes input because CLK = 00 is the default after reset. It becomes output after setting CLK to 01 or 10 by “operation mode setting LCW”. When CLK is set to 00 by “operation mode setting LCW” (input) Inputs transmit clock externally. 5 17 7 O – A serial transmit data output pin. Remark LCW: abbreviation for Link Command Word 10 µPD72107 SDIP Pin Name Pin No. RxD (Receive Data) RxC (Receive Clock) 2 13 3 I – When CLK is set to 01 or 10 by “operation mode setting LCW” Sixteen times the clock input of the transmit/receive clock for the on-chip DPLL of the µ PD72107 When CLK is set to 00 by “operation mode setting LCW” One time the clock input of the receive clock 3 Pin No. 14 Pin No. 4 I QFP QFJ I/O Level – A serial receive data input pin. Active Function Remark LCW: abbreviation for Link Command Word 1.2 Pin Status after Reset of µ PD72107 The status of the output pins and input/output pins after reset in the µ PD72107 is as shown in Table 1-1. Table 1-1. Pin Status after Reset Pin Number Pin Name 64-pin SDIP 4 5 15, 16 17 to 30 80-pin QFP 16 17 30, 31 32 to 47 (except 40, 41) 48 to 58 (except 50, 51, 55) 59 to 67 (except 61) 75 76 77 78 2 5 6 10 68-pin QFJ 6 7 17, 18 19 to 32 TxC TxD A0, A1 A2 to A15 I/O Note O I/O Note O Note High impedance H High impedance High impedance I/O During Reset 31 to 38 33 to 41 (except 35) 42 to 49 A16D8 to A23D15 I/O Note High impedance 39 to 46 D0 to D7 I/O Note High impedance 52 53 54 55 57 60 61 64 56 57 58 59 61 64 65 68 MRD MWR UBE INT HLDRQ ASTB AEN RTS O Note O Note I/O Note O O O O O High impedance High impedance High impedance L L L L H Note 3-state Remarks 1. The status after reset is released is the same as the status during reset. 2. Input low level to the RESET pin for more than 7 clocks of the system clock. 11 µPD72107 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25°C) Parameter Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VO TA Tstg Conditions Ratings –0.5 to +7.0 –0.5 to V DD + 0.3 –0.5 to V DD + 0.3 –40 to +85 –40 to +125 Unit V V V °C °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. DC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%) Parameter Input voltage, low Symbol VILC VIL Input voltage, high VIHC VIH Output voltage, low Output voltage, high Power supply current Input leakage current Output leakage current VOL VOH I DD I LI I LO CLK pin Other pins CLK and PU pins Other pins I OL = 2.5 mA I OH = –400 µA At operation 0 V ≤ V IN ≤ V DD 0 V ≤ V OUT ≤ VDD 0.7 × V DD 20 50 ±10 ±10 Conditions MIN. –0.5 –0.5 +3.3 +2.2 TYP. MAX. +0.8 +0.8 VDD + 0.3 VDD + 0.3 0.4 Unit V V V V V V mA µA µA Capacitance (TA = +25°C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f C = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. – – – TYP. 8 8 8 MAX. 15 15 20 Unit pF pF pF 12 µPD72107 AC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%) When bus master (1) Parameter CLK cycle time CLK low-level time CLK high-level time CLK rise time CLK fall time Symbol t CYK t KKL t KKH t KR t KF 1.5 – 3.0 V 3.0 – 1.5 V Conditions MIN. 121 50 50 10 10 MAX. 1000 Unit ns ns ns ns ns Load condition DUT CL = 50 pF CL includes jig capacitance. Caution If the load capacitance exceeds 50 pF due to the configuration of the circuit, keep the load capacitance of this device to within 50 pF by inserting a buffer or by some other means. Remark DUT: device under test AC test input/output waveform (except clock) 2.4 V 2.2 V Test points 0.8 V 0.4 V 0.8 V 2.2 V System clock tKF tKKL 3.0 V CLK 1.5 V tCYK tKKH tKR 13 µPD72107 When bus master (2) Parameter HLDRQ ↑ delay time (vs. CLK ↓) HLDRQ ↓ delay time (vs. CLK ↑) HLDAK setup time (vs. CLK ↑) HLDAK hold time (vs. CLK ↑) AEN ↑ delay time (vs. CLK ↓) AEN ↓ delay time (vs. CLK ↑) ASTB ↑ delay time (vs. CLK ↑) ASTB high-level width ASTB ↓ delay time (vs. CLK ↓) ADR/UBE/MRD/MWR delay time (vs. CLK ↑) ADR/UBE/MRD/MWR float time (vs. CLK ↑) ADR setup time (vs. ASTB ↓) ADR hold time (vs. ASTB ↓) MRD ↓ delay time (vs. ADR float) MRD ↓ delay time (vs. CLK ↑) MRD low-level width MRD ↑ delay time (vs. CLK ↑) Data setup time (vs. MRD ↑) Data hold time (vs. MRD ↑) MWR ↓ delay time (vs. CLK ↑) MWR low-level width MWR ↑ delay time (vs. CLK ↑) READY setup time (vs. CLK ↑) READY hold time (vs. CLK ↑) Symbol t DHQH t DHQL t SHA t HHA t DAEH t DAEL t DSTH t STSTH t DSTL t DA t KKH–15 100 100 35 20 100 100 70 Conditions MIN. MAX. 100 100 Unit ns ns ns ns ns ns ns ns ns ns t FA 70 ns t SAST t HSTA t DAR t DRL t RRL2 t DRH t SDR t HRD t DWL t WWL2 t DWH t SRY t HRY t KKH–35 t KKL –20 0 70 2t CYK–50 70 100 0 70 2t CYK–50 70 35 20 ns ns ns ns ns ns ns ns ns ns ns ns ns 14 When bus master CLK tDHQH HLDRQ tSHA tHHA tHHA tDHQL HLDAK tDAEH AEN tDSTH ASTB tSTSTH A16D8-A23D15 Hi-Z Address tSAST A0, A1/A2-A15 UBE Hi-Z tHSTA Address tWWL2 MWR Hi-Z tDWL tHRY tHRY tDWH Hi-Z Hi-Z tDA Output data Hi-Z tDSTL tDAEL READY tFA A16D8-A23D15 Hi-Z tSRY Address tDA Hi-Z MRD tRRL2 tDRL tDAR tSRY Input data tSDR tDRH tHRD tFA Hi-Z Hi-Z µPD72107 15 µPD72107 When bus slave (1) Parameter IOWR low-level width CS low-level hold time (vs. IOWR ↑) ADR/UBE/CS low-level setup time (vs. IOWR ↓) ADR/UBE hold time (vs. IOWR ↑) Data setup time (vs. IOWR ↑) Data hold time (vs. IOWR ↑) IORD low-level width ADR/CS low-level setup time (vs. IORD ↓) ADR/CS low-level hold time (vs. IORD ↑) Data delay time (vs. IORD ↓) Data float time (vs. IORD ↑) RESET low-level width VDD setup time (vs. RESET ↑) RESET ↑ –1st • IOWR/IORD IOWR/IORD recovery time Symbol tWWL t HWCS Conditions MIN. 100 0 MAX. Unit ns ns tSAW 0 ns t HWA t SDW t HWD t RRL tSAR 0 100 0 150 35 ns ns ns ns ns t HRA 0 ns t DRD t FRD t RSTL t SVDD tSYWR t RVWR 10 7tCYK 1000 2tCYK 200 120 100 ns ns ns ns ns ns 16 µPD72107 When bus slave CS tSAW IOWR tHWA A0-A23 UBE tSDW tHWD tWWL tHWCS D0-D15 CS A0-A23 tSAR tRRL IORD tDRD Hi-Z tFRD Hi-Z tHRA D0-D15 VDD tSVDD tRSTL RESET tSYWR IORD/IOWR tRVWR IORD tRVWR tRVWR IOWR tRVWR 17 µPD72107 When bus slave (2) Parameter IOWR/IORD high-level setup time (vs. HLDAK ↑) IOWR/IORD high-level hold time (vs. AEN ↓) Symbol tSWR Conditions MIN. –20 MAX. Unit ns t HWR 100 ns HLDAK tSWR IOWR/IORD AEN tHWR IOWR/IORD When bus slave (3) Parameter CLRINT high-level width INT ↑ delay time (vs. CLK ↑) INT ↓ delay time (vs. CLRINT ↑) CRQ high-level width Symbol t CLCLH t DIH t DIL t CRCRH 100 Conditions MIN. 100 100 100 MAX. Unit ns ns ns ns CLK CLRINT tCLCLH INT tDIH CRQ tCRCRH tDIL 18 µPD72107 Serial block (1) Parameter TxC/RxC cycle time TxC/RxC low-level time TxC/RxC high-level time TxC/RxC rise time TxC/RxC fall time TxD delay time (vs. TxC ↓) RxD setup time (vs. RxC ↑) RxD hold time (vs. RxC ↑) Symbol t CYS t SSL tSSH t SR t SF t DTXD t SRXD t HRXD 50 70 Conditions When on-chip DPLL is not used MIN. 250 110 110 20 12 100 MAX. DC Unit ns ns ns ns ns ns ns ns Serial clock (when on-chip DPLL is not used) tSF tSSL tSR 2.2 V TxC/RxC 0.8 V tCYS tSSH TxC (input) tDTXD TxD tDTXD RxC tSRXD tHRXD RxD 19 µPD72107 Serial block (2) Parameter RxC cycle time Symbol t CYR Conditions When on-chip DPLL is used (source clock = RxC) When on-chip DPLL is used (source clock = CLK) When on-chip DPLL is used (source clock = RxC) When on-chip DPLL is used (source clock = CLK) When on-chip DPLL is used (source clock = RxC) When on-chip DPLL is used (source clock = CLK) When on-chip DPLL is used (source clock = RxC) When on-chip DPLL is used (source clock = CLK) When on-chip DPLL is used (source clock = RxC) When on-chip DPLL is used (source clock = CLK) When on-chip DPLL is used (source clock = RxC) When on-chip DPLL is used (source clock = CLK) When on-chip DPLL is used 500 2000 0.5tCYD–25 0.5tCYD–25 50 0.5tCYD–25 MIN. 30.3 125 10 50 10 50 5 10 5 10 MAX. Unit ns 1000 ns RxC low-level time t SSRL RxC high-level time t SSRH ns RxC rise time t SRR ns RxC fall time t SRF ns Transmit/receive data cycle t CYD ns 16000 ns ns ns ns TxC low-level time TxC high-level time TxD delay time (vs. TxC ↓) TxD hold time (vs. TxC ↑) t TCTCL t TCTCH t DTCTD t HTCTD Serial clock (when on-chip DPLL is used) tCYR tSSRL tSRF RxC tSSRH tSRR TxC tTCTCL tDTCTD tTCTCH tHTCTD TxD tCYD 20 µPD72107 Serial block (3) Parameter RTS ↑ delay time (vs. CLK ↑) RTS ↓ delay time (vs. CLK ↑) CD setup time (vs. CLK ↑) CD hold time (vs. CLK ↑) CTS setup time (vs. CLK ↑) CTS hold time (vs. CLK ↑) Symbol t DRTH t DRTL t SCD t HCD t SCT t HCT 35 20 35 20 Conditions MIN. MAX. 100 100 Unit ns ns ns ns ns ns CLK RTS tDRTL tHCD CD tSCD tHCT CTS tDRTH tSCT 21 µPD72107 3. APPLICATION CIRCUIT EXAMPLE (1) Connection with SIFC (µ PD98201) µ PD72107 µPD98201 TxD RxD LAP-B TxC RxC BINA BOUT1 SIFC BCLK 22 4. SYSTEM CONFIGURATION EXAMPLES µPD72107 System Configuration Example (Local Memory Type) Local memory 64 Kbytes Host processor MEMR MEMW IOR IOW RD WR CS UBE A0-A15 D0-D15 µ PD72107 MRD MWR IORD IOWR CS A B µ PD71086 OE Decoder AB0-AB7 AB8-AB15 A B µ PD71086 OE A0-A15 A0-A15 D0-D7 AB16-AB19 BHE A B µ PD71086 OE A16D8-A23D15 UBE DB0-DB15 A B µ PD71086 OE D0-D15 AEN INT Local bus request WAIT INT Access contention resolution circuit HLDRQ µPD72107 HLDAK 23 24 µ PD72107 System Configuration Example (Main Memory Sharing Type) Host processor INTP CS A0 µ PD72107 INT µ PD70116 INT INTAK RD WR HLDRQ HLDAK ASTB INT INTAK µ PD71059 RD WR D0-D7 IORD IOWR CS MRD MWR HLDRQ HLDAK AEN ASTB Decoder D0-D7 OE STB µ PD71082 A16-A19 STB OE A16-A19 A16D8-A23D15 AD8-AD15 µ PD71082×3 A0-A15 AD0-AD7 UBE BUF R/W BUFEN D8-D15 UBE A0-A15 µ PD71086×2 T OE D0-D7 RD WR CS UBE D0-D7 D8-D15 Memory µPD72107 µPD72107 5. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 A 32 K J I L H G NOTES F D C N M B M R ITEM MILLIMETERS 58.0 +0.68 –0.20 1.78 MAX. 1.778 (T.P.) 0.50±0.10 0.9 MIN. 3.2±0.3 0.51 MIN. 4.05 +0.26 –0.20 5.08 MAX. 19.05 (T.P.) 17.0±0.2 0.25 +0.10 –0.05 0.17 0 to 15 ° INCHES 2.283 +0.028 –0.008 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 –0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.159 +0.011 –0.008 0.200 MAX. 0.750 (T.P.) 0.669 +0.009 –0.008 0.010 +0.004 –0.003 0.007 0 to 15 ° P64C-70-750A,C-3 1. Controlling dimension millimeter. A B C D F G H I J K L M N R 2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 3. Item "K" to center of leads when formed parallel. 25 µPD72107 80 PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end CD S Q R 80 1 21 20 F G H P I M J K M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 –0.05 0.10 2.7±0.1 0.1±0.1 5 ° ±5 ° 3.0 MAX. INCHES 0.677±0.016 0.551 +0.009 –0.008 0.551 +0.009 –0.008 0.677±0.016 0.032 0.032 0.012 +0.004 –0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 –0.008 0.006 +0.004 –0.003 0.004 0.106 +0.005 –0.004 0.004±0.004 5 ° ±5 ° 0.119 MAX. S80GC-65-3B9-5 26 µPD72107 68 PIN PLASTIC QFJ (950 x 950 mil) A B 68 1 CD G H J F E U K M N P M S Q S T ITEM A B C D MILLIMETERS 25.2 ± 0.2 24.20 ± 0.1 24.20 ± 0.1 25.2 ± 0.2 1.94 ± 0.15 0.6 4.4 ± 0.2 2.8 ± 0.2 0.9 MIN. 3.4 ± 0.1 1.27 (T.P.) 0.42 ± 0.08 0.12 23.12 ± 0.2 0.15 R 0.8 0.22 + 0.08 − 0.07 INCHES 0.992 ± 0.008 0.953 + 0.004 − 0.005 0.953 + 0.004 − 0.005 0.992 ± 0.008 0.076 + 0.007 − 0.006 0.024 0.173 + 0.009 − 0.008 0.110 + 0.009 − 0.008 0.035 MIN. 0.134 + 0.004 − 0.005 0.050 (T.P.) 0.017 + 0.003 − 0.004 0.005 0.910 + 0.009 − 0.008 0.006 R 0.031 0.009 + 0.003 − 0.004 P68L-50A1-3 I NOTES 1. Controlling dimension millimeter. E F 2. Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. G H I J K M N P Q T U 27 µPD72107 6. RECOMMENDED SOLDERING CONDITIONS The µ PD72107 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Surface mounting type • µ PD72107GC-3B9: 80-pin plastic QFP (14 × 14 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 ° C, Time: 30 sec. Max. (at 210° C or higher), Count: three times or less Package peak temperature: 215 ° C, Time: 40 sec. Max. (at 200° C or higher), Count: three times or less Solder bath temperature: 260° C, Time: 10 sec. Max., Count: one time, Preheating temperature: 120 ° C Max. (package surface temperature) Pin temperature: 300° C Max., Duration: 3 sec. Max. (per pin row) Recommended Condition Symbol IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Partial heating – Caution Do not use different soldering methods together (except for partial heating). • µ PD72107L: 68-pin plastic QFJ (950 × 950 mils) Soldering Method VPS Soldering Conditions Package peak temperature: 215 ° C, Time: 40 sec. Max. (at 200° C or higher), Count: one time Pin temperature: 300° C Max., Duration: 3 sec. Max. (per pin row) Recommended Condition Symbol VP15-00-1 Partial heating – Insertion type • µ PD72107CW: 64-pin plastic shrink DIP (750 mils) Soldering Method Wave soldering (pin only) Partial heating Soldering Conditions Solder bath temperature: 260° C Max., Time: 10 sec. Max. Pin temperature: 300° C Max., Duration: 3 sec. Max. (per a pin) Caution Wave soldering must be applied only to pins. Be sure to avoid jet soldering the package body. 28 µPD72107 [MEMO] 29 µPD72107 [MEMO] 30 µPD72107 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 31 µPD72107 The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2