UPD75P3216GT

DATA SHEET MOS INTEGRATED CIRCUIT µPD75P3216 4-BIT SINGLE-CHIP MICROCONTROLLER The µPD75P3216 replaces the µPD753208’s internal mask ROM with a one-time PROM, and features expanded ROM capacity. Because the µPD75P3216 supports programming by users, it is suitable for use in prototype testing for system development using the µPD753204, 753206, or 753208, and for use in small-lot production. The functions are explained in detail in the following user’s manual. Be sure to read this manual when designing your system. µPD753208 User’s Manual: U10158E FEATURES • Compatible with µPD753208 • Memory capacity: • PROM : 16384 × 8 bits • RAM : 512 × 4 bits • Can operate in same power supply voltage range as the mask version µPD753208 • VDD = 1.8 to 5.5 V • LCD controller/driver ORDERING INFORMATION Part Number Package 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch) µPD75P3216GT Caution Mask-option pull-up resistors are not provided in this device. The information in this document is subject to change without notice. Document No. U10241EJ1V0DS00 (1st edition) Date Published January 1997 N Printed in Japan The mark shows major revised points. '© 1995 1997 µPD75P3216 FUNCTION OUTLINE Parameter Instruction execution time Function • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation with system clock) • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation with system clock) 16384 × 8 bits 512 × 4 bits • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks 6 20 Connecting on-chip pull-up resistors can be specified by software: 5 Connecting on-chip pull-up resistors can be specified by software: 20 Also used for segment pins: 8 13-V withstand Internal memory PROM RAM General-purpose register Input/ output port CMOS input CMOS input/output N-ch open-drain I/O Total LCD controller/driver 4 30 • Segment selection: • Display mode selection: 4/8/12 segments (can be changed to CMOS input/ output port in 4-time units; max. 8) Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) Timer 5 channels • 8-bit timer/event counter: 1 channel • 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier generator, timer with gate) • Basic interval timer/watchdog timer: 1 channel • Watch timer: 1 channel • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit • 2-wire serial I/O mode • SBI mode Serial interface Bit sequential buffer (BSB) Clock output (PCL) 16 bits • Φ , 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock) • Φ , 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock) • 2, 4, 32 kHz (@ 4.19-MHz operation with system clock) • 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock) External: 2, Internal: 5 External: 1, Internal: 1 Ceramic or crystal oscillator for system clock oscillation STOP/HALT mode VDD = 1.8 to 5.5 V 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch) Buzzer output (BUZ) Vectored interrupts Test input System clock oscillator Standby function Power supply voltage Package 2 µPD75P3216 CONTENTS 1. PIN CONFIGURATION (Top View) .................................................................................................... 4 2. BLOCK DIAGRAM .............................................................................................................................. 5 3. PIN FUNCTIONS ................................................................................................................................. 6 3.1 3.2 3.3 3.4 Port Pins ...................................................................................................................................................... 6 Non-port Pins .............................................................................................................................................. 7 Equivalent Circuits for Pins ...................................................................................................................... 8 Recommended Connection of Unused Pins ........................................................................................ 10 4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................ 11 4.1 4.2 Difference between Mk I Mode and Mk II Mode ................................................................................... 11 Setting of Stack Bank Selection (SBS) Register ................................................................................. 12 5. Differences between µPD75P3216 and µPD753204, 753206, and 753208 ................................13 6. MEMORY CONFIGURATION ........................................................................................................... 14 7. INSTRUCTION SET ........................................................................................................................... 16 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................. 25 8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ........................................................................... 25 Program Memory Write Procedure ........................................................................................................ 26 Program Memory Read Procedure ........................................................................................................ 27 One-time PROM Screening ..................................................................................................................... 28 9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 29 10. CHARACTERISTIC CURVE (REFERENCE VALUE) ...................................................................... 42 11. PACKAGE DRAWINGS .................................................................................................................... 44 12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 45 APPENDIX A. µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST ........................................... 46 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 48 APPENDIX C. RELATED DOCUMENTS ............................................................................................... 52 3 µPD75P3216 1. PIN CONFIGURATION (Top View) • 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch) µPD75P3216GT COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2 P33/MD3 VSS P50/D4 P51/D5 P52/D6 P53/D7 P60/KR0/D0 P61/KR1/D1 P62/KR2/D2 P63/KR3/D3 VDD X1 X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 S12 S13 S14 S15 P93/S16 P92/S17 P91/S18 P90/S19 P83/S20 P82/S21 P81/S22 P80/S23 P23 P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P10/INT0 P03/SI/SB1 P02/SO/SB0 P01/SCK P00/INT4 RESET VPPNote Note Be sure to connect VPP to VDD directly in normal operation mode. PIN IDENTIFICATIONS BIAS BUZ D0-D7 INT0, INT4 KR0-KR3 LCDCL MD0-MD3 P00-P03 P10, P13 P20-P23 P30-P33 P50-P53 P60-P63 P80-P83 P90-P93 : LCD Power Supply Bias Control : Buzzer Clock : Data Bus 0 to 7 : External Vectored Interrupt 0, 4 : Key Return 0 to 3 : LCD Clock : Mode Selection 0 to 3 : Port0 : Port1 : Port2 : Port3 : Port5 : Port6 : Port8 : Port9 PCL RESET S12-S23 SB0, SB1 SCK SI SO SYNC TI0 VDD VLC0-VLC2 VPP VSS X1, X2 : Programmable Clock : Reset Input : Segment Output 12 to 23 : Serial Bus 0, 1 : Serial Clock : Serial Input : Serial Output : LCD Synchronization : Timer Input 0 : Positive Power Supply : LCD Power Supply 0 to 2 : Programming Power Supply : Ground : System Clock Oscillation 1, 2 PTO0-PTO2 : Programmable Timer Output 0 to 2 COM0-COM3 : Common Output 0 to 3 4 µPD75P3216 2. BLOCK DIAGRAM BUZ/P23 WATCH TIMER INTW fLCD BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT PORT0 4 P00-P03 PROGRAM COUNTER ALU SP (8) CY SBS PORT1 2 P10, P13 PORT2 4 P20-P23 P30/MD0P33/MD3 P50/D4P53/D7 P60/D0P63/D3 P80-P83 TI0/P13 PTO0/P20 8-BIT TIMER/EVENT COUNTER #0 INTT0 TOUT BANK PORT3 4 PORT5 GENERAL REG. PROM PROGRAM MEMORY 16384 × 8 BITS 4 PTO1/P21 TOUT PTO2/ PCL/P22 INTT1 8-BIT TIMER CASCADED COUNTER #1 16-BIT TIMER 8-BIT COUNTER TIMER COUNTER #2 INTT2 PORT6 4 DECODE AND CONTROL PORT8 DATA MEMORY (RAM) 512 × 4 BITS 4 PORT9 4 P90-P93 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT 4 S12-S15 S16/P93S19/P90 S20/P83S23/P80 COM0-COM3 VLC0 VLC1 VLC2 BIAS LCDCL/P30 SYNC/P31 4 LCD CONTROLLER/ DRIVER fx/2 N CLOCK CLOCK OUTPUT DIVIDER CONTROL CPU CLOCK Φ SYSTEM CLOCK GENERATOR STANDBY CONTROL fLCD 4 INT0/P10 INT4/P00 KR0/P60KR3/P63 4 BIT SEQ. BUFFER (16) INTERRUPT CONTROL 4 PCL/PTO2/P22 X1 X2 Vpp VDD VSS RESET 5 µPD75P3216 3. PIN FUNCTIONS 3.1 Port Pins 8-bit I/O × Status I/O Circuit After Reset TypeNote 1 Input -A -B -C This is a 1-bit input port (PORT1). These are 1-bit pins for which an internal pull-up resistor can be connected by software. P10/INT0 can select noise elimination circuit. This is a 4-bit I/O port (PORT2). These are 4-bit pins for which an internal pull-up resistor can be connected by software. × Input -C Pin Name P00 P01 P02 P03 P10 I/O Input I/O I/O I/O Input Shared by INT4 SCK SO/SB0 SI/SB1 INT0 Function This is a 4-bit input port (PORT0). P01 to P03 are 3-bit pins for which an internal pull-up resistor can be connected by software. P13 TI0 P20 P21 P22 P23 P30 P31 P32 P33 P50Note 2 P51Note 2 P52Note 2 P53Note 2 P60 P61 P62 P63 P80 P81 P82 P83 P90 P91 P92 P93 I/O PTO0 PTO1 PCL/PTO2 BUZ × Input E-B I/O LCDCL/MD0 SYNC/MD1 MD2 MD3 This is a programmable 4-bit I/O port (PORT3). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor can be connected by software. × Input E-B I/O D4 D5 D6 D7 This is an N-ch open-drain 4-bit I/O port (PORT5). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (upper 4 bits) for program memory (PROM) write/verify. × High impedance M-E I/O KR0/D0 KR1/D1 KR2/D2 KR3/D3 This is a programmable 4-bit I/O port (PORT6). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor can be connected by software. Also functions as data I/O pin (lower 4 bits) for program memory (PROM) write/verify. This is a 4-bit I/O port (PORT8). When set for 4-bit units, an internal pull-up resistor can be connected by software. × Input -A I/O S23 S22 S21 S20 Input H I/O S19 S18 S17 S16 This is a programmable 4-bit I/O port (PORT9). When set for 4-bit units, an internal pull-up resistor can be connected by software. Input H Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits. 2. Low level input current leakage increases when input instructions or bit manipulation instructions are executed. 6 µPD75P3216 3.2 Non-port Pins Status I/O Circuit After Reset TypeNote 1 Input Input -C E-B Pin Name TI0 PTO0 PTO1 PTO2 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 I/O Input Shared by P13 Function External event pulse input to timer/event counter Timer/event counter output Timer counter output Output P20 P21 P22/PCL P22/PTO2 P23 I/O P01 P02 P03 Input Input P00 P10 Clock output Any frequency output (for buzzer or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge detection vectored interrupt input (detecting both rising and falling edges) Edge detection vectored interrupt input (detected edge is selectable). INT0/P10 can select noise elimination circuit Falling edge detection testable input Ceramic/crystal oscillation circuit connection for system clock. If using an external clock, input to X1 and input inverted phase to X2. System reset input Mode selection for program memory (PROM) write/verify Data bus pin for program memory (PROM) write/verify. Noise elimination circuit/asynch is selectable Input Input Input -A -B -C -C KR0 to KR3 X1 X2 RESET MD0 to MD3 D0 to D3 D4 to D7 VPP Input Input — Input Input I/O P60/D0-P63/D3 — Input — -A — — P30 to P33 P60/KR0-P63/KR3 P50 to P53 — Input Input -A -A M-E — — Programmable power supply voltage for program memory (PROM) write/verify. For normal operation, connect directly to VDD. Apply +12.5 V for PROM write/verify. Positive power supply Ground Segment signal output Segment signal output — — VDD VSS S12 to S15 S16 to S19 S20 to S23 — — Output — — — — — Note 2 Input — — G-A H Output P93 to P90 P83 to P80 — — — COM0 to COM3 Output VLC0 to VLC2 BIAS LCDCLNote 4 SYNCNote 4 — Output Common signal output Power source for LCD drive Output for external split resistor cut Clock output for driving external expansion driver Clock output for synchronization of external expansion driver Note 2 — Note 3 Input G-B — — E-B Output P30/MD0 P31/MD1 Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits. 2. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs. S12 to S15: VLC1, COM1 to COM2: VLC2, COM3: VLC0 3. When the split resistor is incorporated : Low level When the split resistor is not incorporated : High impedance 4. These pins are provided for future system expansion. Currently, only P30 and P31 are used. 7 µPD75P3216 3.3 Equivalent Circuits for Pins The equivalent circuits for the µPD75P3216’s pins are shown in abbreviated form below. TYPE A VDD Data P-ch IN Output disable N-ch TYPE D VDD P-ch OUT N-ch CMOS standard input buffer Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch TYPE B IN Data Type D Output disable IN/OUT Type A Schmitt trigger input with hysteresis characteristics. P.U.R. : Pull-Up Resistor TYPE B-C TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable Data Type D Output disable IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor P.U.R. P-ch P-ch IN/OUT (Continued) 8 µPD75P3216 (Continued) TYPE F-B VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch Data Output disable Type E-B VDD P-ch IN/OUT P-ch SEG data Type G-A IN/OUT TYPE H P.U.R. : Pull-Up Resistor TYPE G-A TYPE M-C VDD VLC0 P.U.R. VLC1 P-ch N-ch P.U.R. enable P-ch IN/OUT OUT SEG data VLC2 N-ch Data Output disable N-ch N-ch P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-E IN/OUT VLC0 VLC1 P-ch N-ch data output disable VDD input instruction OUT P-ch P.U.R.Note N-ch P-ch N-ch (+13 V) COM data VLC2 N-ch Voltage control circuit (+13 V) Note This pull-up resistor is effective only when an input instruction is executed (when the pin level is low, current flows from VDD to the pin). 9 µPD75P3216 3.4 Recommended Connection of Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/MD0/LCDCL P31/MD1/SYNC P32/MD2 P33/MD3 P50/D4 to P53/D7 Connect to Vss Connect to Vss Recommended Connection Connect to Vss or VDD Connect to Vss or VDD through a resistor individually Connect to Vss or VDD Input status : connect to Vss or VDD through a resistor individually Output status: open P60/KR0/D0 to P63/KR3/D3 Input status : connect to Vss or VDD through a resistor individually Output status: open S12 to S15 COM0 to COM3 S16/P93 to S19/P90 S20/P83 to S23/P80 VLC0 to VLC2 BIAS Input status : connect to Vss or VDD through a resistor individually Output status: open Connect to Vss Connect to Vss only when VLC0 to VLC2 are all not used. In other cases, leave open. VPP Be sure to connect VDD directly. Open 10 µPD75P3216 4. Mk I AND Mk II MODE SELECTION FUNCTION Setting a stack bank selection (SBS) register for the µPD75P3216 enables the program memory to be switched between Mk I mode and Mk II mode. This function is applicable when using the µPD75P3216 to evaluate the µPD753204, 753206, or 753208. When the SBS bit 3 is set to 1: sets Mk I mode (supports Mk I mode for µPD753204, 753206, and 753208) When the SBS bit 3 is set to 0: sets Mk II mode (supports Mk II mode for µPD753204, 753206, and 753208) 4.1 Difference between Mk I Mode and Mk II Mode Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3216. Table 4-1. Difference between Mk I Mode and Mk II Mode Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank No. of stack bytes Instruction BRA !addr1 instruction CALLA !addr1 instruction Instruction CALL !addr instruction execution time CALLF !faddr instruction Supported mask ROMs 3 machine cycles 2 machine cycles When set to Mk I mode: µPD753204, 753206, and 753208 4 machine cycles 3 machine cycles When set to Mk II mode: µPD753204, 753206, and 753208 PC13-0 16384 512 × 4 Selectable via memory banks 0, 1 2 bytes None 3 bytes Provided Mk I Mode Mk II Mode Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode. 11 µPD75P3216 4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 100XBNote at the beginning of the program. When using the Mk II mode, be sure to initialize it to 000XBNote. Note Set the desired value for X. Figure 4-1. Format of Stack Bank Selection Register Address F84H 3 SBS3 2 SBS2 1 SBS1 0 SBS0 Symbol SBS Stack area specification 0 0 1 1 0 1 0 Setting prohibited 1 Memory bank 0 Memory bank 1 0 Be sure to enter “0” for bit 2. Mode selection specification 0 1 Mk II mode Mk I mode Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in Mk I mode. When using instructions for Mk II mode, set SBS3 to “0” and set Mk II mode before using the instructions. 2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register. 12 µPD75P3216 5. DIFFERENCES BETWEEN µPD75P3216 AND µPD753204, 753206, AND 753208 The µPD75P3216 replaces the internal mask ROM in the µPD753204, 753206, and 753208 with a one-time PROM and features expanded ROM capacity. The µPD75P3216’s Mk I mode supports the Mk I mode in the µPD753204, 753206, and 753208 and the µPD75P3216’s Mk II mode supports the Mk II mode in the µPD753204, 753206, and 753208. Table 5-1 lists differences among the µPD75P3216 and the µPD753204, 753206, and 753208. Be sure to check the differences among these products before using them with PROMs for debugging or prototype testing of application systems or, later, when using them with a mask ROM for full-scale production. For details on the CPU functions and internal hardware, refer to µPD753208 User’s Manual (U10158E). Table 5-1. Differences between µPD75P3216 and µPD753204, 753206, and 753208 Item Program counter Program memory (bytes) Data memory (× 4 bits) Mask options Pull-up resistor for port 5 Waiting time in RESET Pin configuration Pin 9 to 12 Pin 14 to 17 Pin 18 to 20 µPD753204 12 bits Mask ROM 4096 512 Yes (specifiable) µPD753206 13 bits Mask ROM 6144 µPD753208 µPD75P3216 14 bits Mask ROM 8192 One-time PROM 16384 No (off chip) Yes (selectable from 217/fX and 215/fX)Note No (Fixed to 215/fX ms) P30/MD0-P33/MD3 P50/D4-P53/D7 P60/KR0/D0P63/KR3/D3 VPP P30 to P33 P50 to P53 P60/KR0 to P63/KR3 Pin 25 Other IC Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. Note 217/fX = 21.8 ms (@6.0 MHz), 31.3 ms (@4.19 MHz) 215/fX = 5.46 ms (@6.0 MHz), 7.81 ms (@4.19 MHz) Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask ROM versions from the PROM version in a process between prototype development and full production, be sure to fully evaluate the mask ROM version’s CS (not ES). 13 µPD75P3216 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map 7 0000H MBE 6 RBE 5 0 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) CALLF !faddr instruction entry address 0004H MBE RBE INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H BRCB !caddr instruction branch address Branch addresses for the following instructions • BR !addr • CALL !addr • BRA !addr1 Note • CALLA !addr1Note • MOVT BCDE • MOVT BCXA Branch/call address by GETI Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH BR $addr instruction relative branch address (–15 to –1, +2 to +16) 0008H MBE RBE INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE RBE INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTT1/INTT2 start address (upper 6 bits) INTT1/INTT2 start address (lower 8 bits) 0020H BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address Note Can be used only in Mk II mode. Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC’s lower 8 bits only. 14 µPD75P3216 Figure 6-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H (32 × 4) Memory bank 0 256 × 4 (224 × 4) Stack area Note Data area static RAM (512 × 4) 0FFH 100H 256 × 4 (236 × 4) 1EBH 1ECH (12 × 4) 1F7H 1F8H (8 × 4) 1FFH 1 Display data memory (12 × 4) Not incorporated F80H Peripheral hardware area 128 × 4 15 FFFH Note Memory bank 0 or 1 can be selected as the stack area. 15 µPD75P3216 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, refer to RA75X Assembler Package User’s Manual –Language (EEU-1343)). When there are several codes, select and use just one. Codes that consist of upper-case letters and + or – symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer to µPD753208 User’s Manual (U10158E)). The number of labels that can be entered for fmem and pmem are restricted. Representation reg reg1 rp rp1 rp2 rp’ rp’1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE Coding Format XA, BC, DE, HL, XA’, BC’, DE’, HL’ BC, DE, HL, XA’, BC’, DE’, HL’ HL, HL+, HL–, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label 0000H to 3FFFH immediate data or label 0000H to 3FFFH immediate data or label (Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9 IEBT, IECSI, IET0, IET1, IET2, IE0, IE2, IE4, IEW RB0 to RB3 MB0, MB1, MB15 Note When processing 8-bit data, only even-numbered addresses can be specified. 16 µPD75P3216 (2) Operation legend A B C D E H L X XA BC DE HL XA’ BC’ DE’ HL’ PC SP CY PSW MBE RBE IME IPS IEXXX RBS MBS PCC . (XX) XXH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA’) : Expansion register pair (BC’) : Expansion register pair (DE’) : Expansion register pair (HL’) : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Delimiter for address and bit : Addressed data : Hexadecimal data PORTn : Port n (n = 0 to 3, 5, 6, 8, 9) 17 µPD75P3216 (3) Description of symbols used in addressing area MB = MBE • MBS *1 MBS = 0, 1, 15 *2 MB = 0 MBE = 0 *3 MBE = 1 : MB = MBS MBS = 0, 1, 15 *4 *5 *6 *7 (Current PC) +2 to (Current PC) +16 caddr = 0000H to 0FFFH (PC13, 12 = 00B) or 1000H to 1FFFH (PC13, 12 = 01B) or *8 2000H to 2FFFH (PC13, 12 = 10B) or 3000H to 3FFFH (PC13, 12 = 11B) *9 *10 *11 faddr = 0000H to 07FFH taddr = 0020H to 007FH addr1 = 0000H to 3FFFH (Mk II mode only) Program memory addressing MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3FFFH addr, addr1 = (Current PC) – 15 to (Current PC) – 1 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) Data memory addressing Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. • No skip .................................................................... S = 0 • Skipped instruction is 1-byte or 2-byte instruction .. S = 1 • Skipped instruction is 3-byte instructionNote ........... S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock F. Use the PCC setting to select among four cycle times. 18 µPD75P3216 Instruction Group Transfer No. of Machine Bytes Cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A←n4 reg1←n4 XA←n8 HL←n8 rp2←n8 A←(HL) A←(HL), then L←L+1 A←(HL), then L←L–1 A←(rpa1) XA←(HL) (HL)←A (HL)←XA A←(mem) XA←(mem) (mem)←A (mem)←XA A←reg XA←rp’ reg1←A rp’1←XA A↔(HL) A↔(HL), then L←L+1 A↔(HL), then L←L–1 A↔(rpa1) XA↔(HL) A↔(mem) XA↔(mem) A↔reg1 XA↔rp’ XA←(PC13-8+DE)ROM XA←(PC13-8+XA)ROM XA←(B2-0+BCDE)ROM XA←(B2-0+BCXA)ROM *6 *6 *1 *1 *1 *2 *1 *3 *3 L=0 L=FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L=FH String-effect A String-effect B Addressing Area Skip Condition String-effect A Mnemonic MOV Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp’ reg1, A rp’1, XA Operation XCH A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp’ Table reference MOVT XA, @PCDE XA, @PCXA XA, @BCDENote XA, @BCXANote Note Only the lower 2 bits in the B register are valid. 19 µPD75P3216 Instruction Group Bit transfer No. of Machine Bytes Cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S Addressing Area *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1 Skip Condition Mnemonic MOV1 Operand CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation CY←(fmem.bit) CY←(pmem7-2+L3-2.bit(L1-0)) CY←(H+mem3-0.bit) (fmem.bit)←CY (pmem7-2+L3-2.bit(L1-0))←CY (H+mem3-0.bit)←CY A←A+n4 XA←XA+n8 A←A+(HL) XA←XA+rp’ rp’1←rp’1+XA A, CY←A+(HL)+CY XA, CY←XA+rp’+CY rp’1, CY←rp’1+XA+CY A←A–(HL) XA←XA–rp’ rp’1←rp’1–XA A, CY←A–(HL)–CY XA, CY←XA–rp’–CY rp’1, CY←rp’1–XA–CY A←A∧n4 A←A∧(HL) XA←XA∧rp’ rp’1←rp’1∧XA A←A∨n4 A←A∨(HL) XA←XA∨rp’ rp’1←rp’1∨XA A←A∨n4 A←A∨(HL) XA←XA∨rp’ rp’1←rp’1∨XA CY←A0, A3←CY, An-1←An A ←A reg←reg+1 rp1←rp1+1 (HL)←(HL)+1 (mem)←(mem)+1 reg←reg–1 rp’←rp’–1 Arithmetic ADDS A, #n4 XA, #n8 A, @HL XA, rp’ rp’1, XA ADDC A, @HL XA, rp’ rp’1, XA SUBS A, @HL XA, rp’ rp’1, XA *1 borrow borrow borrow SUBC A, @HL XA, rp’ rp’1, XA *1 AND A, #n4 A, @HL XA, rp’ rp’1, XA *1 OR A, #n4 A, @HL XA, rp’ rp’1, XA *1 XOR A, #n4 A, @HL XA, rp’ rp’1, XA *1 Accumulator manipulation Increment/ decrement RORC NOT INCS A A reg rp1 @HL mem reg=0 rp1=00H *1 *3 (HL)=0 (mem)=0 reg=FH rp’=FFH DECS reg rp’ 20 µPD75P3216 Instruction Group Comparison No. of Machine Bytes Cycle 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Skip if reg=n4 Skip if(HL)=n4 Skip if A=(HL) Skip if XA=(HL) Skip if A=reg Skip if XA=rp’ CY←1 CY←0 Skip if CY=1 CY←CY (mem.bit)←1 (fmem.bit)←1 (pmem7-2+L3-2.bit(L1-0))←1 (H+mem3-0.bit)←1 (mem.bit)←0 (fmem.bit)←0 (pmem7-2+L3-2.bit(L1-0))←0 (H+mem3-0.bit)←0 Skip if(mem.bit)=1 Skip if(fmem.bit)=1 Skip if(pmem7-2+L3-2.bit(L1-0))=1 Skip if(H+mem3-0.bit)=1 Skip if(mem.bit)=0 Skip if(fmem.bit)=0 Skip if(pmem7-2+L3-2.bit(L1-0))=0 Skip if(H+mem3-0.bit)=0 Skip if(fmem.bit)=1 and clear Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear Skip if(H+mem3-0.bit)=1 and clear CY←CY∧(fmem.bit) CY←CY∧(pmem7-2+L3-2.bit(L1-0)) CY←CY∧(H+mem3-0.bit) CY←CY∨(fmem.bit) CY←CY∨(pmem7-2+L3-2.bit(L1-0)) CY←CY∨(H+mem3-0.bit) CY←CY∨ (fmem.bit) CY←CY∨(pmem7-2+L3-2.bit(L1-0)) CY←CY∨(H+mem3-0.bit) *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 CY=1 *1 *1 *1 Addressing Area Skip Condition reg=n4 (HL)=n4 A=(HL) XA=(HL) A=reg XA=rp’ Mnemonic SKE Operand reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp’ Operation Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit Memory bit manipulation SET1 CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit 21 µPD75P3216 Instruction Group Branch No. of Machine Bytes Cycle — — Addressing Area *6 Skip Condition Mnemonic BRNote Operand addr Operation PC13-0←addr Use the assembler to select the most appropriate instruction among the following. • BR !addr • BRCB !caddr • BR $addr PC13-0←addr1 Use the assembler to select the most appropriate instruction among the following. • BRA !addr1 • BR !addr • BRCB !caddr • BR $addr1 PC13-0←addr PC13-0←addr PC13-0←addr1 PC13-0←PC13-8+DE PC13-0←PC13-8+XA PC13-0←BCDE PC13-0←BCXA PC13-0←addr1 PC13-0←PC13, 12+caddr11-0 addr1 — — *11 !addr $addr $addr1 PCDE PCXA BCDE BCXA BRANote BRCB !addr1 !caddr 3 1 1 2 2 2 2 3 2 3 2 2 3 3 3 3 3 2 *6 *7 *6 *6 *11 *8 Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 22 µPD75P3216 Instruction Group Subroutine stack control No. of Machine Bytes Cycle 3 3 Addressing Area Skip Condition Mnemonic Operand Operation (SP–6)(SP–3)(SP–4)←PC11-0 (SP–5)←0, 0, PC13, 12 (SP–2)←X, X, MBE, RBE PC13–0←addr1, SP←SP–6 (SP–4)(SP–1)(SP–2)←PC11-0 (SP–3)←MBE, RBE, PC13, 12 PC13–0←addr, SP←SP–4 (SP–6)(SP–3)(SP–4)←PC11-0 (SP–5)←0, 0, PC13, 12 (SP–2)←X, X, MBE, RBE PC13-0←addr, SP←SP–6 (SP–4)(SP–1)(SP–2)←PC11-0 (SP–3)←MBE, RBE, PC13, 12 PC13-0←000+faddr, SP←SP–4 (SP–6)(SP–3)(SP–4)←PC11-0 (SP–5)←0, 0, PC13, 12 (SP–2)←X, X, MBE, RBE PC13-0←000+faddr, SP←SP–6 MBE, RBE, PC13, 12←(SP+1) PC11-0←(SP)(SP+3)(SP+2) SP←SP+4 X, X, MBE, RBE←(SP+4) PC11-0←(SP)(SP+3)(SP+2) MBE, 0, PC13, 12←(SP+1) SP←SP+6 CALLANote !addr1 CALLNote !addr 3 3 *6 4 CALLFNote !faddr 2 2 *9 3 RETNote 1 3 RETSNote 1 3+S MBE, RBE, PC13, 12←(SP+1) PC11-0←(SP)(SP+3)(SP+2) SP←SP+4 then skip unconditionally X, X, MBE, RBE←(SP+4) PC11-0←(SP)(SP+3)(SP+2) 0, 0, PC13, 12←(SP+1) SP←SP+6 then skip unconditionally Unconditional RETINote 1 3 MBE, RBE, PC13, 12←(SP+1) PC11-0←(SP)(SP+3)(SP+2) PSW←(SP+4)(SP+5), SP←SP+6 0, 0, PC13, 12←(SP+1) PC11-0←(SP)(SP+3)(SP+2) PSW←(SP+4)(SP+5), SP←SP+6 PUSH rp BS 1 2 1 2 1 2 1 2 (SP–1)(SP–2)←rp, SP←SP–2 (SP–1)←MBS, (SP–2)←RBS, SP←SP–2 rp←(SP+1)(SP), SP←SP+2 MBS←(SP+1), RBS←(SP), SP←SP+2 POP rp BS Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 23 µPD75P3216 Instruction Group Interrupt control No. of Machine Bytes Cycle 2 IEXXX DI IEXXX I/O INNote 1 A, PORTn XA, PORTn OUTNote 1 PORTn, A PORTn, XA CPU control HALT STOP NOP Special SEL RBn MBn GETINote 2, 3 taddr 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 2 2 2 2 2 2 2 2 1 2 2 3 IME(IPS.3)←1 IEXXX←1 IME(IPS.3)←0 IEXXX←0 A←PORTn (n=0-3, 5, 6, 8, 9) Addressing Area Skip Condition Mnemonic EI Operand Operation XA←PORTn+1, PORTn(n=8) PORTn←A (n=2-3, 5, 6, 8, 9) PORTn+1, PORTn←XA(n=8) Set HALT Mode(PCC.2←1) Set STOP Mode(PCC.3←1) No Operation RBS←n (n=0-3) MBS←n (n=0, 1, 15) • When using TBR instruction *10 --------------------------• When using TCALL instruction (SP–4)(SP–1)(SP–2)←PC11-0 (SP+1)←MBE, RBE, PC13, 12 PC13-0←(taddr)5-0+(taddr+1) PC13-0←(taddr)5-0+(taddr+1) ------------ --------------------------• When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions 1 3 • When using TBR instruction PC13-0←(taddr)5-0+(taddr+1) *10 SP←SP–4 -----------Determined by referenced instruction -------------------------------4 • When using TCALL instruction (SP–6)(SP–3)(SP–4)←PC11-0 (SP–2)←X, X, MBE, RBE PC13-0←(taddr)5-0+(taddr+1) ------------ -------------------------------3 • When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions SP←SP–6 -----------Determined by referenced instruction Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBE to 15. 2. TBR and TCALL instructions are assembler directives for the GETI instruction’s table definitions. 3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 24 µPD75P3216 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory contained in the µPD75P3216 is a 16384 × 8-bit one-time PROM that can be electrically written one time only. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses. Pin VPP Function Pin where program voltage is applied during program memory write/verify (usually VDD potential) Clock input pins for address updating during program memory write/verify. Input the X1 pin’s inverted signal to the X2 pin. Operation mode selection pin for program memory write/ verify 8-bit data I/O pins for program memory write/verify X1, X2 MD0 to MD3 D0/P60/KR0-D3/P63/KR3 (lower 4 bits) D4/P50-D7/P53 (upper 4 bits) VDD Pin where power supply voltage is applied. Applies 1.8 to 5.5 V in normal operation mode and +6 V for program memory write/verify. Caution Pins not used for program memory write/verify should be connected to Vss. 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P3216 enters the program memory write/ verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation Mode Specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L X MD2 H H H H MD3 L H H H Operation Mode Zero-clear program memory address Write mode Verify mode Program inhibit mode X: L or H 25 µPD75P3216 8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull down unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Write data in the 1 ms write mode. (7) Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7). (8) (X : number of write operations from steps (6) and (7)) × 1 ms additional write. (9) Apply four pulses to the X1 pin to increment the program memory address by one. (10) Repeat steps (6) to (9) until the end address is reached. (11) Select the zero-clear program memory address mode. (12) Return the VDD and VPP pins back to 5 V. (13) Turn off the power. The following figure shows steps (2) to (9). X repetitions Write VPP VPP VDD Verify Additional write Address increment VDD + 1 VDD VDD X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 MD0/P30 Data input Data output Data input MD1/P31 MD2/P32 MD3/P33 26 µPD75P3216 8.3 Program Memory Read Procedure The µPD75P3216 can read program memory contents using the following procedure. (1) Pull down unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (7) Select the zero-clear program memory address mode. (8) Return the VDD and VPP pins back to 5 V. (9) Turn off the power. The following figure shows steps (2) to (9). VPP VPP VDD VDD + 1 VDD VDD X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 MD0/P30 Data output Data output MD1/P31 “L” MD2/P32 MD3/P33 27 µPD75P3216 8.4 One-time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening. Storage Temperature 125 ˚C Storage Time 24 hours 28 µPD75P3216 9. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C) Parameter Supply voltage PROM supply voltage Input voltage Symbol V DD V PP V I1 V I2 Output voltage Output current, high VO IOH Per pin Total for all pins Output current, low IOL Per pin Total for all pins Operating ambient temperature Storage temperature T stg –65 to +150 ˚C TA Except port 5 Port 5 N-ch open-drain Test Conditions Rating –0.3 to +7.0 –0.3 to +13.5 –0.3 to VDD + 0.3 –0.3 to +14 –0.3 to V DD + 0.3 –10 –30 30 220 –40 to +85Note Unit V V V V V mA mA mA mA ˚C Note When LCD is driven in normal mode: TA = –10 to +85 ˚C Caution Exposure to Absolute Maximum Ratings even for instant may affect device reliability; exceeding the ratings could cause parmanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. CAPACITANCE (TA = 25 ˚C, V DD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 29 µPD75P3216 SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Resonator Ceramic resonator C1 VDD C2 Recommended Constant X1 X2 Parameter Oscillator frequency (fx) Oscillation stabilization time Note 3 Note 1 Test Conditions MIN. 1.0 TYP. MAX. 6.0 Note 2 Unit MHz After VDD reaches oscillation voltage range MIN. 1.0 Note 1 4 ms Crystal resonator C1 X1 X2 Oscillator frequency (fx) C2 6.0 Note 2 MHz Oscillation stabilization time X1 input Note 3 VDD = 4.5 to 5.5 V 10 30 1.0 6.0 Note 2 ms VDD External clock X1 X2 MHz frequency (fx) Note 1 X1 input high/low level width (t XH, tXL) 83.3 500 ns Notes 1. 2. The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the instruction execution time, refer to the AC characteristics. When the oscillator frequency is 4.19 MHz < fx ≤ 6.0 MHz, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being less than the required 0.95 µs. Therefore, set PCC to a value other than 0011. 3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. Caution When using the system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS. • Do not ground it to the ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 30 µPD75P3216 DC CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Parameter Output current, low Symbol IOL Per pin Total for all pins Input voltage, high VIH1 Ports 2, 3, 8, 9 2.7 ≤ VDD ≤ 5.5 V 1.8 ≤ V DD < 2.7 V VIH2 Ports 0, 1, 6, RESET 2.7 ≤ VDD ≤ 5.5 V 1.8 ≤ V DD < 2.7 V VIH3 Port 5 N-ch open-drain 2.7 ≤ VDD ≤ 5.5 V 1.8 ≤ V DD < 2.7 V VI14 Input voltage, low VIL1 X1 Ports 2, 3, 5, 8, 9 2.7 ≤ VDD ≤ 5.5 V 1.8 ≤ V DD < 2.7 V VIL2 Ports 0, 1, 6, RESET 2.7 ≤ VDD ≤ 5.5 V 1.8 ≤ V DD < 2.7 V VIL3 Output voltage, high Output voltage, low VOH VOL1 X1 SCK, SO, ports 2, 3, 6, 8, 9 IOH = –1 mA SCK, SO, ports 2, 3, 5, 6, 8, 9 IOL = 15 mA, VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 Input leakage current, high ILIH1 ILIH2 ILIH3 Input leakage current, low ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V SB0, SB1 VIN = V DD N-ch open-drain pull-up resistor ≥ 1 kΩ Other pins than X1 X1 Port 5 (N-ch open-drain) Other pins than port 5 and X1 X1 Port 5 (N-ch open-drain) When an input instruction is not executed Port 5 (N-ch open-drain) When an input instruction is executed Output leakage current, high Output leakage current, low Pull-up resistor RL VIN = 0 V Ports 0, 1, 2, 3, 6, 8, 9 (Excluding P00 pin) 50 100 200 kΩ ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 13 V VOUT = 0 V SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9 Port 5 (N-ch open-drain) 3 20 –3 VDD = 5.0 V VDD = 3.0 V –10 –3 –27 –8 –30 0.4 0.2V DD 3 20 20 –3 –20 –3 V V 0.7V DD 0.9V DD 0.8V DD 0.9V DD 0.7V DD 0.9V DD VDD – 0.1 0 0 0 0 0 VDD – 0.5 0.2 2.0 Test Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD 13 13 VDD 0.3V DD 0.1V DD 0.2V DD 0.1V DD 0.1 Unit mA mA V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA µA 31 µPD75P3216 DC CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Parameter LCD drive voltage Symbol VLCD VAC0 = 0 Test Conditions T A = –40 to +85 °C T A = –10 to +85 °C VAC0 = 1 VAC current LCD output voltage deviation Note 1 MIN. 2.7 2.2 1.8 TYP. MAX. VDD VDD VDD Unit V V V IVAC VODC VAC0 = 1, V DD = 2.0 V ± 10% lo = ± 1 µA VLCD0 = VLCD VLCD1 = VLCD × 2/3 0 1 4 ± 0.2 µA V (common) VODS lo = ± 0.5 µA LCD output voltage deviation Note 1 VLCD2 = VLCD × 1/3 2.2 V ≤ VLCD ≤ V DD Note 1 Note 3 Note 4 0 ± 0.2 V (segment) Note 2 Supply current IDD1 6.0 MHz Crystal oscillation VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% HALT mode 2.6 0.47 0.72 0.27 1.9 0.36 0.7 0.23 0.05 0.02 7.8 1.4 2.1 0.8 5.7 1.1 2.0 0.7 10 5 3 mA mA mA mA mA mA mA mA IDD2 C1 = C2 = 22 pF VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% IDD1 4.19 MHz Crystal oscillation VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% HALT mode Note 3 Note 4 IDD2 C1 = C2 = 22 pF VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% IDD5 STOP mode Note 5 VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% TA = 25˚C µA µA µA 0.02 Notes 1. 2. 3. 4. 5. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). Not including current flowing in on-chip pull-up resistors. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. When PCC is set to 0000 and the device is operated in the low-speed mode. Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1 µA. 32 µPD75P3216 AC CHARACTERISTICS (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Parameter CPU clock cycle time Note 1 Symbol tCY VDD = 2.7 to 5.5 V Test Conditions MIN. 0.67 0.95 TYP. MAX. 64 64 1 275 Unit µs µs MHz kHz TI0 input frequency fTI VDD = 2.7 to 5.5 V 0 0 TI0 input high/low-level width Interrupt input high/ low-level width tTIH, t TIL VDD = 2.7 to 5.5 V 0.48 1.8 µs µs µs µs µs µs µs tINTH, t INTL INT0 IM02 = 0 IM02 = 1 Note 2 10 10 10 10 INT4 KR0 to KR3 RESET low level width tRSL Notes 1. The cycle time (minimum instruction execution time) of the CPU clock (Φ) is determined by the oscillation frequency of the connected resonator (and external clock) and (PCC). The figure at the right Cycle Time tCY [ µ s] tCY vs VDD 64 30 6 5 4 3 Guaranteed Operation Range the processor clock control register indicates the cycle time tCY versus supply voltage V DD characteristic. 2. 2t CY or 128/fx is set by setting the interrupt mode register (IM0). 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 33 µPD75P3216 SERIAL TRANSFER OPERATION 2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 Test Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high/low-level width SI Note 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns tKL1, t KH1 VDD = 2.7 to 5.5 V tKCY1/2–50 tKCY1/2–150 setup time tSIK1 VDD = 2.7 to 5.5 V 150 500 (to SCK↑) SI Note 1 hold time tKSI1 VDD = 2.7 to 5.5 V 400 600 (from SCK ↑) SO Note 1 output delay time tKSO1 RL = 1 kΩ, CL = 100 pF Note 2 VDD = 2.7 to 5.5 V 0 0 250 1000 ns ns from SCK↓ Notes 1. 2. In the 2-wire serial I/O mode, read SB0 or SB1 instead. RL and C L are the load resistance and load capacitance of the SO output lines. 2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 Test Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high/low-level width SINote 1 setup time (to SCK↑) SINote 1 hold time (from SCK ↑) SONote 1 output delay time from SCK ↓ tKSO2 RL = 1 kΩ, CL = 100 pF Note 2 TYP. MAX. Unit ns ns ns ns ns ns ns ns tKL2, t KH2 VDD = 2.7 to 5.5 V 400 1600 tSIK2 VDD = 2.7 to 5.5 V 100 150 tKSI2 VDD = 2.7 to 5.5 V 400 600 VDD = 2.7 to 5.5 V 0 0 300 1000 ns ns Notes 1. 2. In the 2-wire serial I/O mode, read SB0 or SB1 instead. RL and C L are the load resistance and load capacitance of the SO output lines. 34 µPD75P3216 SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY3 Test Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high/low-level width SB0, 1 setup time (to SCK↑) SB0, 1 hold time (from SCK↑) SB0, 1 output delay time from SCK↓ SB0, 1↓ from SCK↑ SCK ↓ from SB0, 1↑ SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 VDD = 2.7 to 5.5 V RL = 1 k Ω,Note CL = 100 pF VDD = 2.7 to 5.5 V tSIK3 VDD = 2.7 to 5.5 V tKL3, t KH3 VDD = 2.7 to 5.5 V tKCY3/2–50 tKCY3/2–150 150 500 t KCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note RL and C L are the load resistance and load capacitance of the SB0 and SB1 output lines. SBI Mode (SCK...External clock input (slave)): (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY4 Test Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high/low-level width SB0, 1 setup time (to SCK↑) SB0, 1 hold time (from SCK↑) SB0, 1 output delay time from SCK↓ SB0, 1↓ from SCK↑ SCK ↓ from SB0, 1↑ SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 VDD = 2.7 to 5.5 V RL = 1 kΩ, Note TYP. MAX. Unit ns ns ns ns ns ns ns tKL4, t KH4 VDD = 2.7 to 5.5 V 400 1600 tSIK4 VDD = 2.7 to 5.5 V 100 150 t KCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns CL = 100 pF Note RL and C L are the load resistance and load capacitance of the SB0 and SB1 output lines. 35 µPD75P3216 AC Timing Test Point (Excluding X1 Input) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock Timing 1/fX tXL tXH X1 Input VDD–0.1 V 0.1 V TI0 Timing 1/fTI tTIL tTIH TI0 36 µPD75P3216 Serial Transfer Timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SI tKSO1, 2 Input Data SO Output Data 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 37 µPD75P3216 Serial Transfer Timing Bus release signal transfer tKCY3, 4 tKL3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INTP0, 4 KR0 to 3 RESET input timing tRSL RESET 38 µPD75P3216 DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 ˚C) Parameter Release signal set time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Test Conditions MIN. 0 TYP. MAX. Unit µs 2 /f X Note 2 15 Release by RESET Release by interrupt ms ms Notes 1. 2. The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. Depends on the basic interval timer mode register (BTM) settings (See the table below). BTM3 BTM2 BTM1 BTM0 Wait Time When fx = 4.19-MHz operation — — — — 0 0 1 1 0 1 0 1 0 1 1 1 2 /fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.81 ms) 213/fx (approx. 1.95 ms) 20 When fx = 6.0-MHz operation 220/fx (approx. 175 ms) 217/fx (approx. 21.8 ms) 215/fx (approx. 5.46 ms) 213/fx (approx. 1.37 ms) Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode STOP Mode Operating Mode Data Retention Mode VDD STOP Instruction Execution RESET VDDDR tSREL tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode STOP Mode Operating Mode Data Retention Mode VDD STOP Instruction Execution Standby Release Signal (Interrupt Request) VDDDR tSREL tWAIT 39 µPD75P3216 DC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, V SS = 0V) Parameter Input voltage, high Symbol V IH1 V IH2 Input voltage, low V IL1 V IL2 Input leakage current Output voltage, high Output voltage, low VDD supply current VPP supply current I LI V OH V OL I DD I PP MD0 = V IL, MD1 = VIH Test Conditions Other than X1, X2 pins X1, X2 Other than X1, X2 pins X1, X2 VIN = VIL or V IH I OH = – 1 mA I OL = 1.6 mA VDD – 1.0 0.4 30 30 MIN. 0.7 VDD VDD – 0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V µA V V mA mA Cautions 1. Keep V PP t o within +13.5 V, including overshoot. 2. Apply V DD b efore VPP a nd turn it off after V PP. AC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, V SS = 0 V) Parameter Address setup time (vs. MD0 ↓) Note 2 Symbol t AS t M1S t DS t AH t DH tDF t VPS t VDS tPW t OPW t M0S t DV t M1H t M1R t PCR t XH, tXL fX t1 t M3S t M3H t M3SR t DAD t HAD t M3HR tDFR Note 1 t AS t OES t DS t AH t DH tDF t VPS t VCS tPW t OPW t CES t DV t OEH tOR — — — — — — — t ACC tOH — — Test Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 TYP. MAX. Unit µs µs µs µs µs 130 ns MD1 setup time (vs. MD0 ↓) Data setup time (vs. MD0 ↓) Address hold time (vs. MD0 ↑) Note 2 Data hold time (vs. MD0 ↑) MD0 ↑ → data output float delay time VPP setup time (vs. MD3 ↑) VDD setup time (vs. MD3 ↑) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD1 ↑) MD0 ↓ → data output delay time MD1 hold time (vs. MD0 ↑) MD1 recovery time (vs. MD0 ↓) Program counter reset time X1 input high-, low-level width X1 input frequency Initial mode set time MD3 setup time (vs. MD1 ↑) MD3 hold time (vs. MD1 ↓) MD3 setup time (vs. MD0 ↓) Address delay time Note 2 µs µs 1.0 1.05 21.0 ms ms µs 1 MD0 = MD1 = VIL t M1H + tM1R ≥ 50 µs 2 2 10 0.125 µs µs µs µs µs 4.19 2 2 2 When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read 0 2 2 2 2 130 MHz µs µs µs µs µs ns → data output Address Note 2 → data output hold time MD3 hold time (vs. MD0 ↑) MD3 ↓ → data output float delay time µs µs Notes 1. 2. Symbol of corresponding µ PD27C256A The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not connected to a pin. 40 µPD75P3216 Program Memory Write Timing tVPS VPP VPP VDD tVDS VDD VDD+1 VDD X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 MD0/P30 tPW MD1/P31 tPCR MD2/P32 tM3S MD3/P33 tM3H tM1S tM1H tM1R tM0S tOPW tXL Data input tI tDS tDH tDV tDF Data output Data input tDS tDH tAH tAS Data input tXH Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 tI MD0/P30 tHAD Data output tDV tM3HR Data output tDFR tDAD tXH MD1/P31 tPCR MD2/P32 tM3SR MD3/P33 41 µPD75P3216 10. CHARACTERISTIC CURVE (REFERENCE VALUE) IDD vs VDD (System clock : 6.0 MHz Crystal resonator) (TA = 25 °C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 HALT mode 1.0 0.5 Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF VDD 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 42 µPD75P3216 IDD vs VDD (System clock : 4.19 MHz Crystal resonator) 10 (TA = 25 °C) 5.0 PCC = 0011 PCC = 0010 PCC = 0001 1.0 PCC = 0000 HALT mode 0.5 Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF VDD 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 43 µPD75P3216 11. PACKAGE DRAWINGS 48 PIN PLASTIC SHRINK SOP (375 mil) 48 25 detail of lead end 1 A 24 H G 3°+7° –3° I J F C D MM N B E K L P48GT-65-375B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 16.21 MAX. 0.63 MAX. 0.65 (T.P.) 0.30 ± 0.10 0.125 ± 0.075 2.0 MAX. 1.7 ± 0.1 10.0 ± 0.3 8.0 ± 0.2 1.0 ± 0.2 0.15+0.10 –0.05 0.5 ± 0.2 0.10 0.10 INCHES 0.639 MAX. 0.025 MAX. 0.026 (T.P.) 0.012+0.004 –0.005 0.005 ± 0.003 0.079 MAX. 0.067 ± 0.004 0.394 +0.012 –0.013 0.315 ± 0.008 0.039+0.009 –0.008 0.006+0.004 –0.002 0.020+0.008 –0.009 0.004 0.004 44 µPD75P3216 12. RECOMMENDED SOLDERING CONDITIONS The µPD75P3216 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Sales representative. Table 12-1. Surface Mounting Type Soldering Conditions µPD75P3216GT: 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch) Soldering Method Infrared rays reflow Soldering Conditions Peak package's surface temperature: 235 ˚C, Reflow time: 30 seconds or less (at 210 ˚C or higher), Number of reflow processes: Twice max. Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours) Products other than those supplied in thermal-resistant tray (magazine, taping, and nonthermal-resistant tray) cannot be baked in their packs. Peak package's surface temperature: 215 ˚C, Reflow time: 40 seconds or less (at 200 ˚C or higher), Number of reflow processes: Twice max. Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours) Products other than those supplied in thermal-resistant tray (magazine, taping, and nonthermal-resistant tray) cannot be baked in their packs. Symbol IR35-107-2 VPS VP15-107-2 Wave soldering Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less, Number of WS60-107-1 flow process: 1, Preheating temperature: 120 ˚C or below (Package surface temperature) Number of days: 7Note (after that, prebaking is necessary at 125 °C for 10 hours) Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per device side) — Partial heating Note The number of days during which the product can be stored at 25 °C, 65 % RH max. after the dry pack has been opened. Caution Use of more than one soldering method should be avoided (except for partial heating). 45 µPD75P3216 APPENDIX A. µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST Parameter Program memory µPD753108 Mask ROM 0000H-1FFFH (8192 × 8 bits) µPD753208 µPD75P3216 One-time PROM 0000H-3FFFH (16384 × 8 bits) Data memory 000H-1FFH (512 × 4 bits) CPU Instruction execution time When main system clock is selected When subsystem clock is selected I/O port CMOS input 75XL CPU • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation) 122 µs (@ 32.768-kHz operation) 8 (on-chip pull-up resistors can be specified by software: 7) CMOS input/output N-ch open drain input/output Total 20 (on-chip pull-up resistors can be specified by software) 4 (on-chip pull-up resistors can be specified by software, withstand voltage is 13 V) 32 Segment selection: 16/20/24 (can be changed to CMOS input/output port in 4 timeunit; max. 8) Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD driver can be specified by using mask option. No on-chip split resistor for LCD driver 5 channels • 8-bit timer counter: 2 channels (Can be used as 16-bit timer counter, carrier generator, timer with gate) • 8-bit timer/event counter: 1 channel • Basic interval timer/watchdog timer: 1 channel • Watch timer: 1 channel 30 Segment selection: 4/8/12 segments (can be changed to CMOS input/output port in 4 time-unit; max. 8) 4 (no mask option, withstand voltage is 13 V) 6 (on-chip pull-up resistors can be specified by software: 5) None LCD controller/driver Timer 5 channels • 8-bit timer/event counter: 3 channels (Can be used as 16-bit timer/event counter, carrier generator, timer with gate) • Basic interval timer/ watchdog timer: 1 channel • Watch timer: 1 channel • Φ, 524, 262, 65.5 kHz Clock output (PCL) (Main system clock: @ 4.19-MHz operation) • Φ, 750, 375, 93.8 kHz (Main system clock: @ 6.0-MHz operation) Buzzer output (BUZ) • 2, 4, 32 kHz (Main system clock: @ 4.19-MHz operation or subsystem clock: @ 32.768-kHz operation) • 2.86, 5.72, 45.8 kHz (Main system clock: @ 6.0-MHz operation) Serial interface 3 modes are available • 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit • 2-wire serial I/O mode • SBI mode SCC register SOS register Vectored interrupt External: 3, internal: 5 External: 2, internal: 5 Contained None • 2, 4, 32 kHz (Main system clock: @ 4.19-MHz operation) • 2.93, 5.86, 46.9 kHz (Main system clock: @ 6.0-MHz operation) 46 µPD75P3216 Parameter Test input Operation supply voltage Operating ambient temperature Package µPD753108 External: 1, internal: 1 VDD = 1.8 to 5.5 V TA = –40 to +85°C • 64-pin plastic QFP (14 × 14 mm) • 64-pin plastic QFP (12 × 12 mm) µPD753208 µPD75P3216 • 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch) 47 µPD75P3216 APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the µPD75P3216. In the 75XL series, relocatable assemblers common to the series can be used in combination with the device files for each product type. RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOS TM Part No. (name) Supply medium 3.5” 2HD 5” 2HD µS5A13RA75X µS5A10RA75X Ver.3.30 to Ver.6.2Note IBM PC/ATTM or compatible Refer to “OS for IBM PCs” 3.5” 2HC 5” 2HC µS7B13RA75X µS7B10RA75X Device file Host machine OS PC-9800 Series MS-DOSTM Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to “OS for IBM PCs” 3.5” 2HC 5” 2HC Supply medium 3.5” 2HD 5” 2HD Part No. (name) µS5A13DF753208 µS5A10DF753208 µS7B13DF753208 µS7B10DF753208 Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above. 48 µPD75P3216 PROM Write Tools Hardware PG-1500 This is a PROM programmer that can program single-chip microcomputer with PROM in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 K to 4 M bits. This is a PROM programmer adapter for the µPD75P3216GT. It can be used when connected to a PG-1500. Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on host machine. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to “OS for IBM PCs” 3.5” 2HD 5” 2HC Supply medium 3.5” 2HD 5” 2HD Part No. (name) PA-75P3216GT Software PG-1500 controller µS5A13PG1500 µS5A10PG1500 µS7B13PG1500 µS7B10PG1500 Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above. 49 µPD75P3216 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P3216. Various system configurations using these in-circuit emulators are listed below. IE-75000-RNote 1 Hardware The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. For development of the µPD753208 subseries, the IE-75000-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753208GT-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. The IE-75000-R includes a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. The IE-75001-R is used in combination with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753208GT-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. This is an emulation board for evaluating application systems using the µPD75P3216. It is used in combination with the IE-75000-R or IE-75001-R. This is an emulation probe for the µPD75P3216GK. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-REM. It includes a flexible board (EV-9500GT-48) to facilitate connections with target system. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note 2 IBM PC/AT or compatible Refer to “OS for IBM PCs” 3.5” 2HC 5” 2HC Supply medium 3.5” 2HD 5” 2HD Part No. (name) IE-75001-R IE-75300-R-EM EP-753208GT-R EV-9500GT-48 Software IE control program µS5A13IE75X µS5A10IE75X µS7B13IE75X µS7B10IE75X Notes 1. This is a maintenance product. 2. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described above. 2. The generic name for the µPD753204, 753206, 753208, and 75P3216 is the µPD753208 subseries. 50 µPD75P3216 OS for IBM PCs The following operating systems for the IBM PC are supported. OS PC DOSTM Version Ver.5.02 to Ver.6.3 J6.1/VNote to J6.3/VNote Ver.5.0 to Ver.6.22 5.0/VNote to 6.2/VNote J5.02/VNote MS-DOS IBM DOSTM Note Only English version is supported. Caution Ver. 5.0 or later include a task swapping function, but this software is not able to use that function. 51 µPD75P3216 APPENDIX C. RELATED DOCUMENTS Some of the related documents are preliminary but are not marked as such. Device related documents Document Name Document Number Japanese English U10166E This document U10158E U10453E µPD753204, 753206, 753208 preliminary product information µPD75P3216 data sheet µPD753208 user’s manual 75XL series selection guide U10166J U10241J U10158J U10453J Development tool related documents Document Name Hardware IE-75000-R/IE-75001-R user’s manual IE-75300-R-EM user’s manual EP-753208GT-R user’s manual PG-1500 user’s manual Software RA75X assembler package user’s manual Operation Language PG-1500 controller user’s manual PC-9800 series (MS-DOS) base IBM PC series (PC DOS) base EEU-846 U11354J U10739J EEU-651 EEU-731 EEU-730 EEU-704 Document Number Japanese English EEU-1416 U11354E U10739E EEU-1335 EEU-1346 EEU-1363 EEU-1291 EEU-5008 U10540E Other related documents Document Name IC package manual Semiconductor device mounting technology manual Quality grade on NEC semiconductor devices NEC semiconductor device reliability/quality control system Static electricity discharge (ESD) test Semiconductor device quality guarantee guide Microcomputer related product guide - other manufacturers C10943X C10535J C11531J C10983J MEM-539 MEI-603 U11416J Document Number Japanese English C10535E C11531E C10983E – MEI-1202 – Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc. 52 µPD75P3216 [MEMO] 53 µPD75P3216 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 54 µPD75P3216 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 55 µPD75P3216 [MEMO] MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 56