UPD765A

NC E Description NEC Electronics Inc. Features uPD765A/uPD765B Single/Double Density Floppy-Disk Controller The uPD765A/B is an LSI floppy disk controller (FDC) chip which contains the circuitry and control functions for interfacing a processor to 4 floppy disk drives. It is capableof either IBM 3740singledensity format (FM), or IBM System 34 double density format (MFM) including double-sided recording. The u PD765A/B provides control signals which simplify the design of an external phase-locked loop and write precompensation circuitry. The FDC simplifies and handles most of the burdens associated with implementing a floppy disk interface. Hand-shaking signals are provided in the u PD765A/B which make DMA operation easy to incorporate with the aid of an external DMA controller chip, such as the uPD8257. The FDC will operate in eitherthe DMA or nonDMA mode. In the non-DMA mode the FDC generates interrupts to !he processor every time a data byte is to be transferred. In the DMA mode, the processor need only load the command into the FDC and all data transfers occur under control of the FDC and DMA controllers. There are 16 commands which the uPD765A/uPD765B will execute. Most of these commands require multiple 8-bit bytes to fully specify the operation which the processor wishes the FDC to perform. The following commands are available. Read Data Read ID Specify Read Diagnostic Scan Equal Scan High or Equal Scan Low or Equal Version Read Deleted Data Write Data Write ID (Format Write) Write Deleted Data Seek Recalibrate Sense Interrupt Status Sense Drive Status. Address mark detection circuitry is internal to the FDC which simplifies the phase-locked loop and read electronics. The track stepping rate, head load time, and head unload time are user-programmable. The uPD765A/uPD765B offers additional features such as multi-track and multi-side read and write commands and single and double density capabilities. FM, MFM Control V ariable recording length: 128,256, .8192 sector IBM-compatible format (single- and doublesided, single- and double-density) Multi-sector and multi-track transfer capability Drive up to 4 floppy or micro floppydisk drives Data scan capability-will scan a single sector or an entire cylinder comparing byte-for-byte host memory and disk data Data transfers in DMA or non-DMA mode Parallel seek operations on up to four drives C ompatible with u PD8080/85, uPD8086/88, and uPD780 (Z80@) microprocessors Single-phase clock: 8 MHz maximum 3 +5V only Z80 is a registered trademark of the Zilog Corporation V-series bytes/ Pin Configuration Ordering Information Device Number uPD765AC2 uPD765B Package Type Max Freq. of Operation 8 MHz 8 MHz 40-pin plastic DIP 40-pin plastic DIP NECEL-000324 5-3 uPD765A/uPD765B Pin Identification No. Symbol Function NEC RD (Read Strobe) Reset input Read control input Write control input Chip select input Data or status select input Bidirectional data bus DMA request output DMA acknowledge input Terminal count input Index input Interrupt request output Clock input Ground Write clock input Read data window input Read data input VCO sync output Write enable output MFM output Head select output FDD unit select output Write data output Preshift output Fault/track zero input Write protect/two side input R e a d y input Head load output Fault reset/step output Low current direction output Read/write/ seek output DC power ( +5 V) 1 2 3 4 5 6-13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31, 32 33 34 35 36 37 38 39 40 RESET R D WR C S A0 DB0-DB7 DRQ DACK TC INDEX INT CLK GND WCLK WINDOW R DATA SYNC WE MFM SIDE USn US1 WDATA P S 0 PS1 FLT/TRK0 WPRT/2SIDE READY HDLD FLTR/STEP LCT/DIR m/SEEK kc The RD input allows the transfer of data from the FDC to the data bus when low and either C or DACK is S asserted. WR (Write Strobe) T e R input allows the transfer of data to the FDC hW from the data bus when low. Disabled when C i s high. S A0 (Data/Status Select) The A0 input selects the data register (A0 = 1) or status register (A0=O) contents to be accessed through the data bus. C (Chip Select) S The FDC is selected when C i s low, enabling R a nd S D WR. DBo-DB7 (Data Bus) DBo-DB7 a re a bidirectional 8-bit S when C i s high. data bus. Disabled DRQ (DMA Request) The FDC asserts the DRQ output high to request a DMA transfer. DACK (DMA Acknowledge) When the DACK input is low, a DMA cycle is active and the controller is performing a DMA transfer. TC (Terminal Count) When t h e T C i nput is high, it indicates the termination of a DMA transfer. It terminates data transfer during R ead/ Write/Scan commands in DMA or interrupt mode. INDEX (Index) The INDEX input goes high at the beginning of a disk track. Pin Functions RESET (Reset) The RESET input places the FDC in the idle state. It resets the output lines to the FDD to 0 (low), except PSO, 1 and WDATA (undefined), INT and DRQ also go low; DBO-7 goes to an input state. It does not affect SRT, HUT, or HLT in the Specify command. If the RDY input is held high during reset, the FDC will generate an interrupt within 1.024ms. To clear this interrupt, use the Sense Interrupt Status command. INT (Interrupt) The INT output is F DC’s interrupt request. In Non-DMA mode, the signal is output for each byte. In DMA mode, it is output at the termination of a command operation. CLK (Clock) CLK is the input for the F DC’s single-phase, lTL-level squarewave clock: 8 MHz or 4 MHz. (Requires a pull-up resistor.) NEC WCLK (Write Clock) The WCLK input sets the data write rate to the FDD. It is 500 kHz for FM, 1 MHz for MFM drives, for 8 MHz operation of the FDC; 250kHz FM or 500 kHz MFM for 4 MHz FDC operation. This signal must be input for read and write c y c l e s WCLK’s rising edge must be synchronized with CLK’s rising edge, except for the uPD765B. uPD765A/uPD765B READY (Ready) The READY input indicates that the FDD is ready to receive data. WINDOW (Read Data Window) The WINDOW input is generated by the phase-locked loop (PLL). It is used to sample data from the FDD and in distinguishing between clock and data bits in the FDC. HDLD (Head Load) The HDLD output is the command which causes the read/write head in the FDD to contact the diskette. RDATA (Read Data) The RDATA input is the read data from the FDD, containing clock and data bits. To avoid a deadlock situation, input RDATA and WINDOW together. FLT/TRKO (Fault/Track 0) In the read/write mode, the FLT input detects FDD fault conditions. In the seek mode, TRKO indicates track 0 head position. WDATA (Write Data) WDATA is the serial clock and data output to the FDD. WPRT/2SlDE (Write Protect/Two Side) In the read/write mode, the WPRT input senses write protected status (at the drive or media.) In the seek mode, 2SIDE senses two-sided media. WE (Write Enable) The WE output enables write data into the FDD. SYNC (VCO Sync) The SYNC output inhibits the VCO in the PLL when low, enables it when high. FLTR/STEP (Fault Reset/Step) In the read/write mode, the FLTR output resets the fault flip-flop in the FDD. In the seek mode, STEP outputs step pulses to move the head to another cylinder. A fault reset pulse is issued at the beginning or each Read or Write command prior to the HDLD signal. MFM (MFM Mode) The MFM output shows the high for MFM, low for FM. VCO’s operation mode. It is LCT/DlR (Low Current/Direction) In the read/write mode, the LCT output indicates that the R/W head is positioned at cylinder 42 or greater. In the seek mode, the DIR output determines the direction the head will move in when it receives a step pulse. If DIR is 0, seeks are performed in the outward direction; DIR is 1, seeks are performed in the inward direction. SIDE (Head Select) Head 1 is selected when the SIDE output is 1 (high), head 0 is selected when SIDE is 0 (low). U S 0 US1 (Unit Select 0,1) The US0 and US1 outputs select up to 4 floppy disk drive units using an external decoder. RWlSEEK (Read/Write/Seek) PS0, PS1 (Preshift 0,1) The PS0 and PS1 outputs are the write precompensation request signals for MFM mode. They determine early, late, and normal times for WDATA shifting. The RW/SEEK output specifies the read/write mode when low, and the seek mode when high. GND (Ground) Ground. Vcc(+5v) +5 V power supply. 5-5 uPD765AIuPD765B Block Diagram DC Characteristics +70°C,Vcc = __ Symbol +5V%lO% Limits Parameter NEC Th= -1O’C to Min -0.5 2.0 Typ Max Teal Input voltage IOW Unit v 5v Conditions Input voltage high Output voltage low Voltage VIH 0.45 2.4 0 .5 kc 0.65 V V V Input voltage low (CLK + WCLK) Input voltage high (CLK + WCLK) Supply current kc) Input load current high Input load current low Output leakage current high v 150 140 10 -10 10 -10 Absolute Maximum Ratings TA = 250C Power supply voltage, VCC Input voltage, V1 Output voltage, VO -0 5 to +7v Output leakage current low -0.5 to +7v - 0 . 5 1 0 +7v Capacitance Limits Typ Test Conditions (Note 1) (Note 1) Operating temperature, T OpT Storage temperature, TSTG - 1OOC to +7ooc -65°C to +150°C Parameter Input clock Input capacitance Symbol Min Comment: Exposing the device to stresses above those listed in the Absolute Maximum Ratings could cause permanent damage. The device should not be operated under conditions outside the limits described in the operational sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Max Unit 20 pF 10 pF output capacitance COUT 20 pF [Note 1) Note: (1) All pinsexcept pin under test tied to AC ground. 5-6 NEC DIFFERENCES BETWEEN ,uPD765A AND uP D765B The uPD765B is a functionally enhanced version of the uPD765A.Differences are explained below. uPD765A/uPD765B Overrun Bit [OR] In uPD765A, when executing a read- or write-type command (except READ ID and SCAN types), the result status OR bit is not set if there is an overrun on the final byte of a sector. An improvement in the uPD765B allows it to set the OR bit in any situation. DRQ Reset When an overrun occurs, the uPD765A needs DACK input to reset DRQ. If DACK is not available, an external DMA controller continues to operate even after the F C enters the R-Phase (Result Phase), and stored D result status may be transferred accidentally as ordinary data. On the other hand, the uPD765B resets DRQ automatically just before the R-Phaseentry and independent of the DACK input. See AC Characteristics for DRQ reset timing. Clock Synchronization The uPD765B does not require synchronization between the CLK and WCLK inputs. Version Command The Version command distinguishes the uPD765B from other devices. The ST0 response to the Version command is: Part No. uPD765A uPD765B ST0 Value 80H 90H 5-7 uPD765AIuPD7656 AC Characteristics = -10 to = V Parameter Clock period Clock active (high, low) Clock rise time Clock fall time DACK setup time to RO CS, DACK hold time from width Data access from DB to float delay time from CS. OACK setup time to WR I OACK hold time width Data setup time to Data hold time from time from Symbol Min Typ 120 240 40 125 250 Max Unit Conditions 500 ns CLK C LK Parameter WCLK cycle time WCLK active time Symbol Min Typ 16 8 250 0 Max Conditions M FM = 0 M FM = 1 350 ns Note 4 ns only 20 20 ns CLK delay WCLK WCLK. RDATA and time WINDOW and WCLK, WINDOW fall time 20 20 20 20 20 100 100 ns ns ns ns ns ns 0 0 200 140 10 AW 0 0 200 100 0 ns ns ns ns ns Non-DMA mode 85 ns = 100 ns Preshift from WCLK WCLK delav time RDATA time Window cycle time Window hold time from RDATA Window setup time to RDATA setup time to SEEK SEEK setup time to DIR Direction setup time to step hold time from step t ns (Note 4) Step active time (high) Step cycle time Fault reset time (high) Write data width hold time after seek 7 1 40 2 1 MFM=O ns ns CLK Notes 4, 5 15 15 12 7 + + 135 INT delay time from + 135 cycle time DACK delav DRQ delay DACK AA 200 13 140 5.0 6 7 8 Notes 4.5 ns ns ns (Note 4) ns 33 Note 2Note 2 8 .0 10 DACK width TC width Reset width INT DRQ response time DACK INT ineffective + 15 1 15 14 60 7 only SEEK hold time from DIR DIR hold time after step Index pulse 30 24 4 CLK Notes 3.4. 5 CLK Notes 4, 5 AC Characteristics (cont) Parameter delay from DRQ delay from DRQ response time from DRQ Notes: (1) Typical values for TA = 25°C and nominal supply voltage. ( 2 ) Under software controLThe range is from 1 16ms at 8-Mhz ms to clock period, and 2 ms to 32 ms at 4 -Mhz clock period. (3) When one device is executing a SEEK operation, SENSE DRIVE STATUS is executed on another device. (4) Double these values for a 4-MHZ (5) Thedrivesiderating value. clock period Symbol Min Typ (1) Max Unit Conditions 800 250 12 ns S-MHz CLK Note 4 ns has a variance of ~5Ons from the minimum liming Waveforms Processor Read Operation Processor Write C S, DACK Operation liming Waveforms (Cont) Data Input Waveform for AC Test (Except CLK, 2.4 Seek Operation 0.45 s t e p Clock (WCLK, Waveform for AC Test Output Overrun Operation Only) Clock Operation FLJ Reset I Fault Reset FDD Read Operation 1 FDD Write Operation Write Enable 0 or Terminal I Count Write Data 0 Normal 0 0 Early Invalid 0 0 Reset I 5-10 NEC liming Waveforms (Cont) Write Clock No. Name uPD765A/uPD765B Table 2. Main Status Register Function DB0 D0B (FDD 0 Busy) D1B (FDD 1 Busy) D2B (FDD 2 Busy) D3B (FDD 3 Busy) CB (FDC Busy) EXM (Execution Mode) FDD number 0 is in the seek mode. II any of the D nB bits I S set FDC will not accept read or write command. FDD number1 is in the seek mode. If any of the DnB bits I S set FDC will not accept read or write command. FDD number 2 is i n the seek mode If any of the D nB bits IS set FDC will not acceot read or write command FDD number 3 is i n the seek mode. If any of the DnB bits I S set FDC will not a ccept read or write command A Read or Write command is in orocess. FDC will not accept any other command. This bit is set only during execution ohase in non-DMA mode When DB5 goes low, execution phase has ended and result phase has started. It operates only during non-DMA mode of operation DB1 DB2 Index I INDEX DB3 DB4 D5 B Internal Registers D B 6 contains two registers which The uPD765A/uPD765B may be accessed by the main system processor: a status register and a data register. The 8-bit main status register contains the status information of the FDC, and may be accessed at any time. The 8-bit data register in a (which actually consists of four registers, STO-ST3, stack with only one register presented to the data bus at a time), stores data, commands, parameters, and FDD status information. Data bytes are read out of, or written into, the data register in order to program or obtain the results after a particular command (table 3). Only the status register may be read and used to facilitate the transfer of data between the processor and uPD765A/ uPD765B. The relationship between the status/data registers and the signals RD, WR, and A 0 is shown in table 1. Table 1. Status/Data Register Addressing A0 0 D7 B DIO Indicates direction of data transfer be(Data Input/Output) tween FDC and data regrster If DIO = 1, then transfer is from data register to the processor. If DIO = 0, then transfer is from the processor to data register. RQM Indicates data register I S ready to send or (Request for Master) receive data to or from the processor Both bits DIO and RQM should be used to perform the hand-shaking functions of “ready” and “directron” to the processor The DIO and RQM bits in the status register indicate when data is ready and in which direction data will be transferred on the data bus. See figure 1. Figure 1. Data In/Out (I) DO DIO and RQM Out FDC and Into Processor Out Processor and Into FDC RD 0 WR 1 Function Read main status register Illegal Illegal Illegal Read from data register Write into data register II C 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 The bits in the main status register are defined in table 2. 5-l 1 uPD765A/uPD765B Table 3. Status Register Identification Pin NO. Name NEC Table 3. Status Register Identification (cont) Pin Function NO. Name Function During execution of Read Data. Read Deleted Data Write Data. W rite Deleted Data or Scan command, if the FDC cannot find the sector specified in the IDR(2) Register, this flag i s set. During execution of the Read ID command. if the FDC cannot read the ID field without an error, then this flag I S set. During execution of the Read D iagnostic command. if the starting sector cannot be found, then this flag is set. Status Register 0 D7, D6 IC (Interrupt Code) D7=0 and D6=0 Normal termination of command, (NT) Command was completed and properly executed D7=0 and D6=1 Abnormal termination of command, (AT) Execution of command was started but was not successfully completed. D7=1 and D6=0 Invalid command issue, (IC) Command which was issued was never started D7=1 and D6=1 Abnormal termination because during command execution the ready srgnal from FDD changed state Status Register 1 (cont) D2 ND (No Data) D1 N ( o Writeable) Wt N During execution of Write Data, Write Deleted Data or Write ID command. if the FDC detect: a write protect srgnal from the F D D . t h e n this f l a g i s S e t This bit is set i f the FDC does not detect the IDAM before 2 i ndex pulses It is also set if the FDC cannot find the DAM or DDAM after the IDAM is found. MD bit of ST2 is also ser at t his time. Not used. This bit I S alwavs 0 (low) D65 D4 SE (Seek End) EC (Equipment Check) When the FDC completes the Seek command, this flag I S set lo 1 (high). If a fault srgnal I S received from the FDD, or if the track 0 srgnal fails to occur after 77 step pulses (Recalibrate Command) then this flag is set When the FDD I S in the not-ready state and a Read or Write command I S Issued, this flag IS set If a Read or Write command is issued to s ide 1 of a single-sided drive, then this flag IS set This flag IS used to i ndicate the state of the head at interrupt. This flag I S used to indicate a d rive unit number at interrupt. This flaa is used to Indicate a drive unit number at interrupt When the FDC tries to access a sector beyond the final sector of a c ylinder, this flag IS s e t Not used. This b it is always 0 (low) When the FDC detects a CRC(1) error in e ither the ID field or the data field, this flag i s set If the FDC i s not serviced by the host system during data transfers w ithin a certain time interval. t his flaa i s set. Not used. This b it is alwavs 0 (low). Do MA (Missing Address Mark) Status Register 2 D7 De CM (Control Mark) During execution of the Read Data or Scan command, if the FDC encounters a sector which contains a deleted data address mark, this flag is set Also set if DAM is found during Read Deleted Data If the FDC detects a CRC error i n the data field then this flag is set This bit IS related to the ND bit, and when the contents of C(3) on the medium is different from that stored i n the IDR. t his flag is set During execution of the Scan command. i f the condition o f “equal” is satisfied, this flag is set. During execution of the Scan command, i f the F D cannot find a sector on the cylinder which meets the condition. then Cthis flag is set This bit is related to the ND bit. and when the contents of C on the m edium i s different from that stored i n the IDR and the contents of C I S FFH. then this flag I S set When data I S read from the m edium, if the FDC cannot find a data address mark or deleted data address mark, then t his flag is set D3 NR (Not Ready) D2 D1 D0 HD (Head Address) US: (Unit Select 1) Us0 (Unit Select 0) EN (End of Cylinder) D5 DA DD (Data Error in Data Field) WC (Wrong Cylinder) Status Register 1 D7 D3 SH (Scan Equal Hit) SN (Scan N o t S a t i s f i e d ) D2 DE(Data Error) D4 OR (Overrun) D1 BC (Bad Cylinder) D3 Do MD (Missing Address Mark in Data Field) NEC Table 3. Status Register Identification ( cont) Pin NC. Status Register 3 Name Function Name A0 uPD765A/uPD765B Command Symbol Description Function (Address Line 0) This bit is used to indicate the status of the fault signal from the FDD. This bit is used to indicate the status of the write protected signal from the FDD. This bit is used to Indicate the status of the ready signal from the FDD. This bit IS used to indicate the status of the track 0 signal from the FDD. This bit I S used to indicate the status of the two-side signal from the FDD. This bit is used to Indicate the status of the side select signal to the FDD This bit is used to Indicate the status of the unit select 1 signal to the FDD. This bit is used to indicate the status of the unit select 0 signal to the FDD. H (Head Address) HD(Head) C (Cylmder Number) D (Data) D7-D0 (Data Bus) DTL (Data Length) EOT (End of Track) GPL (Gap Length) A0 controls selection of m ain status register (A0=0) or data register (A0= 1). C stands for the current /selected cylinder (track) numbers 0 through 76 of the medium D stands for the data pattern which is going to be written into a sector during WRITE ID operation 8-bit data bus, where D7 stands for a most significant bit, a nd D0 s t a n d s f o r a l e a s t significant bit. When N is defined as 00. DTL stands for the data length which users are g oing to read out or write into the sector EOT stands for the final sector number on a cylinder Durmg read or write operations, FDC will stop data transfer after a sector number e qual to EOT GPL stands for the length of gap 3. During Read / Write commands t his value determines the number of bytes that VCO sync will stay l ow after two CRC bytes During Format command it determines the size of gap 3 H stands for the logical specified in ID field head number 0 or 1. as D7 D6 D56 D4 03 D2 D1 D0 Note: FT (Fault) WP (Write Protected) RY (Ready) TO (Track 0) TS (Two-Side) HD (Head Address) US1 (Unit Select 1 ) US0 (Unit Select 0) (1) CRC = Cyclic Redundancy Check (2) IDR = Internal Data Register (3) Cylinder (C) is described more fully in the Command Symbol Description. HD stands for a the physical head number 0 or 1 and controls the polarity of p in 27 (H = HD in all command words ) HLT stands for the head load time in the FDD (2 to 254 ms in 2 ms Increments). HUT stands for the head unload t ime after a Read or Write operation has occurred (16 to 240 ms in 16 ms Increments) If MF I S low, FM mode I S selected, and if it is high, M F M m o d e IS s e l e c t e d IF MT i s high, a multitrack operation IS performed If MT = 1 after finishing read/write operation on siude 0. FDC will automatically start searching for sector 1 on side 1 N stands for the number of data bvtes written in a sector NCN stands for a new cylinder number which is going to be reached as a result of the seek operation; desired position of head ND stands for operation in the non-DMA mode Command Sequence The uPD765A/uPD765B is capable of performing 15 different commands. Each command is initiated by a multibyte transfer from the processor, and the result after execution of the command may also be a multibyte transfer back to the processor. Because of this m ultibyte interchange of information between the uPD765A/ uPD765B and the processor, it is convenient to consider each command as consisting of three phases: Command Phase: Execution Phase: Result Phase: The FDC receives all information required to perform a particular operation from the processor. The FDC performs the operation it was instructed to do. After completion of the operation, status and other housekeeping information are made available to the processor. HLT (Head Load Time) HUT (Head Unload T ime) MF (FM or MFM Mode) MT (Multitrack) N (Number) NCN (New Cylinder Number) ND (Non-DMA Mode) Table 4 shows the required preset parameters and results for each command. Most commands require 9 command bytes and return 7 bytes during the result phase. The “W” to the left of each byte indicates a command phase byte to be written, and an “R” indicates a result byte. The definitions of other abbriviations used in table are given in the Command Symbol Description table. PCN PCN stands for the cylinder number at the (Present Cylinder Number) completion of Sense Interrupt Status command, position of head at present time R [Record) R/W (Read/Write) SC (Sector) SK (Skip) R stands for the sector number which or written will be read R/W stands for either Read (R) or Write (W) signal SC indicates the number of sectors per cylinder SK stands for skip deleted data address mark 5-13 uPD765A/ uPD765B Command Symbol Description (cont) SRT (Step Rate Time) STO-ST3 (Status O-3) SRT stands for the steooino rate for the FDD ( 1 to 16 ms in 1 ms increments). Stepping rate applies to all drives (FH=1ms, EH=2ms, etc.). STO-ST3 stands for one of four registers which store the status information after a command has been executed. This information I S available during the result phase after command e xecution. These registers should not be confused with the main status register (selected by Ao=O). STO-ST3 may be read only after a command has been executed and c ontains information relevant to that particular command Command Symbol Description (cont) Name Function STP During a scan o peration if STP=1, the data in contiguous sectors is compared byte by byte with data sent from the processor (or DMA); and i f STP=2, then alternate sectorsare read and compared US stands for a selected drive number 0 or 3 US0, US1 (Unit Select) Table 4. Instruction Set (Notes 1,2) Instruction Code Phase Read Data R/W D7 MT X D6 MF X D5 SK X X D4 0 X C H R N EOT GQL DTL ST0 ST1 ST2 C H D3 0 HD D2 1 US1 D1 1 D0 0 US0 Remarks Command w W W W w W W w Command codes (Note 3) Sector ID prior to command e xecution are compared against header on floppy disk. The 4 bytes w Execution Result Data transfer between the FDD and main system Status Information after command execution Sector ID Information after command execution R R R R e a d D e l e t e d Data Command W W W W W w N MT X MF X SK X X C H R N 0 X 1 HD 1 0 US, 0 US0 Command codes Sector ID rnformation to command execution are compared against header on floppy disk The 4 bytes W W W Execution Result EOT GPL DTL Data transfer between the FDD and main system ST0 ST1 ST2 C Status information after command execution Sector ID information after command execution R RR Note: H R N (1) Symbols used in this table are described at the end of this section (2) A0 should equal 1 for all operations. (3) X = Don’t care, usually made to equal 0. NEC Table 4. Instruction Set (Notes 1,2) (cont) instruction Code Phase Write Data Command W W W W W W MT X MF X X 0 X 0 X c H R EOT GPL DTL 0 HD 1 0 1 uPD765A/uPD765B Remarks Command codes Sector ID information prior to command execution. The 4 are compared against header on floppy Data transfer between the main system and FDD Status ST2 C H R R Write Deleted Data Command W W W W W W w MT X MF 0 0 X X X X C 1 HD 0 US, Sector Information prior to are compared against header on floppy disk The 4 bytes 1 Command codes N after command execution Sector ID information after command execution - p w Execution Result R N EOT GPL DTL Data transfer between the FDD and main system Status information after command execution ST1 ST2 C H Sector ID information after command execution R Read Diagnostic Command w W W W 0 X MF X SK X X 0 N 0 X H R N EOT GPL DTL Data transfer between the FDD and main system data fields from index hole to EDT. FDC reads all HD Sector prior to command execution 0 1 0 Command codes w W W W w Result ST1 ST2 C H N Status information after command execution Sector ID Information after command 5-15 Table 4. Set (Notes instruction Code Remarks Read Command Executron W W 0 X MF X 0 X X 0 X 1 HD 0 US, The first correct ID register. ST1 ST2 C H N ID Command W MF Command codes on the cylinder stored data Status information after command execution Sector ID read during executron phase from floppy 1 X X X N SC GPL HD 1 US, 1 C o m m a n d codes Bytes/sector Sectors/track Gap3 byte FDC formats an entire track. Status information after command execution w W W W W Result X X R Scan Equal Command W W W W MT X SK X X X ST1 ST2 C H RN 1 X C H EOT GPL STQ 0 0 0 US, 1 In this case, the ID has no Command codes Sector command execution w W W w W Execution Result Data Status ST1 ST2 C H fl N between the and main after command execution Sector ID information after command Note: (1) Symbols used this table are described at the end of this section should equal 1 for all operations. (3) X Don’t care, usually made to equal 0. 5-16 Table 4. Instruction Set (Notes code Phase Remarks Scan or MT X MF SK X X X 1 X C H N EOT GPL STP Data comoared between the FDD and 1 HD 0 0 US, 1 Command codes Sector ID to command Command Result ST1 ST2 C R Scan High Command Equal W w w w W W W W w MT X MF X SK X X C N EDT GPL STP 1 X 1 1 0 US, R N - Status after command execution Sector ID Information after command Command codes Sector ID information prior to command execution Execution Result ST1 ST2 C H R R Command W W o x 0 x 0 x x D x 0 1 1 Data compared between the FDD and Status Information after command Sector ID information after command - system Command codes Head retracted to track 0 Sense Interrupt Status Command Result P CN Specify Command W W W W W 0 0 SRT HLT 0 X 0 X 0 X X 0 X ST3 D HD 0 US, 0 0 0 0 HUT ND 0 Command codes Status about FDD 1 1 Command codes w 0 0 0 0 1 0 0 0 Command codes Status Information about the FDC at the end of seek Sense Drive Status Command Result 5-17 Table 4. Instruction Set (Notes I, Version Command w x x x 1 0 0 0 0 Command codes Indicates 7658 indicates S eek Command W W W 0 X 0 X 0 X X 0 X NCN 1 HD 1 1 US, 1 Command c o d e Execution Invalid Command Note: (1) Symbols used in this table are described at the end of this section. (2) should equal 1 for all operations. (3) Don’t care, usually made to equal 0. Head W Codes IS positioned over proper cylinder on diskette goes state) Invalid Command codes (No op- System Configuration Figure 2 shows an example of a system using a Figure 2. System Configuration 5-18 Data Format Figure 3 shows the data transfer format for a nd in FM and MFM modes. Figure 4 shows VCO Sync timing. Figure 3. Data Format [FM Mode] [MFM Mode] Figure 4. VCO Sync Timing