UPD78C14G

DATA SHEET MOS INTEGRATED CIRCUIT µPD78C14(A) 8-BIT SINGLE-CHIP MICROCONTROLLER (WITH A/D CONVERTER) The µPD78C14(A) is a single-chip, CMOS 8-bit microcontroller in which a 16-bit ALU, a ROM, a RAM, an A/D converter, a multifunction timer/event counter, and a serial interface are all integrated. Moreover, a 48-Kbyte external expansion memory (ROM/RAM) can be connected. Since the µPD78C14(A) uses the CMOS construction, its operations are performed with low power consumption. By using the standby function, functions such as data retention are performed with lower power consumption. For details on functions, refer to the User’s Manual listed below. Please read it before starting design work. 87AD series µPD78C18 User’s Manual: IEU-1314 FEATURES High reliability as compared with µPD78C14 159 instructions: 87AD instruction set Multiply and divide instructions, 16-bit arithmetic operation instructions Instruction cycle: 0.8 µs at 15 MHz Internal ROM: 16384 W x 8 Internal RAM: 256 W x 8 Direct addressing to an external memory (ROM/RAM) up to 64 Kbytes Highly accurate 8-bit A/D converter: Eight analog inputs General-purpose serial interface: Asynchronous, synchronous, and I/O interface modes Multifunction 16-bit timer/event counter Two 8-bit timers I/O lines: 44 Interrupt functions: Three external, eight internal • Non-maskable interrupt: 1 • Maskable interrupts: 10 Zero-cross detection function (two inputs) Standby functions: HALT mode, Hardware/software STOP mode ORDERING INFORMATION Part number µPD78C14G(A)-xxx-36 µPD78C14GF(A)-xxx-3BE µPD78C14L(A)-xxx Remark xxx is a ROM code suffix. Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Package 64-pin plastic QUIP 64-pin plastic QFP (14 x 20 mm) 68-pin plastic QFJ (950 x 950 mil) Quality grade Special Special Special The information in this document is subject to change without notice. Document No. IC-2813B (O.D. No. IC-8242B) Date Published May 1995 P Printed in Japan H The mark * shows revised points. © © 1991 1994 µPD78C14(A) Pin Configuration (Top View) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/TxD PC1/RxD PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 NMI INT1 MODE1 RESET MODE0 X2 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD STOP PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD VAREF AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS PD3 PD4 PD5 PD6 PD7 STOP VDD PA0 PA1 PA2 PA3 PA4 PA5 51 50 49 48 47 46 454443 42 41 40 39 38 37 36 35 34 33 52 32 53 31 54 30 55 29 56 28 57 27 µ PD78C14GF(A)-XXX-3BE 58 26 59 25 60 24 61 23 62 22 63 21 641 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1718 19 20 PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD VAREF AN7 AN6 AN5 2 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/TxD PC1/RxD PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 NMI µ PD78C14G(A)-XXX-36 AN4 AN3 AN2 AN1 AN0 AVSS VSS X1 X2 MODE0 RESET MODE1 INT1 µPD78C14(A) PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/TxD PC1/RxD PC2/SCK PC3/INT2 IC PC4/TO PC5/CI PC6/CO0 9 8 7 6 5 4 3 2 1 68 67 66 6564 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 µ PD78C14L(A)-XXX 19 51 20 50 21 49 22 48 23 47 24 46 25 45 44 26 2728 29 30 3132 33 34 35 36 37 38 39 4041 42 43 IC PA6 PA5 PA4 PA3 PA2 PA1 PA0 VDD STOP PD7 PD6 PD5 PD4 PD3 PD2 IC PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD IC VAREF AN7 PC7/CO1 NMI INT1 MODE1 RESET MODE0 X2 X1 VSS AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 3 X1 X2 PC0/TxD PC1/RxD PC2/SCK NMI INT1 4 PC3/INT2/TI PC4/TO PC5/CI PC6/CO0 PC7/CO1 AN7-0 VAREF VDD AVSS 8 OSC SERIAL I/O 8 DATA MEMORY (256-BYTE) 8 8 8 16 PORT C INT. CONTROL 8 16 LATCH INC/DEC PC SP EA V A B C E D H L EA' V' A' B' C' E' D' H' L' BUFFER 8/16 8 8 14 8 MAIN G.R PORT F 16 8 8 Note PORT D TIMER 8 8 16 8 LATCH 16 INTERNAL DATA BUS 6 PSW INST.REG 16 PORT B PORT A 4 8 PF7-0/AB15-8 8 PD7-0/AD7-0 PROGRAM MEMORY ALT (16 K-BYTE) G.R 8 8 PC7-0 8 8 8 PB7-0 TIMER EVENT COUNTER Block Diagram LATCH 8 INST. DECODER 8 PA7-0 A/D CONVERTER 8 ALU (8/16) 16 READ/WRITE CONTROL SYSTEM CONTROL STANDBY CONTROL RD WR ALE MODE1 MODE0 RESET STOP VDD VSS µPD78C14(A) Note DATA MEMORY can only be used when RAE bit of MM register is set to 1. External memory is necessary when 0 is set. µPD78C14(A) CONTENTS 1. 2. DIFFERENCES BETWEEN µPD78C14(A) AND µPD78C14 ...................................................6 PIN FUNCTIONS ......................................................................................................................7 2.1 2.2 2.3 Pin Function List .........................................................................................................................7 Pin Input/Output Circuits ...........................................................................................................9 Recommended Connections for Unused Pins....................................................................... 13 3. INSTRUCTION SET ................................................................................................................14 3.1 3.2 3.3 Operand Expression Format/Description Method .................................................................14 Instruction Code Description ..................................................................................................16 Instruction Execution Time......................................................................................................17 4. 5. 6. 7. 8. LIST OF MODE REGISTERS .................................................................................................29 ELECTRICAL SPECIFICATIONS ..........................................................................................30 CHARACTERISTIC CURVES (reference value) ...................................................................41 PACKAGE DRAWINGS .........................................................................................................44 RECOMMENDED SOLDERING CONDITIONS .....................................................................47 APPENDIX DEVELOPMENT TOOLS ............................................................................................49 5 µPD78C14(A) 1. DIFFERENCES BETWEEN µPD78C14(A) AND µPD78C14 Part number Item Quality grade Electrical specifications Package Special Input leakage current (AN7-0; ±1 µA (MAX.) • 64-pin plastic QUIP • 64-pin plastic QFP (14 x 20 mm, thickness: 2.05 mm) • 68-pin plastic QFJ Standard Input leakage current AN7-0; ±10 µA (MAX.) • 64-pin plastic shrink DIP • 64-pin plastic QUIP • 64-pin plastic QUIP (straight) • 64-pin plastic QFP (14 x 20 mm, thickness: 2.05 mm) • 64-pin plastic QFP (14 x 20 mm, thickness: 2.70 mm) • 68-pin plastic QFJ µPD78C14(A) µPD78C14 6 µPD78C14(A) 2. PIN FUNCTIONS 2.1 Pin Function List Pin PA7-PA0 (Port A) PB7-PB0 (Port B) PC0/TxD PC1/RxD PC2/SCK Input/Output, Output Input/Output, Input Input/Output, Input/Output Input/Output Input/Output Input/Output units. These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit units. Port C These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit units. Transmit Data This pin outputs serial data. Receive Data This pin inputs serial data. Serial Clock This pin inputs/outputs serial clock. It becomes an output pin when an internal clock is used or an input pin when an external clock is used. PC3/INT2/TI Input/Output, Input, Input Interrupt Request/Timer Input This pin inputs edge triggering (falling edge) maskable interrupt or external clock for timer. This pin is also shared with zero-cross detection pin for AC input. PC4/TO Input/Output, Output Timer Output This pin outputs square waves in which one cycle of the internal clock forms a half cycle, indicating the timer’s counting time. PC5/CI Input/Output, Input PC6/CO0 PC7/CO1 PD7-PD0/ AD7-AD0 Input/Output, Output Input/Output, Input/Output Port D These 8 pins constitute an 8-bit I/O port and input/output can be specified in byte units. PF7-PF0/ AB15-AB8 Input/Output, Output Port F These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit units. WR (Write Strobe) Output This is a strobe signal output to write data in external memory. This signal becomes high level except during the data write machine cycle for external memory. This signal becomes output high impedance when the RESET signal is low or in the hardware STOP mode. Counter Input This pin inputs external pulse for timer/ event counter. Counter Output 0,1 This pin outputs programmable square wave by timer/event counter. Address/Data Bus These pins function as multiplexed address/data bus when using an external memory. Address Bus These pins function as address bus when using an external memory. Function These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit 7 µPD78C14(A) (Continued) Pin RD (Read Strobe) ALE (Address Latch Enable) MODE0 MODE1 (Mode) NMI (NonMaskable Interrupt) INT1 (Interrupt Request) AN7-AN0 (Analog Input) VAREF (Reference Voltage) AVDD (Analog VDD) AVSS (Analog VSS) X1, X2 (Crystal) RESET (Reset) STOP (Stop) VDD VSS Input This pin inputs control signal of the hardware STOP mode. When the low level of this signal is input, the oscillator stops to operate. Positive power supply pin Ground pin Input These are crystal connecting pins for the system clock oscillation. When a clock is externally supplied, input it through pin X1. Input the clock to X1 and its reverse phase to X2. This pin inputs the active-low reset input signal. Ground pin for the A/D converter Power supply pin for the A/D converter Input This pin inputs the reference voltage for the A/D converter and controls the operation for the A/D converter. Input These eight pins input analog signals for the A/D converter. Pins AN7-AN4 can be used as edge detection (falling edge) input. Input This pin inputs edge triggering (rising edge) maskable interrupt. This pin is also shared with zero-cross detection pin for AC input. Input Input/Output Output Input/Output Output Function This is a strobe signal output to read data from external memory. This signal becomes high level except during the data read machine cycle for external memory. This signal becomes output high impedance when the RESET signal is low or in the hardware STOP mode. This is a strobe signal to externally latch the low-order address information output to pins PD7-PD0 to access the external memory. This signal becomes output high impedance when the RESET signal is low or in the hardware STOP mode. Set the MODE0 pin to 0 (low level) and MODE1 pin to 1 (high level)Note. When both pins MODE0 and MODE1 are set to 1Note, these pins synchronize to the ALE and a control signal is output. This pin inputs the edge triggering (falling edge) nonmaskable interrupt. Note Pull-up with the following external resistor: 4 (kΩ) ≤ R ≤ 0.4 tCYC (kΩ) Example tCYC (unit: ns) 4 (kΩ) ≤ R ≤ 26 (kΩ): tCYC = 66 (ns) at 15 MHz 4 (kΩ) ≤ R ≤ 33 (kΩ): tCYC = 83 (ns) at 12 MHz 8 µPD78C14(A) 2.2 Pin Input/Output Circuits Schematic input/output circuits of the pins are shown in Table 2-1 and figures from (1) to (11). Table 2-1. Name of Type No. Pin PA0-7 PB0-7 PC0-1 PC2/SCK PC3/INT2 PC4-7 PD0-7 PF0-7 NMI INT1 Type No. 5 5 5 8 10 5 5 5 2 9 Pin RESET RD WR ALE STOP MODE0 MODE1 AN0-3 AN4-7 VAREF Type No. 2 4 4 4 2 11 11 7 12 13 9 µPD78C14(A) (1) Type 1 VDD P-ch IN N-ch (2) Type 2 IN (3) Type 4 VDD output data P-ch OUT output disable N-ch (4) Type 5 output data Type 4 output disable IN/OUT Type 1 10 µPD78C14(A) (5) Type 7 AVDD P-ch IN AVDD + N-ch – sampling C AVSS AVSS reference voltage (from voltage tap of serial resistor string) (6) Type 8 output data output disable N-ch Type 5 IN/OUT N-ch Type 2 MCC (7) Type 9 self bias enable IN Type 1 data (8) Type 10 output data output disable N-ch self bias enable N-ch Type 5 IN/OUT Type 9 MCC 11 µPD78C14(A) (9) Type 11 IN/OUT output data N-ch Type 1 (10) Type 12 IN Type 7 Type 2 edge detection circuit (11) Type 13 IN Type 1 STOP Mode P-ch AVSS 12 µPD78C14(A) 2.3 Recommended Connections for Unused Pins Pin PA7-0 PB7-0 PC7-0 PD7-0 PF7-0 RD WR ALE STOP INT1, NMI AVDD VAREF AVSS AN7-0 Connect to AVSS or AVDD. VDD Connect to VDD or VSS. Connect to VDD. Connect to VSS. Leave unconnected. Connect to VDD or VSS via resistor. Recommended connection 13 µPD78C14(A) 3. INSTRUCTION SET 3.1 Operand Expression Format/Description Method Expression format r r1 r2 sr sr1 sr2 sr3 sr4 rp rp1 rp2 rp3 rpa rpa1 rpa2 rpa3 wa word byte bit f irf Description method V, A, B, C, D, E, H, L EAH, EAL, B, C, D, E, H, L A, B, C PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF, TXB, TM0, TM1, ZCM PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3 PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM ETM0, ETM1 ECNT, ECPT SP, B, D, H V, B, D, H, EA SP, B, D, H, EA B, D, H B, D, H, D+, H+, D–, H– B, D, H B, D, H, D+, H+, D–, H–, D+byte, H+A, H+B, H+EA, H+byte D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte 8-bit immediate data 16-bit immediate data 8-bit immediate data 3-bit immediate data CY, HC, Z NMI Note, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB Note NMI can be also described as FNMI. 14 µPD78C14(A) Remarks 1. sr to sr4 (special register) PA PB PC PD PF MA MB MC : PORT A : PORT B : PORT C : PORT D : PORT F : MODE A : MODE B : MODE C ANM CR0 to CR3 TXB RXB SMH SML MKH MKL ZCM : Tx BUFFER : Rx BUFFER : SERIAL MODE High : SERIAL MODE Low : MASK High : MASK Low : ZERO CROSS MODE EOM ETMM : TIMER/EVENT COUNTER MODE : TIMER/EVENT COUNTER OUTPUT MODE : A/D CHANNEL MODE : A/D CONVERSION RESULT 0 to 3 3. rpa to rpa3 (rp addressing) B D H D+ H+ D– H– D++ H++ : (BC) : (DE) : (HL) : (DE)+ : (HL)+ : (DE)– : (HL)– : (DE)++ : (HL)++ 2. rp to rp3 (register pair) SP B D H V EA : STACK POINTER : BC : DE : HL : VA : EXTENDED ACCUMULATOR 5. irf (interrupt flag) NMI : NMI INPUT FT0 : INTFT0 FT1 : INTFT1 F1 F2 : INTF1 : INTF2 4. f (flag) CY : CARRY HC : HALF CARRY Z : ZERO MCC : MODE CONTROL C MF MM TM0 TM1 : MODE F : MEMORY MAPPING : TIMER REG0 : TIMER REG1 FE0 : INTFE0 FE1 : INTFE1 FEIN: INTFEIN FAD : INTFAD FSR : INTFSR FST : INTFST ER : ERROR OV : OVERFLOW AN4 : ANALOG INPUT to AN7 SB : STANDBY 4 to 7 TMM : TIMER MODE ETM0 : TIMER/EVENT COUNTER REG0 ETM1 : TIMER/EVENT COUNTER REG1 ECNT : TIMER/EVENT COUNTER UPCOUNTER ECPT : TIMER/EVENT COUNTER CAPTURE D+byte : (DE+byte) H+A H+B : (HL+A) : (HL+B) H+EA : (HL+EA) H+byte : (HL+byte) 15 µPD78C14(A) 3.2 Instruction Code Description r R2 0 0 0 0 1 1 1 1 sr S5 S4 S3 S2 S1 S0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Special-reg PA PB PC PD PF MKH MKL ANM SMH SML EOM ETMM TMM MM MCC MA MB MC MF TXB RXB TM0 TM1 CR0 CR1 CR2 CR3 ZCM R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 reg V A B C D E H L r1 T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 reg EAH EAL B C D E H L rpa A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 1 0 1 0 1 addressing (BC) (DE) (HL) (DE)+ (HL)+ (DE)– (HL)– (DE+byte) (HL+A) (HL+B) (HL+EA) (HL+byte) r2 r rpa1 rpa rpa2 sr1 sr2 rpa3 C3 0 0 0 0 1 1 1 1 1 C2 0 0 1 1 0 1 1 1 1 C1 1 1 0 0 1 0 0 1 1 C0 0 1 0 1 1 0 1 0 1 addressing (DE) (HL) (DE)++ (HL)++ (DE+byte) (HL+A) (HL+B) (HL+EA) (HL+byte) sr irf I4 I3 00 00 00 00 00 00 00 00 01 01 01 01 01 10 10 10 10 10 rp1 I2 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 f Q1 0 0 1 1 0 Q0 0 1 0 1 0 reg-pair VA BC DE HL EA F2 0 0 0 1 F1 0 1 1 0 F0 0 0 1 0 flag — CY HC Z I0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 INTF NMI FT0 FT1 F1 F2 FE0 FE1 FEIN FAD FSR FST ER OV AN4 AN5 AN6 AN7 SB sr3 U0 0 1 Special-reg ETM0 ETM1 sr4 V0 0 1 Special-reg ECNT ECPT rp P2 0 0 0 0 1 P1 0 0 1 1 0 P0 0 1 0 1 0 reg-pair SP BC DE HL EA Q2 0 0 0 0 1 rp rp2 rp3 16 µPD78C14(A) 3.3 Instruction Execution Time In the following table, one state consists of three clock cycles. So, when the 15 MHz clock is used, one state becomes 200 ns (= 3 x 1/15 µs). Execution time of the 4-state instruction, the shortest instruction, becomes 0.8 µs. 17 Instruction group 8-bit data transfer 16-bit data transfer 18 Instruction code Mnemonic Operand B1 r1, A A, r1 * MOV * A, sr1 r, word word, r * MVI sr2, byte MVIW MVIX STAW LDAW STAX LDAX EXX EXA EXH BLOCK rp3, EA DMOV EA, rp3 1 0 1 0 0 1 P1 P0 4 EAL ← rp3L, EAH ← rp3H * * * * * * wa, byte rpa1, byte wa wa rpa2 rpa2 01100100 01110001 0 1 0 0 1 0 A1 A0 01100011 00000001 A3 0 1 1 1 A2 A1 A0 A3 0 1 0 1 A2 A1 A0 00010001 00010000 01010000 00110001 1 0 1 1 0 1 P1 P0 S3 0 0 0 0 S2 S1 S0 Offset Data Offset Offset Data Data Note 1 State B2 B3 B4 4 4 1 1 S5 S4 S3 S2 S1 S0 1 1 S5 S4 S3 S2 S1 S0 0 1 1 0 1 R2 R1 R0 0 1 1 1 1 R2 R1 R0 Data Data Data Low Adrs Low Adrs High Adrs High Adrs 10 10 17 17 7 14 13 10 10 10 Note 3 Operation r1 ← A A ← r1 sr ← A A ← sr1 r ← (word) (word) ← r r ← byte sr2 ← byte (V. wa) ← byte (rpa1) ← byte (V. wa) ← A A ← (V. wa) (rpa2) ← A A ← (rpa2) ↔ {B ↔ B', C ↔ C', D ↔ LD' ' E ↔ E', H ↔ H', L V, A ↔ V', A', EA ↔ EA' H, L ↔ H', L' (DE)+ ← (HL)+, C ← C–1 End if borrow rp3L ← EAL, rp3H ← EAH Skip condition 0 0 0 1 1 T2 T1 T0 0 0 0 0 1 T2 T1 T0 01001101 01001100 01110000 01110000 0 1 1 0 1 R2 R1 R0 sr, A r, byte 7/13 Note 3 Note 1 7/13 4 4 4 13 (C+1) 4 µPD78C14(A) Instruction group Instruction code Mnemonic Operand B1 sr3, EA DMOV EA, sr4 SBCD SDED SHLD SSPD word word word word rpa3 word word word word rpa3 rp1 rp1 * rp2, word 01001000 1 0 1 1 0 Q2 Q1 Q0 1 0 1 0 0 Q2 Q1 Q0 0 P2 P1 P0 0 1 0 0 01001000 A, r ADD r, A A, r ADC r, A 0101 8 r ← r+A+CY 0100 1101 8 8 r ← r+A A ← A+r+CY 01100000 Low Byte 10101000 1 1 0 0 0 R2 R1 R0 High Byte 01001000 01110000 01110000 1 1 0 0 0 0 0 V0 00011110 00101110 00111110 00001110 1 0 0 1 C3 C2 C1 C0 00011111 00101111 00111111 00001111 1 0 0 0 C3 C2 C1 C0 Data Note 2 State B2 1 1 0 1 0 0 1 U0 B3 B4 14 14 Low Adrs High Adrs 20 20 20 20 Data Note 2 Note 3 Operation sr3 ← EA EA ← sr4 (word) ← C, (word+1) ← B (word) ← E, (word+1) ← D (word) ← L, (word+1) ← H (word) ← SPL, (word+1) ← SPH (rpa3) ← EAL, (rpa3+1) ← EAH C ← (word), B ← (word+1) E ← (word), D ← (word+1) L ← (word), H ← (word+1) SPL ← (word), SPH ← (word+1) EAL ← (rpa3), EAH ← (rpa3+1) (SP–1) ← rp1H, (SP–2) ← rp1L SP ← SP–2 rp1L ← (SP), rp1H ← (SP+1) SP ← SP+2 rp2 ← word C ← (PC+3+A) B ← (PC+3+A+1) Skip condition 01001000 16-bit data transfer STEAX LBCD LDED LHLD LSPD LDEAX PUSH POP LXI TABLE 14/20 High Adrs 20 20 20 20 Note 3 Low Adrs 14/20 13 10 10 17 8 µPD78C14(A) 8-bit arithmetic operation (register) A ← A+r 19 Instruction group 8-bit arithmetic operation (register) 20 Instruction code Mnemonic Operand B1 A, r ADDNC r, A A, r SUB r, A A, r SBB r, A A, r SUBNB r, A A, r ANA r, A A, r ORA r, A A, r XRA r, A A, r GTA r, A A, r LTA r, A A, r NEA r, A 0110 8 r–A No Zero 0011 1110 8 8 r–A A–r 0010 1011 8 8 r–A–1 A–r 0001 1 0 1 0 1 R2 R1 R0 8 8 0001 1 0 0 1 0 R2 R1 R0 8 8 r←r A A←A r r←r A A–r–1 0000 1001 8 8 r←r A A←A r 0011 1 0 0 0 1 R2 R1 R0 8 8 r ← r–A A←A r 0111 1011 8 8 r ← r–A–CY A ← A–r No Borrow No Borrow 0110 1111 8 8 r ← r–A A ← A–r–CY 0010 1110 8 8 r ← r+A A ← A–r 01100000 B2 1 0 1 0 0 R2 R1 R0 B3 B4 8 A ← A+r State Operation Skip condition No Carry No Carry < > < > > > No Borrow No Borrow Borrow µPD78C14(A) Borrow No Zero Instruction group Instruction code Mnemonic Operand B1 A, r EQA r, A ONA OFFA ADDX ADCX ADDNCX SUBX SBBX A, r A, r rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa 01110000 0111 1100 1101 1 1 0 0 0 A2 A1 A0 1101 1010 1110 1111 1011 1 0 0 0 1 A2 A1 A0 1001 1 0 0 1 0 A2 A1 A0 1 0 1 0 1 A2 A1 A0 1011 1110 1111 1100 1101 8 8 8 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 r–A Ar Ar A ← A+(rpa) A ← A+(rpa)+CY A ← A+(rpa) A ← A–(rpa) A ← A–(rpa)–CY A ← A–(rpa) A ← A (rpa) A ← A (rpa) A ← A (rpa) A–(rpa)–1 A–(rpa) A–(rpa) A–(rpa) A (rpa) A (rpa) < < > > < < < State B2 1 1 1 1 1 R2 R1 R0 B3 B4 8 A–r Operation Skip condition 8-bit arithmetic operation (register) 01100000 Zero Zero No Zero Zero No Carry 8-bit arithmetic operation (memory) SUBNBX ANAX ORAX XRAX GTAX LTAX NEAX EQAX ONAX OFFAX No Borrow No Borrow Borrow µPD78C14(A) No Zero Zero No Zero Zero 21 Instruction group Arithmetic operation of immediate data 22 Instruction code Mnemonic Operand B1 * ADI A, byte r, byte sr2, byte * ACI A, byte r, byte sr2, byte * ADINC A, byte r, byte sr2, byte * SUI A, byte r, byte sr2, byte * SBI A, byte r, byte sr2, byte * SUINB A, byte r, byte sr2, byte * A, byte r, byte 01000110 01110100 0110 01010110 01110100 0110 00100110 01110100 0110 01100110 01110100 0110 01110110 01110100 0110 00110110 01110100 0110 00000111 01110100 B2 Data 0 1 0 0 0 R2 R1 R0 S3 1 0 0 0 S2 S1 S0 Data 0 1 0 1 0 R2 R1 R0 S3 1 0 1 0 S2 S1 S0 Data 0 0 1 0 0 R2 R1 R0 S3 0 1 0 0 S2 S1 S0 Data 0 1 1 0 0 R2 R1 R0 S3 1 1 0 0 S2 S1 S0 Data 0 1 1 1 0 R2 R1 R0 S3 1 1 1 0 S2 S1 S0 Data 0 0 1 1 0 R2 R1 R0 S3 0 1 1 0 S2 S1 S0 Data 0 0 0 0 1 R2 R1 R0 Data Data Data Data Data Data Data B3 B4 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11 A ← A+byte r ← r+byte sr2 ← sr2+byte A ← A+byte+CY r ← r+byte+CY sr2 ← sr2+byte+CY A ← A+byte r ← r+byte sr2 ← sr2+byte A ← A–byte r ← r–byte sr2 ← sr2–byte A ← A–byte–CY r ← r–byte–CY sr2 ← sr2–byte–CY A ← A–byte r ← r–byte sr2 ← sr2–byte A← A r←r byte No Borrow No Borrow No Borrow No Carry No Carry No Carry State Operation Skip condition µPD78C14(A) < ANI byte < Instruction group Instruction code Mnemonic Operand B1 ANI * ORI sr2, byte A, byte r, byte sr2, byte * XRI A, byte r, byte sr2, byte * GTI A, byte r, byte sr2, byte * LTI A, byte r, byte sr2, byte * NEI A, byte r, byte sr2, byte * EQI A, byte r, byte sr2, byte 01100100 00010111 01110100 0110 00010110 01110100 0110 00100111 01110100 0110 00110111 01110100 0110 01100111 01110100 0110 01110111 01110100 0110 B2 S3 0 0 0 1 S2 S1 S0 Data 0 0 0 1 1 R2 R1 R0 S3 0 0 1 1 S2 S1 S0 Data 0 0 0 1 0 R2 R1 R0 S3 0 0 1 0 S2 S1 S0 Data 0 0 1 0 1 R2 R1 R0 S3 0 1 0 1 S2 S1 S0 Data 0 0 1 1 1 R2 R1 R0 S3 0 1 1 1 S2 S1 S0 Data 0 1 1 0 1 R2 R1 R0 S3 1 1 0 1 S2 S1 S0 Data 0 1 1 1 1 R2 R1 R0 S3 1 1 1 1 S2 S1 S0 Data Data Data Data Data Data B3 Data B4 20 7 11 20 7 11 20 7 11 14 7 11 14 7 11 14 7 11 14 sr2 ← sr2 byte A ← A byte r ← r byte sr2 ← sr2 byte A ← A byte r ← r byte < < < < < < State Operation Skip condition Arithmetic operation of immediate data sr2 ← sr2 byte < A–byte–1 r–byte–1 sr2–byte–1 A–byte r–byte sr2–byte A–byte r–byte sr2–byte A–byte r–byte sr2–byte No Borrow No Borrow No Borrow Borrow Borrow Borrow No Zero No Zero No Zero Zero Zero Zero µPD78C14(A) 23 Instruction group Arithmetic operation of immediate data Arithmetic operation of working register 24 Instruction code Mnemonic Operand B1 * ONI A, byte r, byte sr2, byte * OFFI A, byte r, byte sr2, byte ADDW ADCW ADDNCW SUBW SBBW SUBNBW ANAW ORAW XRAW GTAW LTAW NEAW EQAW ONAW wa wa wa wa wa wa wa wa wa wa wa wa wa wa 01000111 01110100 0110 01010111 01110100 0110 01110100 B2 Data 0 1 0 0 1 R2 R1 R0 S3 1 0 0 1 S2 S1 S0 Data 0 1 0 1 1 R2 R1 R0 S3 1 0 1 1 S2 S1 S0 11000000 1101 1010 1110 1111 1011 10001000 1001 10010000 10101000 1011 1110 1111 1100 offset Data Data B3 B4 7 11 14 7 11 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 A byte r byte sr2 byte A byte r byte sr2 byte A ← A+(V.wa) A ← A+(V.wa)+CY A ← A+(V.wa) A ← A–(V.wa) A ← A–(V.wa)–CY A ← A–(V.wa) A ← A (V.wa) A ← A (V.wa) A ← A (V.wa) A–(V.wa)–1 A–(V.wa) A–(V.wa) A–(V.wa) A (V.wa) < > > < < < < < < < State Operation Skip condition No Zero No Zero No Zero Zero Zero Zero No Carry No Borrow No Borrow Borrow No Zero Zero No Zero µPD78C14(A) Instruction group Instruction code Mnemonic Operand B1 OFFAW wa * * * * * * * * wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte EA, r2 EA, rp3 EA, rp3 EA, rp3 EA, r2 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 0000 0100 01110100 00000101 0001 0010 0011 0110 0111 0100 0101 01110000 0100 0 1 0 0 0 0 R1 R0 1 1 0 0 0 1 P1 P0 1101 1010 0 1 1 0 0 0 R1 R0 1 1 1 0 0 1 P1 P0 1111 1011 1 0 0 0 1 1 P1 P0 1001 1 0 0 1 0 1 P1 P0 B2 11011000 Offset B3 Offset Data B4 14 19 19 13 13 13 13 13 13 11 11 11 11 11 11 11 11 11 11 11 A (V.wa) (V.wa) ← (V.wa) byte State Operation Skip condition Zero < Arithmetic operation of working register ANIW ORIW GTIW LTIW NEIW EQIW ONIW OFFIW EADD DADD DADC (V.wa) ← (V.wa) byte < > (V.wa)–byte–1 (V.wa)–byte (V.wa)–byte (V.wa)–byte (V.wa) byte (V.wa) byte EA ← EA+r2 EA ← EA+rp3 EA ← EA+rp3+CY EA ← EA+rp3 EA ← EA–r2 EA ← EA–rp3 EA ← EA–rp3–CY No Borrow Borrow No Zero Zero No Zero Zero < < 16-bit arithmetic operation DADDNC ESUB DSUB DSBB DSUBNB DAN DOR DXR No Carry µPD78C14(A) EA ← EA–rp3 EA ← EA rp3 EA ← EA rp3 EA ← EA rp3 No Borrow < > < 25 Instruction group 16-bit arithmetic operation Multiply/ divide Decrement/Increment Other arithmetic operation 26 Instruction code Mnemonic Operand B1 DGT DLT DNE DEQ DON DOFF MUL DIV INR INRW * EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 r2 r2 r2 wa rp INX EA DCR DCRW * r2 wa rp DCX EA DAA STC CLC NEGA 10101001 01100001 01001000 00101011 00101010 00111010 7 4 8 8 8 EA ← EA–1 Decimal Adjust Accumulator CY ← 1 CY ← 0 A ← A+1 10101000 0 1 0 1 0 0 R1 R0 00110000 0 0 P1 P0 0 0 1 1 Offset 7 4 16 7 EA ← EA+1 r2 ← r2–1 (V.wa) ← (V.wa)–1 rp ← rp–1 0 1 0 0 0 0 R1 R0 00100000 0 0 P1 P0 0 0 1 0 Offset 01001000 01110100 B2 1 0 1 0 1 1 P1 P0 1011 1110 1111 1100 1101 0 0 1 0 1 1 R1 R0 0011 B3 B4 11 11 11 11 11 11 32 59 4 16 7 EA–rp3–1 EA–rp3 EA–rp3 EA–rp3 EA rp3 EA rp3 EA ← A×r2 EA ← EA÷r2, r2 ← The Remainder r2 ← r2+1 (V.wa) ← (V.wa)+1 rp ← rp+1 < < State Operation Skip condition No Borrow Borrow No Zero Zero No Zero Zero Carry Carry Borrow Borrow µPD78C14(A) Instruction group Instruction code Mnemonic Operand B1 RLD RRD RLL RLR SLL r2 r2 r2 r2 r2 r2 EA EA EA EA * word 01010100 00100001 word * word 11 jdisp 1 jdisp 00101000 Low Adrs 00101001 fa High Adrs 01001000 B2 00111000 1001 0 1 R1 R0 0 0 R1 R0 0 0 1 0 0 1 R1 R0 0 0 R1 R0 0 0 0 0 0 1 R1 R0 0 0 R1 R0 10110100 0000 10100100 0000 Low Adrs High Adrs B3 B4 17 17 8 8 8 8 8 8 8 8 8 8 10 4 10 10 8 16 17 13 Rotate Left Digit Rotate Right Digit r2m+1 ← r2m, r20 ← CY, CY ← r27 r2m—1 ← r2m, r27 ← CY, CY ← r20 r2m+1 ← r2m, r20 ← 0, CY ← r27 r2m—1 ← r2m, r27 ← 0, CY ← r20 r2m+1 ← r2m, r20 ← 0, CY ← r27 r2m—1 ← r2m, r27 ← 0, CY ← r20 EAn+1 ← EAn, EA0 ← CY, CY ← EA15 EAn—1 ← EAn, EA15 ← CY, CY ← EA0 EAn+1 ← EAn, EA0 ← 0, CY ← EA15 EAn—1 ← EAn, EA15 ← 0, CY ← EA0 PC ← word PCH ← B, PCL ← C PC ← PC+1+jdisp 1 PC ← PC+2+jdisp State Operation Skip condition Rotation shift SLR SLLC SLRC DRLL DRLR DSLL DSLR JMP JB Carry Carry Jump JR JRE JEA CALL * 0100111 01001000 µPD78C14(A) PC ← EA (SP–1) ← (PC+3)H, (SP–2) ← (PC+3)L PC ← word, SP ← SP–2 (SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L PCH ← B, PCL ← C, SP ← SP–2 (SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L PC15–11 ← 00001, PC10–0 ← fa, SP ← SP–2 word 01000000 01001000 Call CALB CALF * word 01111 27 Instruction group Call Return Skip CPU operation 28 Instruction code Mnemonic Operand B1 CALT SOFT1 RET RETS RETI BIT SK SKN SKIT SKNIT NOP EI DI HLT STOP * bit, wa f f irf irf 00000000 10101010 10111010 01001000 01001000 00111011 10111011 word 100 ta B2 B3 B4 16 16 10 10 13 Offset 0 0 0 0 1 F2 F1 F0 0001 0 1 0 I4 I3 I2 I1 I0 0 1 1 I4 I3 I2 I1 I0 10 8 8 8 8 4 4 4 12 12 (SP–1) ← (PC+1)H, (SP– 2) ← (PC+1)L, PCL ← (128+2ta), PCH ← (129+2ta), SP ← SP–2 (SP–1) ← PSW, (SP–2) ← (PC+1)H, (SP–3) ← (PC+1)L, PC ← 0060H, SP ← SP–3 PCL ← (SP), PCH ← (SP+1) SP ← SP+2 PCL ← (SP), PCH ← (SP+1), SP ← SP+2 PC ← PC+n PCL ← (SP), PCH ← (SP+1) PSW ← (SP+2), SP ← SP+3 Skip if (V.wa) bit = 1 Skip if f = 1 Skip if f = 0 Skip if irf = 1, then reset irf Skip if irf = 0 Reset irf, if irf = 1 No Operation Enable Interrupt Disable Interrupt Set Halt Mode Set Stop Mode (V.wa) bit = 1 f=1 f=0 irf = 1 irf = 0 Unconditional State Operation Skip condition 01110010 10111000 1001 01100010 0 1 0 1 1 B2 B1 B0 01001000 Notes 1. B2 (Data) is applied for rpa2 = D + byte or H + byte. 2. B3 (Data) is applied for rpa3 = D + byte or H + byte. 3. In the "state" column, data to the right of the slash applies when rpa2 or rpa3 is D + byte, H + A, H + B, H + EA, or H + byte. µPD78C14(A) Remark When the instructions below are skipped, the number of idle states is as listed below and differs from the number of execution states. 3-byte instruction (with *) : 10-state 1-byte instruction : 4-state : 11-state 3-byte : 7-state 2-byte (with *) : 14-state 4-byte : 8-state 2-byte µPD78C14(A) 4. LIST OF MODE REGISTERS Name of mode register MA MB MCC MC MM MF TMM ETMM EOM SML SMH MKL MKH ANM ZCM A/D Channel Mode Zero-cross Mode R/W W Specifies operation mode of the A/D converter Specifies operation mode of the zero-cross detection circuit Interrupt Mask MODE A MODE B MODE CONTROL C MODE C MEMORY MAPPING MODE F Timer mode Timer/Event Counter Mode Timer/Event Counter Output Mode Serial Mode W R/W R/W Specifies interrupt request enable/disable Specifies operation mode of the serial interface R/W Controls output level of CO0 and CO1 Read/Write W W W W W W R/W W Function Specifies input/output of Port A in bit units Specifies input/output of Port B in bit units Specifies port/control mode of Port C in bit units Specifies input/output of Port C set in the port mode in bit units Specifies port/expansion mode of Ports D and F Specifies input/output of Port F set in the port mode in bit units Specifies operation mode of the timer Specifies operation mode of the Timer Event Counter 29 µPD78C14(A) 5. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C) Parameter Power Supply Voltage Symbol VDD AVDD AVSS Input Voltage Output Voltage Output Current Low Output Current High A/D Converter Reference Input Voltage Operating Ambient Temperature Storage Temperature Tstg –65 to +150 ˚C TA –40 to +85 ˚C VI VO IOL IOH VAREF All Output Pin All Output Pin Total All Output Pin All Output Pin Total Test Condition Ratings –0.5 to +7.0 AVSS to VDD + 0.5 –0.5 to +0.5 –0.5 to VDD + 0.5 –0.5 to VDD + 0.5 4.0 100 –2.0 –50 –0.5 to AVDD + 0.3 Unit V V V V V mA mA mA mA V * Caution If any of the parameters exceeds the absolute maximum ratings even for a moment, this may damage product quality. The absolute maximum ratings are values that may physically damage the product. You must use the product within the specified ratings. 30 µPD78C14(A) Oscillation Characteristics (TA = –40 to +85 ˚C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V, VDD – 0.8 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD) Resonator Ceramic Resonator or Crystal ResonatorNote C1 C2 X1 X2 Recommended Circuits Parameter Test Conditions Not used MIN. 4 MAX. 15 UNIT MHz Oscillation Frequency (fxx) A/D Converter A/D Converter Used 5.8 15 MHz External Clock X1 X2 X1 Input Frequency (fx) A/D Converter Not used A/D Converter Used 4 5.8 0 20 15 15 20 250 MHz MHz ns ns X1 Input Rise, Fall Time (tr, tf) HCMOS Inverter X1 Input High, Low Level Width (tøH, tøL) Cautions 1. Oscillator circuit should be in the nearest area from X1 and X2 pins. 2. Do not place other signal lines within the area enclosed with broken lines. Note For a crystal resonator, the following external capacitances are recommended: C1 = C2 = 10 pF CAPACITANCE (TA = 25 ˚C, VDD = VSS = 0 V) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CI CO CIO Test Condition fC = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 10 20 20 UNIT pF pF pF 31 µPD78C14(A) DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V) Parameter Input Low Voltage Symbol VIL1 VIL2 Input High Voltage VIH1 VIH2 Output Low Voltage VOL Test Condition All except RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4 RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4 0 All except RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4, X1, X2 RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4, X1, X2 IOL = 2.0 mA IOH = –1.0 mA IOH = –100 µA Input Current Input Leakage Current Output Leakage Current AVDD Supply Current VDD Supply Current Data Retention Voltage Data Retention Current Notes 1. 2. 3. IDDDR Hardware/Software Note 3 STOP Mode When self-bias is generated by ZCM register. When set in the control mode by MCC register and self-bias is generated by ZCM register. When self-bias is not generated. VDDDR = 2.5 V VDDDR = 5 V ± 10 % 1 10 15 50 AIDD1 AIDD2 IDD1 IDD2 VDDDR Operation Mode fxx = 15 MHz STOP Mode Operation mode fxx = 15 MHz HALT Mode fxx = 15 MHz Hardware/Software STOP Mode 2.5 0.5 10 16 8 1.3 20 30 15 mA ILO II ILI INT1 Note 1 MIN. 0 TYP. MAX. 0.8 0.2VDD VDD VDD 0.45 UNIT V V V V V V V 2.2 0.8VDD Output High Voltage VOH VDD – 1.0 VDD – 0.5 Note 2 , TI (PC3) ; 0 V ≤ VI ≤ VDD ±200 ±10 ±1 ±10 µA µA µA µA All except INT1, TI (PC3), AN7 to AN0; 0 V ≤ VI ≤ VDD AN7 to AN0; 0 V ≤ VI ≤ VDD 0 V ≤ VO ≤ VDD µA mA mA V µA µA 32 µPD78C14(A) AC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V) READ/WRITE OPERATION: Parameter X1 Input Cycle Time Address Setup Time to ALE Address Hold Time after ALE ↓ Address → RD ↓ Delay Time RD ↓ → Address Floating Time Address → Data Input Time ALE ↓ → Data Input Time RD ↓ → Data Input Time ALE ↓ → RD ↓ Delay Time Data Hold Time after RD ↑ RD ↑ → ALE ↑ Delay Time RD Width Low Symbol tCYC tAL tLA tAR tAFR tAD tLDR tRD tLR tRDH tRL tRR CL = 150 pF fxx = 15 MHz, CL = 150 pF Data Read fxx = 15 MHz, CL = 150 pF OP code Fetch fxx = 15 MHz, CL = 150 pF ALE Width High M1 Setup Time to ALE ↓ M1 Hold Time after ALE ↓ IO/M Setup Time to ALE ↓ IO/M Hold Time after ALE ↓ Address → WR ↓ Delay Time ALE ↓ → Data Output Time WR ↓ → Data Output Time ALE ↓ → WR ↓ Delay Time Data Setup Time to WR ↑ Data Hold Time after WR ↑ WR ↑ → ALE ↑ Delay Time WR Width Low tLL tML tLM tIL tLI tAW tLDW tWD tLW tDW tWDH tWL tWW CL = 150 pF fxx = 15 MHz, CL = 150 pF 15 165 60 80 215 fxx = 15 MHz, CL = 150 pF fxx = 15 MHz, CL = 150 pF fxx = 15 MHz 90 30 35 30 35 100 180 100 ns ns ns ns ns ns ns ns ns ns ns ns ns 415 ns 15 0 80 215 CL = 150 pF fxx = 15 MHz, CL = 150 pF fxx = 15 MHz, CL = 150 pF Test Condition MIN. 66 30 35 100 20 250 135 120 MAX. 250 UNIT ns ns ns ns ns ns ns ns ns ns ns ns 33 µPD78C14(A) SERIAL OPERATION: Parameter SCK Cycle Time Symbol tCYK Test Condition SCK Input SCK Output SCK Width Low tKKL SCK Input SCK Output SCK Width High tKKH SCK Input SCK Output RxD Setup Time to SCK ↑ RxD Hold Time After SCK ↑ SCK ↓ → TxD Delay Time Notes 1. 2. tRXK tKRX tKTX Note 1 Note 1 Note 1 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 MIN. 800 400 1.6 335 160 700 335 160 700 80 80 210 MAX. UNIT ns ns µs ns ns ns ns ns ns ns ns ns In case of x1 clock rate in asynchronous mode, synchronous mode, or I/O interface mode. In case of x16 or x64 clock rate in asynchronous mode. Remark The numeric values in the table apply when fXX = 15 MHz, CL = 150 pF. ZERO-CROSS CHARACTERISTICS: Parameter Zero-Cross Detection Input Zero-Cross Accuracy Zero-Cross Detection Input Frequency OTHER OPERATION: Parameter TI Width High, Low CI Width High, Low NMI Width High, Low INT1 Width High, Low INT2 Width High, Low AN7-4 Width High, Low RESET Width High, Low Symbol tTIH, tTIL tCI1H, tCI1L tCI2H, tCI2L tNIH, tNIL tI1H, tI1L tI2H, tI2L tANH, tANL tRSH, tRSL Event Counter Mode Pulse Width Measurement Mode Test Condition MIN. 6 6 48 10 36 36 36 10 MAX. UNIT tCYC tCYC tCYC Symbol VZX AZX fZX Test Condition AC Coupled 60-Hz Sine Wave 0.05 MIN. 1 MAX. 1.8 ±135 1 UNIT VACP–P mV kHz µs tCYC tCYC tCYC µs 34 µPD78C14(A) A/D CONVERTER CHARACTERISTICS: (TA = –40 to +85 ˚C, VDD = +5.0 V ± 10 %, VSS = AVSS = 0 V, VDD – 0.5 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD) Parameter Resolution Absolute Accuracy Note Symbol Test Condition 3.4 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns 4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns TA = –10 to +70 ˚C, 4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns MIN. 8 TYP. MAX. ±0.8 % ±0.6 % ±0.4 % UNIT Bits FSR FSR FSR tCYC tCYC tCYC tCYC Conversion time Sampling Time Analog Input Voltage Reference Voltage VAREF Current AVDD Supply Current tCONV tSAMP VIAN VAREF IAREF1 IAREF2 AIDD1 AIDD2 66 ns ≤ tCYC ≤ 110 ns 110 ns ≤ tCYC ≤ 170 ns 66 ns ≤ tCYC ≤ 110 ns 110 ns ≤ tCYC ≤ 170 ns AN7-0 (include unused pins) 576 432 96 72 0 50 3.4 AVDD 1.5 0.7 0.5 10 3.0 1.5 1.3 20 VAREF V MΩ V mA mA mA Analog Input Impedance RAN Operation mode STOP mode Operation mode, fxx = 15 MHz STOP mode * µA Note Except quantization error (i.e. ±1/2 LSB). AC TIMING TEST POINTS VDD – 1.0 V 0.45 V 2.2 V 0.8 V Test points 2.2 V 0.8 V 35 µPD78C14(A) AC CHARACTERISTIC CALCULATING EXPRESSION depending on tCYC Symbol tAL tLA tAR tAD tLDR tRD tLR tRL tRR tLL tML tLM tIL tLI tAW tLDW tLW tDW tWDH tWL tWW tCYK tKKL tKKH Calculating Expression 2T – 100 T – 30 3T – 100 7T – 220 5T – 200 4T – 150 T – 50 2T – 50 4T – 50 (Data Read) 7T – 50 (OP Code Fetch) 2T – 40 2T – 100 T – 30 2T – 100 T – 30 3T – 100 T + 110 T – 50 4T – 100 2T – 70 2T – 50 4T – 50 6T (SCK Input) Note 1 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns /12T (SCK Input) Note 2 MIN. MIN. MIN. 24T (SCK Output) 2.5T + 5 (SCK Input) Note 1 /5T + 5 (SCK Input) Note 2 12T – 100 (SCK Output) 2.5T + 5 (SCK Input) Note 1 /5T + 5 (SCK Input) Note 2 12T – 100 (SCK Output) Notes 1. 2. Remarks In case of x16 or x64 clock rate in asynchronous mode. In case of x1 clock rate in asynchronous mode, synchronous mode, or I/O interface mode. 1. 2. T = tCYC = 1/fxx Symbols that cannot be found in this table do not depend on the oscillation frequency (fxx). 36 µPD78C14(A) Timing Waveform Read Operation tCYC X1 PF7-0 tAD PD7-0 address (low-order) tLL ALE tAL RD tLR tAR tML MODE1 Note 1 (M1) MODE0 (IO/M) Note 2 tIL tLM tLI tLA tAFR address (high-order) read data tLDR tRDH tRL tRD tRR Write Operation X1 PF7-0 tLDW PD7-0 address (low-order) tLL ALE tAL WR tLW tAW tIL MODE0 (IO/M) Note 3 tLI tLA address (high-order) write data tDW tWD tWW tWL tWDH Notes 1. M1 signal is output to MODE1 pin at first OP code fetch cycle if MODE1 pin is pulled up. 2. IO/M signal is output to MODE0 pin at sr to sr2 register read cycle if MODE0 pin is pulled up. 3. IO/M signal is output to MODE0 pin at sr to sr2 register write cycle if MODE0 pin is pulled up. 37 µPD78C14(A) Serial Operation tCYK tKKL SCK tKTX TXD tKKH RXD tRXK tKRX Timer Input Timing tTIH tTIL TI Timer/Event Counter Input Timing Event Counter Mode tCI1H tCI1L CI Pulse Width Measurement Mode tCI2H tCI2L CI 38 µPD78C14(A) Interrupt Input Timing tNIH tNIL NMI tI1L tI1H INT1 tI2H tI2L INT2 RESET Input Timing tRSH 0.8VDD 0.2VDD tRSL RESET External Clock Timing tφH 0.8VDD X1 0.8 V tr tCYC tf tφL 39 µPD78C14(A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 ˚C) Parameter Data retention power supply voltage Data retention power supply current Symbol VDDDR IDDDR tRVD, tFVD tSSTVD tHVDST VDDDR = 2.5 V VDDDR = 5 V ± 10 % VDD rise, fall time STOP setup time to VDD STOP hold time to VDD Note T = tCYC = 1/fxx Data Retention Timing 200 12T Note Test Condition MIN. 2.5 TYP. 1 10 + 0.5 MAX. 5.5 15 50 UNIT V µA µA µs µs µs * 12TNote + 0.5 90 % VDD 10 % tFVD tSSTVD STOP VIL2 VDDDR tRVD tHVDST VIH2 40 µPD78C14(A) 6. CHARACTERISTIC CURVES (reference value) IDD1, IDD2 vs VDD (TA = 25 ˚C, f XX = 15 MHz) 30 25 VDD Supply Current IDD1 , IDD2 [mA] IDD1 (TYP.) 20 15 10 5 IDD2 (TYP.) 0 0 4.5 5.0 5.5 Supply Voltage VDD [V] 6.0 30 IDD1, IDD2 vs fXX (TA = 25 ˚C, VDD = 5 V) VDD Supply Current IDD1, IDD2 [mA] 20 IDD1(TYP.) 10 IDD2(TYP.) 0 0 5 10 Oscillation Frequency fXX [MHz] 15 41 µPD78C14(A) IOL vs VOL 2.5 (TA = 25 ˚C, VDD = 5 V) TYP. Output Low Current IOL [mA] 2.0 1.5 1.0 0.5 0 0 0.1 0.2 0.3 Output Low Voltage VOL [V] 0.4 0.5 IOH vs VOH – 1.5 (TA = 25 ˚C, VDD = 5 V) Output High Current IOH [mA] TYP. – 1.0 – 0.5 0 0 0.5 0.1 0.2 0.3 0.4 Supply Voltage – Output High Voltage VDD – V OH [V] 42 µPD78C14(A) IDDDR vs VDDDR 10 Data Retention Supply Current IDDDR [ µ A] (TA = 25 ˚C) 8 TYP. 6 4 2 0 0 2 3 4 5 Data Retention Supply Voltage VDDDR [V] 6 43 µPD78C14(A) 7. PACKAGE DRAWINGS 64 PIN PLASTIC QUIP A 64 33 1 32 W X P S M H I M J K N C P64GQ-100-36 NOTE Each lead centerline is located within 0.25 mm (0.010 inch) of its true position (T.P.) at maximum material condition. ITEM A C H I J K M N P S W X MILLIMETERS 41.5 16.5 – 0.50 +0.10 +0.3 –0.2 INCHES 1.634+0.012 –0.008 0.650 0.020 +0.004 –0.005 0.010 0.100 (T.P.) 0.050 (T.P.) 0.043+0.011 –0.006 0.010 +0.004 –0.003 0.157+0.013 –0.012 0.142 –0.005 0.950 – +0.042 +0.042 +0.004 0.25 2.54 (T.P.) 1.27 (T.P.) 1.1 +0.25 –0.15 +0.10 0.25 –0.05 +0.3 4.0 – 3.6 – +0.1 – 24.13 +1.05 – 19.05 +1.05 0.750 – 44 µPD78C14(A) 64 PIN PLASTIC QFP (14 × 20) A B 51 52 33 32 detail of lead end C D S 64 1 20 19 F G H IM J K P N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 ± 0.4 20.0 ± 0.2 14.0 ± 0.2 17.6 ± 0.4 1.0 1.0 0.40 ± 0.10 0.20 1.0 (T.P.) 1.8 ± 0.2 0.8 ± 0.2 0.15+0.10 –0.05 0.12 2.7 0.1 ± 0.1 3.0 MAX. INCHES 0.929 ± 0.016 0.795+0.009 –0.008 0.551+0.009 –0.008 0.693 ± 0.016 0.039 0.039 0.016 +0.004 –0.005 0.008 0.039 (T.P.) 0.071–0.009 0.031+0.009 –0.008 0.006+0.004 –0.003 0.005 0.106 0.004 ± 0.004 0.119 MAX. +0.008 M 5°±5° Q 45 µPD78C14(A) 68 PIN PLASTIC QFJ ( 950 mil) A B F E U G H J T K M N M Q I P C D 68 1 P68L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K M N P Q T U MILLIMETERS 25.2 ± 0.2 24.20 24.20 25.2 ± 0.2 1.94 ± 0.15 0.6 4.4 ± 0.2 2.8 ± 0.2 0.9 MIN. 3.4 1.27 (T.P.) 0.40 ± 1.0 0.12 23.12 ± 0.20 0.15 R 0.8 0.20 +0.10 –0.05 INCHES 0.992 ± 0.008 0.953 0.953 0.992 ± 0.008 0.076+0.007 –0.006 0.024 0.173+0.009 –0.008 0.110+0.009 –0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 –0.005 0.005 0.910+0.009 –0.008 0.006 R 0.031 0.008+0.004 –0.002 46 µPD78C14(A) 8. RECOMMENDED SOLDERING CONDITIONS Solder the µPD78C14(A) under the recommended conditions listed below. For details of the recommended conditions for soldering, please refer to Semiconductor Device Mounting Technology Manual (IEI-1207). Consult an NEC sales representative about soldering methods and soldering conditions other than listed below. Table 8-1. Soldering Conditions for Surface Mount Type (1) µPD78C14GF(A)-xxx-3BE: 64-pin plastic QFP (14 x 20 mm) Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 235 ˚C, Time: Within 30 s (at 210 ˚C or higher), Count: Twice or less (1) Perform the second reflow when the device temperature has come down to the room temperature from the heating from the first reflow. (2) Do not wash the soldered portion with the flux following the first reflow. VPS Package peak temperature: 215 ˚C, Time: Within 40 s (at 200 ˚C or higher), Count: Twice or less (1) Perform the second reflow when the device temperature has come down to the room temperature from the heating from the first reflow. (2) Do not wash the soldered portion with the flux following the first reflow. Wave soldering Soldering bath temperature: 260 ˚C or less, Time: Within 10 s, Count: Once, Preheating temperature: 120 ˚C MAX. (package surface temperature) Partial heating Pin temperature: 300 ˚C or less, Time: Within 3 s (per pin row) — WS60-00-1 VP15-00-2 Recommended Condition Symbol IR35-00-2 * Caution Do not use several soldering methods together (except partial heating). (2) µPD78C14L (A)-xxx: 68-pin plastic QFJ (950 x 950 mil) Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 230 ˚C, Time: Within 30 s (at 210 ˚C or higher), Count: Once, Maximum number of days: Seven prebaking at 125 ˚C is required for 10 hours) VPS Package peak temperature: 215 ˚C, Time: Within 40 s (at 200 ˚C or higher), Count: Once, Maximum number of days: Seven Note (after seven days, prebaking at 125 ˚C is required for 10 hours) Partial heating Note Pin temperature: 300 ˚C or less, Time: Within 3 s (per pin row) — VP15-107-1 Note Recommended Condition Symbol IR30-107-1 (after seven days, Number of storage days under the storage conditions of 25 ˚C and 65 % RH or less after the dry pack is opened. Caution Do not use several soldering methods together (except partial heating). 47 µPD78C14(A) Table 8-2. Soldering Conditions for Hole-Through Type µPD78C14G(A)-xxx-36: 64-pin plastic QUIP Soldering Method Wave Soldering (pin part only) Partial heating Soldering Conditions Soldering bath temperature: 260 ˚C or less, Time: Within 10 s Pin temperature: 300 ˚C or less, Time: Within 3 s (per pin row) Caution Apply wave soldering only to pins and be careful not to bring solder directly in contact with the package. 48 µPD78C14(A) APPENDIX DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD78C14(A): Language processor 87AD series relocatable assembler (RA87) This relocatable assembler is a program which converts a program written in mnemonics into object code that can be executed by microcontroller. In addition, it contains the automatic function of symbol table generation and branch instruction optimization processing. Host machine OS PC-9800 series IBM PC/ATTM MS-DOSTM (Ver. 2.11 to Ver. 5.00A Note) PC DOSTM (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC 5-inch 2HC Ordering code (product name) * µS5A13RA87 µS5A10RA87 µS7B13RA87 µS7B10RA87 PROM write tools Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single chip microcontrollers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256 Kbits to 4 Mbits. PA-78CP14GQ Software PG-1500 controller PROM programmer adapter for the µPD78CP14(A) and connected to PG-1500 for use. PG-1500 and a host machine are connected by a serial or parallel interface and PG-1500 is controlled on the host machine. Host machine OS PC-9800 series IBM PC/AT MS-DOS (Ver. 2.11 to Ver. 5.00A Note) PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HD 5-inch 2HC Ordering code (product name) µS5A13PG1500 µS5A10PG1500 µS7B13PG1500 µS7B10PG1500 Note Ver. 5.00/500A have task swap function. However, this function is not supported by this software. Remark Operations of the assembler and PG-1500 controller are guaranteed only on the host machines under the operating systems listed above. 49 µPD78C14(A) Debugging tools In-circuit emulator (IE-78C11-M) is provided for µPD78C14(A) program debugging tools. The system configuration is listed below: Hardware Software IE-78C11-M control program (IE controller) IE-78C11-M IE-78C11-M is an in-circuit emulator for the 87AD series. IE-78C11-M can be connected to a host machine efficient debugging. IE-78C11-M and a host machine are connected by RS-232-C and IE-78C11-M is controlled on the host machine. Host machine OS PC-9800 series IBM PC/AT MS-DOS (Ver. 2.11 to Ver. 3.30D) PC DOS (Ver. 3.1) Remark Operation of IE controller is guaranteed only on the host machine under the operating systems listed above. Distribution media 3.5-inch 2HD 5-inch 2HD 5-inch 2HC Ordering code (product name) µS5A13IE78C11 µS5A10IE78C11 µS7B10IE78C11 50 µPD78C14(A) NOTES FOR CMOS DEVICES (1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. (2) HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. 51 µPD78C14(A) The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 52