UPD8882

DATA SHEET MOS INTEGRATED CIRCUIT μ PD8882 (10680 + 10680) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The μ PD8882 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The μ PD8882 has 3 rows of (10680 + 10680) staggered pixels, and each row has a dual-sided readout-type charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 2400 dpi/A4 color image scanners. FEATURES • Valid photocell • Photocell’s size • Line spacing • Color filter • Resolution : (10680 + 10680) staggered pixels × 3 : 2.7 μ m × 5.4 μ m : 86.4 μ m (16 lines) Red line - Green line, Green line - Blue line 43.2 μ m (8 lines) Odd line - Even line (for each color) : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) : 96 dot/mm A4 (210 × 297 mm) size (shorter side) 2400 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate • Power supply • On-chip circuits : Built-in amplifiers : 10.0 MHz Max. CCD transfer : 4.5 MHz Max./each CCD : +12 V : Reset feed-through level clamp circuits Voltage amplifiers 7 ORDERING INFORMATION Part Number Package CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) μ PD8882CY-A Remark The μ PD8882CY-A is a lead-free product. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17085EJ2V0DS00 (2nd edition) Date Published May 2005 NS CP (K) Printed in Japan The mark shows major revised points. 2004 μ PD8882 BLOCK DIAGRAM VOD GND GND φ RB 20 VOD 7 2 11 3 CCD analog shift register Transfer gate Photocell (Blue-odd) Transfer gate CCD analog shift register φ2 φ1 14 15 13 φ TG1 VOUT1 21 CCD analog shift register Transfer gate Photocell (Blue-even) Transfer gate CCD analog shift register CCD analog shift register Transfer gate Photocell (Green-odd) Transfer gate CCD analog shift register 12 φ TG2 VOUT2 22 CCD analog shift register Transfer gate Photocell (Green-even) Transfer gate CCD analog shift register CCD analog shift register Transfer gate Photocell (Red-odd) Transfer gate CCD analog shift register 10 φ TG3 VOUT3 1 CCD analog shift register Transfer gate Photocell (Red-even) Transfer gate CCD analog shift register 4 19 9 8 φ CLB φ SEL φ4 φ3 2 Data Sheet S17085EJ2V0DS μ PD8882 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) • μ PD8882CY-A Output signal 3 (Red) Ground Reset gate clock Reset feed-through level clamp clock No connection No connection Output drain voltage Shift register clock 3 Shift register clock 4 Transfer gate clock 3 (for Red) Ground VOUT3 GND 1 2 22 21 VOUT2 VOUT1 VOD Output signal 2 (Green) Output signal 1 (Blue) Output drain voltage Dpi selector No connection No connection No connection Shift register clock 1 Shift register clock 2 Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green) 1 1 φ RB φ CLB NC NC VOD 3 4 5 6 7 8 9 10 11 1 20 19 18 17 16 15 14 13 12 φ SEL NC NC NC Green φ3 φ4 Blue Red φ1 φ2 φ TG1 φ TG2 21360 21360 GND Caution Connect the No connection pins (NC) to GND. 21360 φ TG3 Data Sheet S17085EJ2V0DS 3 μ PD8882 PHOTOCELL STRUCTURE DIAGRAM 2.0 μ m 0.7 μ m 5.4 μ m Channel stopper Aluminum shield PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing) 5.4 μ m Blue odd photocell array 8 lines (43.2 μ m) 16 lines (86.4 μ m) 5.4 μ m Blue even photocell array 8 lines (43.2 μ m) 5.4 μ m Green odd photocell array 8 lines (43.2 μ m) 16 lines (86.4 μ m) 5.4 μ m Green even photocell array 8 lines (43.2 μ m) 5.4 μ m Red odd photocell array 8 lines (43.2 μ m) 5.4 μ m Red even photocell array 4 Data Sheet S17085EJ2V0DS μ PD8882 PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Odd-even pixel) 1 3 5 7 5.4 μ m 43.2 μ m (8 lines) 1.35 μ m 37.8 μ m 2 4 6 8 5.4 μ m 2.0 μ m 0.7 μ m PHOTOCELL ARRAY STRUCTURE DIAGRAM-3 (Dummy, OB, for each color) Dummy (56 pixels) 1 55 57 Optical black (96 pixels) Invalid photocell (8 pixels) 151 153 155 157 159 161 163 Valid photocell (21360 pixels) 21517 21519 Invalid photocell (4 pixels) 2 56 58 152 154 156 158 160 162 164 21518 21520 Data Sheet S17085EJ2V0DS 5 μ PD8882 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Dpi select signal voltage Transfer gate clock voltage Operating ambient temperature Storage temperature Note Symbol VOD Vφ 1, Vφ 2, Vφ 3, Vφ 4 V φ RB Vφ CLB Vφ SEL Vφ TG1 to Vφ TG3 TA Tstg Ratings −0.3 to +15 −0.3 to +8 −0.3 to +8 −0.3 to +8 −0.3 to +8 −0.3 to +8 0 to +60 −40 to +70 Unit V V V V V V °C °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Dpi select signal high level Dpi select signal low level Transfer gate clock high level Transfer gate clock low level Data rate (amplifier) Clock pulse frequency VOD Vφ 1H, Vφ 2H, Vφ 3H, Vφ 4H Vφ 1L, Vφ 2L, Vφ 3L, Vφ 4L Vφ RBH Vφ RBL Vφ CLBH Vφ CLBL Vφ SELH Vφ SELL Vφ TG1H to Vφ TG3H Vφ TG1L to Vφ TG3L f φ RB fφ 1, fφ 2, fφ 3, fφ 4 Symbol Min. 11.4 4.7 −0.3 4.5 −0.3 4.5 −0.3 4.5 −0.3 4.5 −0.3 − − Typ. 12.0 5.0 0 5.0 0 5.0 0 5.0 0 5.0 0 2.0 0.5 Max. 12.6 5.5 +0.3 5.5 +0.5 5.5 +0.5 5.5 +0.5 5.5 +0.5 10.0 4.5 Unit V V V V V V V V V V V MHz MHz 6 Data Sheet S17085EJ2V0DS μ PD8882 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Offset level Note 1 Note 2 Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB VOS td TTE IL PDRI Test Conditions Min. 2.0 − − − − − − − − 2.00 1.89 1.21 5.0 Typ. 2.5 0.877 0.926 1.445 6 0.1 2.0 280 0.4 2.85 2.70 1.73 6.0 25 98 0.5 1.0 630 540 460 −0.8 1.2 Max. − − − − 20 4.0 8.0 450 1.0 3.70 3.51 2.25 7.0 − − 3.0 4.0 − − − +1.0 − Unit V lx•s lx•s lx•s % mV mV mW kΩ V/lx•s V/lx•s V/lx•s V ns % % % nm nm nm mV mV VOUT = 1.0 V Light shielding Light shielding Output fall delay time VOUT = 1.0 V VOUT = 1.0 V Clock pulse frequency = 4.5 MHz VOUT = 1.0 V VOUT = 1.0 V − 92 − − − − − Total transfer efficiency Image lag Photo diode response imbalance Response peak Red Green Blue Reset feed-through noise Random noise (CDS) Note 1 RFTN 74HC04, RS = 47 Ω Light shielding Note 3 −2.0 − σ CDS Notes 1. 2. 3. Refer to TIMING CHART 2-1 to 2-4. When the fall time φ 1-600, φ 1-2400 (t1) is the Typ. value (refer to TIMING CHART 2-1 to 2-4). Using application circuit example. Data Sheet S17085EJ2V0DS 7 μ PD8882 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Shift register clock pin capacitance 3 Shift register clock pin capacitance 4 Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Select signal and gain pin capacitance Transfer gate clock pin capacitance Symbol Cφ 1 Cφ 2 Cφ 3 Cφ 4 Cφ RB Cφ CLB Cφ SEL Cφ TG Pin name Pin No. 15 14 8 9 3 4 19 13 12 10 Min. − − − − − − − − − − Typ. 600 600 600 600 20 20 20 20 20 20 Max. − − − − − − − − − − Unit pF pF pF pF pF pF pF pF pF pF φ1 φ2 φ3 φ4 φ RB φ CLB φ SEL φ TG1 φ TG2 φ TG3 Remark Cφ 1 to Cφ 4 show the equivalent capacity of the real drive including the capacity of between each clock pin (φ 1 and φ 4). 8 Data Sheet S17085EJ2V0DS TIMING CHART 1-1 (2400 dpi, bit clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 Data Sheet S17085EJ2V0DS φ RB Note Note φ CLB φ SEL “H” 21519 21520 21521 21522 21523 21524 21525 151 152 153 154 VOUT1 to VOUT3 Optical black (96 pixels) Invalid photocell (8 pixels) 159 160 161 162 55 56 57 58 1 2 3 4 5 6 Valid photocell (21360 pixels) Invalid photocell (4 pixels) μ PD8882 Note Set the φ RB and the φ CLB to high during this period. 9 VOUT1 to VOUT3 Optical black (96 pixels) Invalid photocell (8 pixels) Valid photocell (21360 pixels) Invalid photocell (4 pixels) 21519 21520 21521 21522 21523 21524 21525 151 152 153 154 159 160 161 162 55 56 57 58 1 2 3 4 5 6 10 Data Sheet S17085EJ2V0DS TIMING CHART 1-2 (2400 dpi, line clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 φ RB Note Note φ CLB φ SEL “H” μ PD8882 Note Set the φ RB to high level and the φ CLB to low level during this period. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. TIMING CHART 1-3 (1200 dpi, bit clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 Data Sheet S17085EJ2V0DS φ RB Note Note φ CLB φ SEL “L” 21519 21521 21523 21525 151 153 155 157 159 161 55 VOUT1 to VOUT3 57 1 3 5 Optical black (48 pixels) Invalid photocell (4 pixels) Valid photocell (10680 pixels) Invalid photocell (2 pixels) μ PD8882 Note Set the φ RB and the φ CLB to high level during this period. 11 21519 21521 21523 VOUT1 to VOUT3 Optical black (48 pixels) Invalid photocell (4 pixels) Valid photocell (10680 pixels) Invalid photocell (2 pixels) 21525 151 153 155 157 159 161 55 57 1 3 5 12 Data Sheet S17085EJ2V0DS TIMING CHART 1-4 (1200 dpi, line clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 φ RB Note Note φ CLB φ SEL “L” μ PD8882 Note Set the φ RB to high level and the φ CLB to low level during this period. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. TIMING CHART 1-5 (600 dpi, bit clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 Data Sheet S17085EJ2V0DS φ RB Note Note φ CLB φ SEL “L” 21517+ 21519 21521+ 21523 21525+ 21527 53+55 57+59 149+ 151 153+ 155 157+ 159 161+ 163 1+3 5+7 VOUT1 to VOUT3 Optical black (24 pixels) Valid photocell (5340 pixels) Invalid photocell (2 pixels) Invalid photocell (1 pixels) μ PD8882 Note Set the φ RB and the φ CLB to high level during this period. 13 21517+ 21519 21521+ 21523 VOUT1 to VOUT3 Optical black (24 pixels) Valid photocell (5340 pixels) Invalid photocell (2 pixels) Invalid photocell (1 pixels) 21525+ 21527 53+55 57+59 149+ 151 153+ 155 157+ 159 161+ 163 1+3 5+7 14 Data Sheet S17085EJ2V0DS TIMING CHART 1-6 (600 dpi, line clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 φ RB Note Note φ CLB φ SEL “L” μ PD8882 Note Set the φ RB to high level and the φ CLB to low level during this period. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. TIMING CHART 1-7 (300 dpi, bit clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 Data Sheet S17085EJ2V0DS φ RB Note Note φ CLB φ SEL “L” 49+51+ 53+55 57+59+ 61+63 21513+ 21515+ 21517+ 21519 VOUT1 to VOUT3 Optical black (12 pixels) Invalid photocell (1 pixels) Valid photocell (2670 pixels) Invalid photocell (1 pixels) 21521+ 21523+ 21525+ 21527 1+3+ 5+7 145+ 147+ 149+ 151 153+ 155+ 157+ 159 161+ 163+ 165+ 167 μ PD8882 Note Set the φ RB and the φ CLB to high level during this period. 15 49+51+ 53+55 57+59+ 61+63 21513+ 21515+ 21517+ 21519 VOUT1 to VOUT3 Optical black (12 pixels) Invalid photocell (1 pixels) Valid photocell (2670 pixels) Invalid photocell (1 pixels) 21521+ 21523+ 21525+ 21527 1+3+ 5+7 145+ 147+ 149+ 151 153+ 155+ 157+ 159 161+ 163+ 165+ 167 16 Data Sheet S17085EJ2V0DS TIMING CHART 1-8 (300 dpi, line clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φ3 φ4 φ RB Note Note φ CLB φ SEL “L” μ PD8882 Note Set the φ RB to high level and φ CLB to low level during this period. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. μ PD8882 TIMING CHART 2-1 (2400 dpi, for each color) t1 t2 φ1 90% 10% 90% 10% t1 t2 φ2 φ3 90% 10% 90% 10% t5 t6 t3 t4 φ4 t19 t4 t19 t4 t4 φ RB 90% 10% t7 t11 t7 t11 t7 t11 t7 t11 φ CLB (Bit clamp mode) 90% 10% t9 t8 t10 φ CLB “H” (Line clamp mode) φ SEL “H” td RFTN VOUT VOS 10% Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9, t10 t11 t19 td Min. 0 20 40 0 −5 20 0 10 110 − Typ. 30 160 150 10 +25 100 10 25 500 25 Max. − − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns ns Data Sheet S17085EJ2V0DS 17 μ PD8882 TIMING CHART 2-2 (1200 dpi, for each color) t1 t2 φ1 90% 10% 90% 10% t19 t19 90% φ2 φ3 φ4 t5 t3 t6 t4 10% t5 t3 t6 t4 φ RB 90% 10% t7 t9 t8 t10 t11 t7 t9 t8 t10 t11 φ CLB (Bit clamp mode) 90% 10% φ CLB “H” (Line clamp mode) φ SEL “L” td RFTN VOUT 10% VOS 10% td Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9, t10 t11 t19 td Min. 0 20 40 0 −5 20 0 10 110 − Typ. 30 160 150 10 +25 100 10 25 500 25 Max. − − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns ns 18 Data Sheet S17085EJ2V0DS μ PD8882 TIMING CHART 2-3 (600 dpi, for each color) t2 t1 φ1 φ2 90% 10% 90% 10% t2 t1 t19 t19 φ3 90% 10% 90% 10% t5 t6 t4 t3 90% 10% t9 t10 t11 t7 t8 90% 10% φ4 φ RB φ CLB (Bit clamp mode) φ CLB “H” (Line clamp mode) φ SEL “L” td RFTN VOUT 10% Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9, t10 t11 t19 td Min. 0 20 40 0 −5 20 0 10 110 − Typ. 30 160 150 10 +25 100 10 25 500 25 Max. − − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns ns Data Sheet S17085EJ2V0DS 19 μ PD8882 TIMING CHART 2-4 (300 dpi, for each color) t2 t1 φ1 φ2 90% 10% 90% 10% t2 t1 t19 t19 φ3 90% 10% 90% 10% t5 t6 t4 t3 90% 10% t9 t10 t11 t7 t8 90% 10% φ4 φ RB φ CLB (Bit clamp mode) φ CLB “H” (Line clamp mode) φ SEL “L” td RFTN VOUT 10% Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9, t10 t11 t19 td Min. 0 20 40 0 −5 20 0 10 110 − Typ. 30 160 150 10 +25 100 10 25 500 25 Max. − − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns ns 20 Data Sheet S17085EJ2V0DS μ PD8882 TIMING CHART 3 t13 t12 t14 90% 10% t16 90% φ TG1 to φ TG3 90% 10% t15 φ1 φ3 90% t17 t18 90% φ RB 90% φ CLB (Line clamp mode) 90% 90% Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB (when line clamp mode). Symbol t12 t13, t14 t15, t16 t17, t18 Min. 5000 0 900 200 Typ. 10000 50 1000 400 Max. 50000 − − − Unit ns ns ns ns φ 1, φ 2, φ 3, φ 4 cross points φ 2, φ 4 2.0 V or more 2.0 V or more φ 1, φ 3 Remark Adjust cross points of (φ 1, φ 2) and (φ 3, φ 4) with input resistance of each pin. Data Sheet S17085EJ2V0DS 21 μ PD8882 SELECTION OF RESOLUTION MODE The μ PD8882 has function of two readout modes, High Resolution Mode and Low Resolution Mode. These two modes can be selected by φ SEL switch. Read Mode High Resolution Mode Low Resolution Mode 2400 dpi (Max.) 1200 dpi (Max.) (odd line readout mode) Description High level Low level φ SEL (1) High Resolution Mode In this mode, both signals in even lines and odd lines can be read out. This mode enables 2400 dpi (Max.) resolution with A4 size (210 × 297 mm, shorter side). Please refer to TIMING CHART 1-1, 1-2 and 2-1. (2) Low Resolution Mode In this mode, only signal in odd photocell arrays can be read out. This mode enables 1200 dpi (Max.) resolution with A4 size. To use intermittent reset drive enable signal charges of adjacent pixels in odd line to add at the charge to voltage conversion area. Then it can achieve low resolution with A4 size such as 600, 300 or 150 dpi. Please refer to TIMING CHART 1-3 to 1-8, 2-2 to 2-4. φ SEL TIMING CHART After changing the dpi selector signal (φ SEL), subsequent data of one line cannot be guaranteed (refer the follow figure). φ TG1 to φ TG3 φ SEL VOUT1 to VOUT3 Invalid date 1 line Valid date 22 Data Sheet S17085EJ2V0DS μ PD8882 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = Δx × 100 x Δ x : maximum of ⎪xj − x ⎪ 21360 j=1 Σx j x= 21360 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x Δx 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 21360 j=1 Σd j ADS (mV) = 21360 dj : Dark signal of valid pixel number j Data Sheet S17085EJ2V0DS 23 μ PD8882 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of ⎪dj − ADS ⎪j = 1 to 21360 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT 24 Data Sheet S17085EJ2V0DS μ PD8882 9. Photo diode response imbalance: PDRI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 n PDRI (%) = j=1 ∑ (V2j –1 – V2j) 1 n j=1 2 ∑ Vj n : Number of valid pixels Vj : Output voltage of each pixel n × 100 10. Offset level : VOS DC level of output signal is defined as follows. 11. Reset feed-through noise : RFTN Reset feed-through noise (RFTN) are defined as follows. + RFTN VOUT – VOS Data Sheet S17085EJ2V0DS 25 μ PD8882 12. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = Σ (VCDS – V) i=1 i 2 , V= 1 100 100 Reset feed-through 100 i = 1 Σ VCDS i Video output 26 Data Sheet S17085EJ2V0DS μ PD8882 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 4 Relative Output Voltage 2 1 0.5 0.25 0.1 0 10 20 30 40 50 Relative Output Voltage 1 0.2 0.1 1 5 Storage Time (ms) 10 Operating Ambient Temperature TA (°C) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R B 80 G Response Ratio (%) 60 40 G 20 B 0 400 500 600 Wavelength (nm) 700 800 Data Sheet S17085EJ2V0DS 27 μ PD8882 APPLICATION CIRCUIT EXAMPLE +5 V +12 V + μ PD8882 10 μ F/16 V 0.1 μ F B3 1 2 RS 47 Ω 47 Ω 3 4 5 6 7 8 4.7 Ω 4.7 Ω 10 Ω 9 10 11 VOUT3 GND VOUT2 VOUT1 VOD 22 21 20 19 18 17 16 15 14 13 12 4.7 Ω 4.7 Ω 10 Ω 10 Ω 47 Ω B2 B1 + 0.1 μ F 47 μ F/25 V +5 V + φ RB φ CLB φ RB φ CLB NC NC VOD φ SEL NC NC NC 0.1 μ F 10 μ F/16 V φ SEL φ3 φ4 φ3 φ1 φ2 φ TG1 φ TG2 φ1 φ2 φ TG φ4 φ TG3 GND Caution Connect the No connection pins (NC) to GND. Remarks 1. φ RB, φ CLB, φ TG1 to φ TG3 and φ SEL driving inverters shown in the above application circuit example are the 74HC04. φ 1 to φ 4 driving inverters shown in the above application circuit example are the 74HC04 (≤ 2.0 MHz) or the 74AC04 (> 2.0 MHz). 2. Inverters B1 to B3 in the above application circuit example are shown in the figure below. B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 47 μ F/25 V 100 Ω 2SC1842 2 kΩ 28 Data Sheet S17085EJ2V0DS μ PD8882 PACKAGE DRAWING μ PD8882CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400)) (Unit : mm) 44.0±0.3 1st valid pixel 1.52±0.3 22 1 9.25±0.3 12 1 37.5 4 11 2.0 4 1.02±0.15 4.39±0.4 (1.72) 2 10.16±0.2 2.62±0.2 0.46±0.1 2.54±0.25 (5.42) 4.21±0.5 3 0.25±0.05 10.16 + 0.7 − 0.2 Name Plastic cap Dimensions 42.7×8.35×0.8(0.7 5) Refractive index 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 4 Mirror finished surface 5 Thickness of mirror finished surface 22C-1CCD-PKG18 Data Sheet S17085EJ2V0DS 29 μ PD8882 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Through-hole Device μ PD8882CY-A : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) Cautions 1. 2. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. 30 Data Sheet S17085EJ2V0DS μ PD8882 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. Either handle bare handed or use non-chargeable gloves, clothes or material. 4. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S17085EJ2V0DS 31 μ PD8882 [MEMO] 32 Data Sheet S17085EJ2V0DS μ PD8882 [MEMO] Data Sheet S17085EJ2V0DS 33 μ PD8882 [MEMO] 34 Data Sheet S17085EJ2V0DS μ PD8882 N OTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17085EJ2V0DS 35 μ PD8882 • T he information in this document is current as of May, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1