NHD-0216CW-AB3

NHD-0216CW-AB3 Character OLED Display Module NHD0216CWAB3- Newhaven Display 2 Lines x 16 Characters Character OLED Module Model Blue 2.4V~5.5V Supply Voltage Newhaven Display International, Inc. 2661 Galvin Ct. Elgin IL, 60124 Ph: 847-844-8795 Fax: 847-844-8796 www.newhavendisplay.com nhtech@newhavendisplay.com nhsales@newhavendisplay.com Document Revision History Revision 0 1 2 Date 12/15/14 4/6/15 2/2/17 Description Initial Release Pin Description, Electrical Characteristics Updated Thru-Hole Diameter Increased, Quality Table Updated, I2C Interface Updated Functions and Features • • • • • • 2 lines x 16 characters Built-in LCD comparable controller 4/8-bit Parallel, SPI, or I²C MPU interface 2.8V or 5.0V operation RoHS compliant Slim design [2] Changed by AK PB SB Mechanical Drawing 1 2 Y R A T E I 3 4 A 5 Rev Description 6 Date A Newhaven Display NHD-0216CW_RevB Not Populated B Notes: P D 1. Emitting Color: R P O R C C D Blue 2. Display format: 2 lines x 16 characters 3. Supply Voltage: 2.4V~5.5V 4. Interface: 4/8-bit Parallel, SPI, I²C 5. Controller: US2066 6. Recommended FFC Connector: MOLEX 52271-2079 1 B 2 Unit mm Gen. Tol. ±0.3 3 4 Date 02/02/17 5 Part Number: NHD-NHD-0216CW-AB3 6 The information contained herein is the exclusive property of Newhaven Display International, Inc. and shall not be copied, reproduced, and/or disclosed in any format without permission. [3] Pin Description Parallel Interface: Pin No. 1 Symbol VSS External Connection Power Supply 2 VDD Power Supply 3 REGVDD Power Supply 4 5 6 D/C R/W E MPU MPU MPU 7-10 DB0 – DB3 MPU 11-14 15 16 17-19 20 DB4 – DB7 /CS /RES BS0 – BS2 VSS MPU MPU MPU MPU Power Supply Serial Interface: Pin No. 1 Symbol VSS External Connection Power Supply 2 VDD Power Supply 3 REGVDD Power Supply 4-6 7 8 9 10-14 15 16 17-19 20 NC SCLK SDI SDO NC /CS /RES BS0 – BS2 VSS MPU MPU MPU MPU MPU MPU Power Supply I²C Interface: Pin No. 1 Symbol VSS External Connection Power Supply 2 VDD Power Supply 3 REGVDD Power Supply 4 5-6 7 8 9 10-15 16 17-19 20 SA0 NC SCL SDAIN SDAOUT NC /RES BS0 – BS2 VSS MPU MPU MPU MPU MPU MPU Power Supply Function Description Ground Supply Voltage for OLED and Logic VDD=2.8V for 2.8V operation, VDD=5V for 5V operation Internal 5V I/O Regulator select signal REGVDD=0V for 2.8V operation, REGVDD=5V for 5V operation Data/Command select signal. D/C=0: Command, D/C=1: Data Read/Write select signal, R/W=1: Read R/W=0: Write Operation Enable signal. Falling edge triggered. Four low order bi-directional three-state data bus lines. These four are not used during 4-bit operation. Four high order bi-directional three-state data bus lines. Active LOW Chip Select signal Active LOW Reset signal MPU interface select signal Ground Function Description Ground Supply Voltage for OLED and Logic VDD=2.8V for 2.8V operation, VDD=5V for 5V operation Internal 5V I/O Regulator select signal REGVDD=0V for 2.8V operation, REGVDD=5V for 5V operation No Connect. Tie to Ground Serial Clock signal Serial Data Input signal Serial Data Output signal No Connect. Tie to Ground Active LOW Chip Select signal Active LOW Reset signal MPU interface select signal Ground Function Description Ground Supply Voltage for OLED and Logic VDD = 2.8V for 2.8V operation ONLY, 5V mode not supported Internal 5V I/O Regulator select signal REGVDD=0V for 2.8V operation ONLY, 5V mode not supported Slave Address select signal No Connect. Tie to Ground Serial Clock signal Serial Data Input. Serial Data Output. Tie together with SDAIN (pin 8) No Connect. Tie to Ground Active LOW Reset signal MPU interface select signal Ground [4] MPU Interface Pin Selections Pin Name BS0 BS1 BS2 4-bit Parallel 6800 interface 1 0 1 4-bit Parallel 8080 interface 1 1 1 8-bit Parallel 6800 interface 0 0 1 8-bit Parallel 8080 interface 0 1 1 Serial Interface 0 0 0 MPU Interface Pin Assignment Summary Bus Interface 4-bit 6800 4-bit 8080 8-bit 6800 8-bit 8080 SPI I²C D7 D6 Data/Command Interface D5 D4 D3 D2 D1 D[7:4] Tie LOW D[7:4] Tie LOW D[7:0] D[7:0] Tie LOW SDO SDI Tie LOW SDAOUT SDAIN [5] D0 SCLK SCL I²C Interface 0 1 0 Control Signals E R/W /CS D/C E R/W /CS D/C /RD /WR /CS D/C E R/W /CS D/C /RD /WR /CS D/C Tie LOW /CS Tie LOW Tie LOW SA0 /RES /RES /RES /RES /RES /RES /RES Electrical Characteristics Item Operating Temperature Range Storage Temperature Range Symbol TOP TST Condition Absolute Max Absolute Max Min. -40 -40 Typ. - Max. +85 +90 Unit ⁰C ⁰C Supply Voltage for logic Supply Voltage for I/O Regulator Supply Current Sleep Mode Current “H” Level input “L” Level input “H” Level output “L” Level output VDD REGVDD IDD (IDD)SLEEP VIH VIL VOH VOL VDD = 5V - 2.4 4.4 0.8 * VDD VSS 0.9 * VDD VSS 2.8 5.0 70 2 - 5.5 5.5 135 5 VDD 0.2 * VDD VDD 0.1 * VDD V V mA mA V V V V Optical Characteristics Optimal Viewing Angles Item Top Bottom Left Right Contrast Ratio Symbol ϕY+ ϕYθXθX+ CR TR TR - Condition CR ≥ 10,000:1 Min. 80 80 80 80 10,000:1 60 25,000 Typ. 10 10 80 - Max. - Unit ⁰ ⁰ ⁰ ⁰ us us 2 cd/m Hrs. Response Time Brightness 50% Checkerboard TOP = 25°C Lifetime 50% Checkerboard Note: Lifetime at typical temperature is based on accelerated high-temperature operation. Lifetime is tested at average 50% pixels on and is rated as Hours until Half-Brightness. The Display OFF command can be used to extend the lifetime of the display. Luminance of active pixels will degrade faster than inactive pixels. Residual (burn-in) images may occur. To avoid this, every pixel should be illuminated uniformly. Rise Fall Controller Information Built-in US2066 controller. Please download specification at http://www.newhavendisplay.com/app_notes/US2066.pdf DDRAM Address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F [6] Table of Commands 1. Fundamental Command List Command IS RE SD Clear Display X X 0 Return Home X 0 0 Instruction Code Description D/C# R/W# (WR#) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM and set DDRAM address to "00H" from AC. * Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. 0 0 0 0 0 0 0 0 1 Assign cursor / blink moving direction with DDRAM address. I/D = "1": cursor/ blink moves to right and DDRAM address is increased by 1 (POR) X 0 0 0 0 0 0 0 0 0 1 I/D S I/D = "0": cursor/ blink moves to left and DDRAM address is decreased by 1 Assign display shift with DDRAM address. S = "1": make display shift of the enabled lines by the DS4 to DS1 bits in the shift enable instruction. Left/ right direction depends on I/D bit selection. Entry Mode Set S = "0": display shift disable (POR) X 1 0 0 0 0 0 0 0 0 1 BDC BDS Common bi-direction function. BDC = "0": COM31 -> COM0 BDC = "1": COM0 -> COM31 Segment bi-direction function. BDS = "0": SEG99 -> SEG0, BDS = "1": SEG0 -> SEG99 Set display/cursor/blink ON/OFF Display ON/ OFF Control D = "1": display ON, D = "0": display OFF (POR), X 0 0 0 0 0 0 0 0 1 D C B C = "1": cursor ON, C = "0": cursor OFF (POR), B = "1": blink ON, B = "0": blink OFF (POR). Assign font width, black/white inverting of cursor, and 4line display mode control bit. Extended Function Set FW = "1": 6-dot font width, FW = "0": 5-dot font width (POR), X 1 0 0 0 0 0 0 0 1 FW BW NW B/W = "1": black/white inverting of cursor enable, B/W = "0": black/white inverting of cursor disable (POR) NW = "1": 3-line or 4-line display mode NW = "0": 1-line or 2-line display mode [7] 1. Fundamental Command Set Command Cursor or Display Shift IS 0 RE 0 SD 0 D/C# 0 Instruction Code R/W# (WR#) D7 0 0 D6 D5 D4 D3 D2 D1 D0 Description Set cursor moving and display shift control bit, and the direction, without changing DDRAM data. 0 0 1 S/C R/L * * S/C = "1": display shift, S/C = "0": cursor shift, R/L = "1": shift to right, R/L = "0": shift to left Double Height (4Line)/ Display-dot Shift 0 1 0 0 0 0 0 0 1 UD2 UD1 * DH’ UD2~1: Assign different doubt height format (POR=11b) Refer to Table 7-2 for details DH’ = "1": display shift enable DH’ = "0": dot scroll enable (POR) DS[4:1]=1111b (POR) when DH’ = 1b Determine the line for display shift. Shift Enable 1 1 0 0 0 0 0 0 1 DS4 DS3 DS2 DS1 DS1 = "1/0": 1st line display shift enable/disable DS2 = "1/0": 2nd line display shift enable/disable DS3 = "1/0": 3rd line display shift enable/disable DS4 = "1/0": 4th line display shift enable/disable. HS[4:1]=1111b (POR) when DH’ = 0b Determine the line for horizontal smooth scroll. Scroll Enable 1 X 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 * HS4 N HS3 DH HS2 RE (0) HS1 IS HS1 = "1/0": 1st line dot scroll enable/disable HS2 = "1/0": 2nd line dot scroll enable/disable HS3 = "1/0": 3rd line dot scroll enable/disable HS4 = "1/0": 4th line dot scroll enable/disable. Numbers of display line, N when N = "1": 2-line (NW=0b) / 4-line (NW=1b), when N = "0": 1-line (NW=0b) / 3-line (NW=1b) DH = “ 1/0”: Double height font control for 2-line mode enable/ disable (POR=0) Extension register, RE ("0") Function Set Extension register, IS X 1 0 0 0 0 0 1 * [8] N BE RE (1) CGRAM blink enable BE = 1b: CGRAM blink enable BE = 0b: CGRAM blink disable (POR) REV Extension register, RE ("1") Reverse bit REV = "1": reverse display, REV = "0": normal display (POR) 1. Fundamental Command Set Command IS RE SD Set CGRAM Address 0 0 Set DDRAM Address 0 Set Scroll Quantity X Instruction Code Description D/C# R/W# (WR#) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. (POR=00 0000) 0 0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. (POR=000 0000) 1 0 0 0 1 * SQ5 SQ4 SQ3 SQ2 SQ1 SQ0 Set the quantity of horizontal dot scroll. (POR=00 0000) Valid up to SQ[5:0] = 110000b Can be known whether during internal operation or not by reading BF. The contents of address counter or the part ID can also be read. When it is read the first time, the address counter can be read. When it is read the second time, the part ID can be read. Read Busy Flag and Address/ Part ID X Write Data X X 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM (DDRAM / CGRAM). Read Data X X 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM (DDRAM / CGRAM). 2. X 0 0 1 BF AC6 / ID6 Function Selection A AC4 / ID4 AC3 / ID3 AC2 / ID2 AC1 / ID1 AC0 / ID0 BF = "1": busy state BF = "0": ready state Extended Command Set Command AC5 / ID5 IS RE SD X X 1 1 0 0 X X 1 1 0 0 D/C# 0 1 0 1 R/W# (WR#) 0 0 0 0 Instruction Code Hex D7 D6 D5 D4 D3 D2 D1 D0 71 A[7:0] 0 A7 1 A6 1 A5 1 A4 0 A3 0 A2 0 A1 1 A0 72 0 * 1 * 1 * 1 * 0 ROM 1 0 ROM 0 1 OPR 1 0 OPR 0 Function Selection B OLED Characteriza tion Description A[7:0] = 00h, Disable internal VDD regulator at 5V I/O application mode A[7:0] = 5Ch, Enable internal VDD regulator at 5V I/O application mode (POR) OPR[1:0]: Select the character no. of character generator OPR[1: 0] CGRO M CGRA M 00b 01b 10b 11b 240 248 250 256 8 8 6 0 ROM[1:0]: Select character ROM X 1 X 0 0 78/79 0 1 [9] 1 1 1 0 0 SD RO[1:0] ROM 00b 01b 01b 11b A B C Invalid Extension Register, SD SD=0b: OLED Command set is disabled (POR) SD=1b: OLED Command set is enabled. 3. OLED Command Set Command Set Contrast Control IS RE SD X X 1 1 X X Instruction Code Description R/W# (WR#) 0 0 Hex D7 D6 D5 D4 D3 D2 D1 D0 1 1 D/C # 0 0 81 A[7:0] 1 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 1 A0 Double byte command to select 1 out of 256 contrast steps. Contrast increases as the value increases. (POR = 7Fh ) 1 1 1 1 0 0 0 0 D5 A[7:0] 1 A7 1 A6 0 A5 1 A4 0 A3 1 A2 0 A1 1 A0 X X 1 1 1 1 0 0 0 0 D9 A[7:0] 1 A7 1 A6 0 A5 1 A4 1 A3 0 A2 0 A1 1 A0 X X 1 1 1 1 0 0 0 0 DB A[6:4] 1 0 1 A6 0 A5 1 A4 1 0 0 0 1 0 1 0 A[3:0]: Define the divide ratio {D) of the display clocks (DCLK) divide ratio = A[3:0] + 1 (POR=0000b) A[7:4]: Set the Oscillator Frequency, FOSC. Oscillator Frequency increases with the value of A[7:4] and vice versa. (POR=0111b) Range:0000b~1111b Frequency increases as setting value increases. A[3:0]: Phase 1 period of up to 32 DCLK; clock 0 is an valid entry with 2 DCLK (POR=1000b) A[7:4]: Phase 2 period of up to 15 DCLK; clock 0 is invalid entry (POR=0111b) VCOMH A[6:4] Hex Code Deselect Set Display Clock Divide Ratio / Oscillator Frequency Set Phase Length Set SEG Pins Hardware Configuration [10] level 000b 00h 001b 10h 010B 20h 011 30h 100b 40h ~0.65 x VCC ~0.71 x VCC ~0.77 x VCC (POR) ~0.83 x VCC 1 x VCC 1. OLED Command Set Command IS RE SD X X 1 1 1 1 Instruction Code D/C # 0 0 R/W# (WR#) 0 0 Hex D7 D6 D5 D4 D3 D2 D1 D0 DC A[7:0] 1 A7 1 A6 0 A5 1 A4 1 A3 1 A2 0 A1 0 A0 Description Set VSL & GPIO Set VSL: A[7] = 0b: Internal VSL (POR) A[7] = 1b: Enable external VSL Set GPIO: A[1:0]= 00b represents GPIO pin HiZ, input disabled (always read as low) A[1:0]= 01b represents GPIO pin HiZ, input enabled A[1:0]= 10b represents GPIO pin output Low (RESET) A[1:0]= 11b represents GPIO pin output High Function Selection C X X 1 1 1 1 0 0 0 0 23 A[5:0] 0 * 0 * 1 A5 0 A4 0 A3 0 A2 1 A1 1 A0 A[5:4] = 00b Disable Fade Out / Blinking Mode[RESET] A[5:4] = 10b Enable Fade Out mode. Once Fade Mode is enabled, contrast decrease gradually to all pixels OFF. Output follows RAM content when Fade mode is disabled. A[5:4] = 11b Enable Blinking mode. Once Blinking Mode is enabled, contrast decrease gradually to all pixels OFF and then contrast increases gradually to normal display. This process loops continuously until the Blinking mode is disabled. Set Fade Out and Blinking A[3:0] : Set time interval for each fade step [11] A[3:0] Time interval of for each fade step 0000b 8 Frames 0001b 16 Frames 0010b 24 Frames : : 1110b 120 Frames 1111b 128 Frames Timing Characteristics 6800-Series Parallel Interface: Symbol tcycle tAS tAH tCS tCH tDSW tDHW tDHR tOH tACC PWCSL PWCSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Chip Select Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Condition 1: /CS low pulse width > E high pulse width [12] Min 400 13 17 0 0 35 18 13 10 Typ - Max 90 Unit ns ns ns ns ns ns ns ns ns - - 125 ns 250 250 50 155 55 - - 15 15 ns ns ns ns ns ns ns Condition 2: /CS low pulse width < E high pulse width [13] 8080-Series Parallel Interface: Symbol tcycle tAS tAH tCS tCSH tDSW tDHW tDHR tOH tACC PWCSL PWCSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Chip Select Time Chip Select hold time to read signal Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) - tPWLR Chip Select Low Pulse Width (read Command) - tPWLR Chip Select Low Pulse Width (write) - tPWLW Chip Select High Pulse Width (read) - tPWHR Chip Select High Pulse Width (write) - tPWHW Rise Time Fall Time [14] Min 400 13 17 0 0 35 18 13 10 Typ - Max 70 Unit ns ns ns ns ns ns ns ns ns - - 125 ns 250 250 50 155 55 - - 15 15 ns ns ns ns ns ns ns Serial Interface: Symbol tC tR, tF tW tsu1 th1 tsu2 th2 tD tDH Parameter Serial Clock Cycle Time Serial clock rise/fall time Serial clock width (high, low) Chip select setup time Chip select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time Min 1 400 60 20 200 TBD 10 [15] Typ - Max 20 15 TBD 70 Unit µs ns ns ns ns ns ns ns ns I²C Interface: Symbol tcycle tHSTART tHD tSD tSSTART tSSTOP tR tF tIDLE Parameter Clock Cycle Time Start Condition Hold Time Data Hold Time (for “SDAOUT” pin) Data Hold Time (for “SDAIN” pin) Data Setup Time Start condition setup time (Only for a repeated Start Condition) Stop condition Setup Time Rise Time for data and clock pin Fall Time for data and clock pin Idle Time before a new transmission can start [16] Min 2.5 0.6 5 300 100 0.6 0.6 1.3 Typ - Max 300 300 - Unit µs µs ns ns ns µs µs ns ns µS Built-in Font Tables [17] [18] [19] Example Program Code void command(char i) { C_S = 0; P1 = i; D_C = 0; R_W = 0; E = 1; delayms(1); E = 0; } void data(char i) { C_S = 0; P1 = i; D_C = 1; R_W = 0; E = 1; delayms(1); E = 0; } //chip select LOW – active //data on port //data/command select LOW – command //read/write select LOW – write //enable HIGH //delay //enable LOW – data latched //chip select LOW – active //data on port //data/command select HIGH – data //read/write select LOW – write //enable HIGH //delay //enable LOW – data latched void output() { int i; command(0x01); command(0x02); for(i=0;i 85⁰C,30min = 1 cycle 100 cycles 10-22Hz , 1.5mm amplitude. 22-500Hz, 1.5G 30min in each of 3 directions X,Y,Z VS=800V, RS=1.5kΩ, CS=100pF One time Note 1: No condensation to be observed. Note 2: Conducted after 2 hours of storage at 25⁰C, 0%RH. Note 3: Test performed on product itself, not inside a container. Evaluation Criteria: 1: Display is fully functional during operational tests and after all tests, at room temperature. 2: No observable defects. 3: Luminance >50% of initial value. 4: Current consumption within 50% of initial value Precautions for using OLEDs/LCDs/LCMs See Precautions at www.newhavendisplay.com/specs/precautions.pdf Warranty Information and Terms & Conditions http://www.newhavendisplay.com/index.php?main_page=terms [22] 3