User’s Guide
NHD-12864EZ-FL-YBW
LCM
(Liquid Crystal Display Graphic Module)
RoHS Compliant
NHD12864EZFLYBW-
Newhaven Display
128 x 64 pixels
Version Line
Transflective
Yellow/Green LED B/L
STN- Yellow/Green
6:00 View
Wide Temperature (-20 ~ +70c)
For product support, contact
Newhaven Display International
2511 Technology Drive, #101
Elgin, IL 60124
Tel: (847) 844-8795 Fax: (847) 844-8796
February 29, 2008
NHD-12864EZ
Feature
1. 128X64 dots with 8192 chinese character fonts (16x16)
2. 128 alpha-numerical fonts (16x8)
3. 64X256 bit graphic display RAM
4.Strong display control fuctions: Vertical scroll, horizontal bit scroll,line reverse etc
5.+2.7~ +5.5V power supply
4. STN; 1/64 duty; LED BKL or EL BKL
7. 4bit,8bit,serial interface
Mechanical diagram
Mechanical data
ITEM
STANDARD
UNIT
MODULE DIMENSION
93X70.0/9.0(EL)/13.0(LED)
mm
VIEWING AREA
72.0X40
mm
DOT SIZE
0.48X0.48
mm
DOT PITCH
0.52X0.52
mm
Newhaven Display International, LLC
Page 2 of 22
NHD-12864EZ
Block diagram
LCD PANEL
Absolute Maximum Ratings
ITEM
Power Voltage
Input Voltage
LCD
Voltage
Operating temperature range
Storage temperature range
SYMBOL
VDD -VSS
VI
VLCD
VOP
TST
MIN
0
VSS
4.5
-20
-30
MAX
5.5
VDD
7.0
+70
+80
UNIT
V
DESCRIPTION OF TERMINALS
PIN
NO.
1
2
3
PIN
NAME
VSS
VDD
VO
INPUT/
OUTPUT
INPUT
INPUT
INPUT
EXTERNAL
CONNECTION
POWER
SUPPLY
4
RS(CS*)
INPUT
MPU
5
R/W(SID*)
INPUT
MPU
6
E(SCLK*)
INPUT
MPU
DB0-DB3
INPUT
MPU
DB4-DB7
INPUT
MPU
A
K
/RST
VEE
A
K
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
7
/
10
11
/
14
15
16
17
18
19
20
Newhaven Display International, LLC
BACKLIGHT
FUNCTION
VSS: GND
VDD: +5V
VLCD ADJUSTMENT
REGISTER SELECT SIGNAL
“0”:INSTRUCTION REGISTER (WHEN WRITING)
BUSY FLAG & ADDRESS COUNTER (WHEN
READING)
“1”:DATA REGISTER (WHEN WRITING &
READING)
READ/WRITE SELECT SIGNAL
“0” FOR WRITING , “1” FOR READING
OPERATION (DATA READ/WRITE) ENABLE
SIGNAL
LOW-ORDER LINES OF DATA BUS WITH
3-STATE,
BI-DIRECTIONAL FUNCTION FOR USE IN DATA
TRANSACTION WITH THE MPU. THESE LINES
ARE
NOT USED WHEN INTERFACING WITH A 4-BIT
MICROPROCESSOR.
HIGH-ORDER LINES OF DATA BUS WITH
3-STATE,
BI-DIRECTIONAL FUNCTION FOR USE IN DATA
TRANSACTIONS WITH THE MPU. DB7 MAY
ALSO BE
USED TO CHECK THE BUSY FLAG.
RESET SIGNAL
DOUBLE VOLTAGE BOOSTER OUTPUT
BACKLIGHT
Page 3 of 22
NHD-12864EZ
Optical
Characteristics
FOR STN TYPE DISPLAY MODULE
ITEM
VIEWING ANGLE
SYMBOL CONDITION
CR4
CR
CONTRAST RATIO
RESPONSE
TIME(RISE)
RESPONSE
TIME(FALL)
(TA=25, VDD=5.0V0.25V)
MIN.
TYP.
MAX.
-25
-30
30
2
UNIT
DEG
TR
120
150
mS
TR
120
150
mS
TYP.
MAX.
UNIT
6
150
150
35
40
250
250
STN TYPE DISPLAY MODULE
ITEM
VIEWING ANGLE
CONTRAST RATIO
RESPONSE TIME(RISE)
RESPONSE TIME(FALL)
Electrical
(TA=25, VDD=5.0V)
SYMBOL CONDITI MIN.
ON
-60
CR2
-40
CR
TR
TR
mS
mS
Characteristics
DC Characteristics(Ta=25,VDD=5.0V)
PARAMETER
SUPPLY VOLTAGE FOR LCD
INPUT VOLTAGE
SUPPLY CURRENT
INPUT LEAKAGE CURRENT
“H” LEVEL INPUT VOLTAGE
SYMBOL
VDDVO
VDD
IDD
ILKG
VIH
“L” LEVEL INPUT VOLTAGE
VIL
“H” LEVEL OUTPUT VOLTAGE
“L” LEVEL OUTPUT VOLTAGE
BACKLIGHT
SUPPLY
VOLTAGE
VOH
VOL
DEG
CONDITIONS
TA=25
VDD=5.0V;TA=25
TWICE INITIAL VALUE
OR LESS
LOH= -0.25mA
LOL=1.6mA
VF
MIN.
3.0
3.5
TYPE
6.5
5.0
0.5
MAX.
5.5
0.7
1.0
VDD
UNIT
V
V
mA
A
V
-0.3
0.6
V
4.0
0
V
V
4.2
5.0
V
TYPE
4.2
3.0
0.4
MAX.
3.3
0.7
1.0
VDD
-0.3
0.6
V
4.0
V
V
V
DC Characteristics(Ta=25,VDD=3.0V)
PARAMETER
SUPPLY VOLTAGE FOR LCD
INPUT VOLTAGE
SUPPLY CURRENT
INPUT LEAKAGE CURRENT
“H” LEVEL INPUT VOLTAGE
SYMBOL
VDDVO
VDD
IDD
ILKG
VIH
“L” LEVEL INPUT VOLTAGE
VIL
“H” LEVEL OUTPUT VOLTAGE
“L” LEVEL OUTPUT VOLTAGE
BACKLIGHT
SUPPLY
VOLTAGE
VOH
VOL
Newhaven Display International, LLC
VF
CONDITIONS
TA=25
VDD=5.0V;TA=25
TWICE INITIAL VALUE
OR LESS
LOH= -0.25mA
LOL=1.6mA
MIN.
3.5
UNIT
V
V
mA
A
V
Page 4 of 22
NHD-12864EZ
AC Characteristics (VDD=5V,TA=25) Parallel mode interface
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
-
540
-
KHZ
Internal clock operation
f osc
OSC Frequency
R=33k
External Clock Operation
t EX
T R, T F
External Frequency
-
-
540
-
KHZ
Duty Cycle
-
45
50
55
%
Rise/Fall Time
-
-
-
0.2
us
Write Mode (writing data from MPU to LCM)
TC
Enable Cycle Time
Pin E
1200
-
-
T PW
Enable Pulse Width
Pin E
140
-
-
T r ,T f
Enable rise/fall time
Pin E
-
-
25
T AS
Address setup time
Pins: RS, RW, E
10
-
-
T AH
Address hold time
Pins: RS, RW, E
20
-
-
T DDR
Data delay time
Pins; DB0-DB7
40
-
-
TH
Data hold time
Pins DB0-DB7
20
-
-
ns
ns
Read mode (writing data from MPU to LCM)
TC
Enable Cycle Time
Pin E
1200
-
-
T PW
Enable Pulse Width
Pin E
140
-
-
T r ,T f
Enable rise/fall time
Pin E
-
-
25
T AS
Address setup time
Pins: RS, RW, E
10
-
-
T AH
Address hold time
Pins: RS, RW, E
20
-
-
T DDR
Data delay time
Pins; DB0-DB7
-
-
100
Data hold time
Pins DB0-DB7
20
-
-
Min.
Typ.
Max.
Unit
470
540
590
KHZ
TH
ns
ns
AC Characteristics (VDD=5V,TA=25) Serial mode interface
Symbol
Parameter
Test Conditions
Internal clock operation
T osc
OSC Frequency
R=33k
External Clock Operation
T EX
External Frequency
-
470
530
590
KHZ
Duty Cycle
-
45
50
55
%
T R, T F
Rise/Fall Time
-
-
-
0.2
us
T SCYC
Enable Cycle Time
Pin E
600
-
-
T SHW
Enable Pulse Width
Pin E
200
-
-
T SLW
Enable rise/fall time
Pin E
200
-
-
T SDS
Address setup time
Pin: RW
40
-
-
T SDH
Address hold time
Pin: RW
40
-
-
T CSS
Data delay time
Pin; RS
60
-
-
T CSH
Data hold time
Pin: RS
60
-
-
Newhaven Display International, LLC
ns
Page 5 of 22
NHD-12864EZ
AC Characteristics (VDD=3.0V,TA=25) Parallel mode interface
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
-
530
-
KHZ
Internal clock operation
F osc
OSC Frequency
R=18k
External Clock Operation
T EX
T R, T F
External Frequency
-
-
530
-
KHZ
Duty Cycle
-
45
50
55
%
Rise/Fall Time
-
-
-
0.2
us
Write Mode (writing data from MPU to LCM)
TC
Enable Cycle Time
Pin E
1800
-
-
T PW
Enable Pulse Width
Pin E
160
-
-
T r ,T f
Enable rise/fall time
Pin E
-
-
25
T AS
Address setup time
Pins: RS, RW, E
10
-
-
T AH
Address hold time
Pins: RS, RW, E
20
-
-
T DDR
Data delay time
Pins; DB0-DB7
40
-
-
TH
Data hold time
Pins DB0-DB7
20
-
-
ns
ns
Read mode (reading data form MPU to LCM)
TC
Enable Cycle Time
Pin E
1800
-
-
T PW
Enable Pulse Width
Pin E
320
-
-
T r ,T f
Enable rise/fall time
Pin E
-
-
25
T AS
Address setup time
Pins: RS, RW, E
10
-
-
T AH
Address hold time
Pins: RS, RW, E
20
-
-
T DDR
Data delay time
Pins; DB0-DB7
-
-
260
Data hold time
Pins DB0-DB7
20
-
-
Min.
Typ.
Max.
Unit
470
540
590
KHZ
TH
ns
ns
AC Characteristics (VDD=3.0V,TA=25) Serial mode interface
Symbol
Parameter
Test Conditions
Internal clock operation
T osc
OSC Frequency
RF=18k
External Clock Operation
T EX
External Frequency
-
470
530
590
KHZ
Duty Cycle
-
45
50
55
%
T R, T F
Rise/Fall Time
-
-
-
0.2
us
T SCYC
Enable Cycle Time
Pin E
600
-
-
T SHW
Enable Pulse Width
Pin E
300
-
-
T SLW
Enable rise/fall time
Pin E
300
-
-
T SDS
Address setup time
Pin: RW
40
-
-
T SDH
Address hold time
Pin: RW
40
-
-
T CSS
Data delay time
Pin; RS
60
-
-
T CSH
Data hold time
Pin: RS
60
-
-
Newhaven Display International, LLC
ns
Page 6 of 22
NHD-12864EZ
Timing Characteristics
Writing data form MPU to LCM
Reading data from LCM to MPU
serial interface & transferring serial data
Writing data form MPU to LCM
Newhaven Display International, LLC
Page 7 of 22
NHD-12864EZ
CGROM,CGRAM,ICON RAM,AND DDRAM,GDRAM
Graphic display data address map
GDRAM Y
GDRAMX
0
9
0
15
31
Table 1: 64 x 256-bit map display RAM (GDRAM) for graphic mode display
Newahevn Display International, LLC
Page 8 of 22
NHD-12864EZ
Character generator ROM (CGROM)
THE CHARACTER GENERATOR ROM GENERATES 16 X 16 DOT OR 16 X 8 DOT CHARACTER
PATTERNS FROM TWO 8-BIT CHARACTER CODES. USER-DEFINED CHARACTER PATTERNS ARE
ALSO AVAILABLE BY MASK-PROGRAMMED ROM.
Character generator RAM (CGRAM)
IN THE CHARACTER GENERATOR RAM, THE USER CAN REWRITE CHARACTER PATTERNS BY
PROGRAM. FOR 16 X 16 DOTS,
FOUR CHARACTER PATTERNS CAN BE WRITTEN.
SEE TABLE 1 FOR THE RELATIONSHIP BETWEEN CGRAM ADDRESSES AND DATA AND DISPLAY
PATTERNS. AREAS THEY ARE NOT USED FOR DISPLAY CAN BE USED AS GENERAL DATA RAM.
Table1
Newhaven Display International, LLC
Page 9 of 22
NHD-12864EZ
Table 1: Relationship between CGRAM Addresses, Character Codes (DDRAM)
and Character patterns (CGRAM Data)
Notes:
1. Character code bits 1 to 2 correspond to CGRAM address bits 4 to 5 (2 bits: 4 types).
2. CGRAM address bits 0 to 3 designate the character pattern line position. The 16th line is the
cursor position and a logical OR with the cursor forms its display. Maintain the 16th line data,
corresponding to the cursor display position, at 0 as the cursor display. If the 16th line data is 1, 1
bits will light up the 16th line regardless of the cursor presence.
3. Character pattern row positions correspond to CGRAM data bits 0 to 15 (bit 15 being at the left).
*4. As shown Table, CGRAM character patterns are selected when character code bits 4 to 15
are all 0 and bit 0 and bit 3 are don’t care (x).
Table 2: 16K-bit half-size character generator ROM (HCGROM) for a total of 128
alpha-numerical fonts(16x8 dots)
Newhaven Display International, LLC
Page 10 of 22
NHD-12864EZ
Control and display command
Basic instruction
Newhaven Display International, LLC
Page 11 of 22
NHD-12864EZ
Extension instruction
Note:
Be sure the LCM is not in the busy state (BF = 0) before sending an instruction from the MPU to
the LCM. If an instruction is sent without checking the busy flag, the time between the first
instruction and next instruction will take much longer than the instruction time itself. Refer to
Instruction Table for the list of each instruction execution time.
Newhaven Display International, LLC
Page 12 of 22
NHD-12864EZ
Serial Interface & Transferring Serial Data
The LCM enters serial mode when the J8 is set low. A two-line clock synchronous transfer
method is used. The LCM receives serial input data(SID) by synchronizing with a transfer
clock(SCLK) sent from the master side.
When the MPU interfaces with several LCD MODULES, chip select pin(CS) must be used. The transfer
clock(SCLK) input is activated by making chip select(CS) high. In addition, the transfer counter of the
LCM can be reset and serial transfer synchronized by making chip select(CS) low. Here, since the
data which was being sent at reset is cleared, restart the transfer from the first bit of this data. In a
minimum system where a single LCM interfaces to a single MPU, an interface can be constructed
from the transfer clock(SCLK) and serial input data(SID). In this case, chip select(CS) should be fixed
to high.
The transfer clock(SCLK) is independent of operational clock of the LCM. However, when several
instructions are continuously transferred, the instruction execution time determined by the operational
clock must be considered since the LCM does not have an internal transmit/receive buffer.
Following figure shows the basic procedure for transferring serial data. To begin with, transfer the start
byte. By receiving five consecutive bits of 1(synchronizing bit string) at the beginning of the start byte,
the transfer counter of the LCM is reset and serial transfer is synchronized. The 2 bits following the
synchronizing bit string(5 bits) specify transfer direction(RW bit) and register select(RS bit). Be sure to
transfer 0 in the 8 th bit.
After receiving the start synchronizing bit string, the RW bit(=0), and RS bit in the start byte, an 8-bit
instruction is received in 2 bytes: the higher 4 bits of the instruction are placed in the LSB of the first
byte, and the lower 4 bits of the instruction are placed in the LSB of the second byte. Be sure to transfer
0 in the following 4 bits of each byte.
Newhaven Display International, LLC
Page 13 of 22
NHD-12864EZ
Initialization procedure
8-bit Interface:
power on
w a it t im e > 4 0 m s
h ig h
x r e s t lo w
fu n c tio n s e t
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
1
1
X
0
0
0
X
X
0
w a it tim e > 1 0 0 u s
fu n c tio n s e t
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
0
0
0
1
1
X
X
X
0
w a it tim e > 1 0 0 u s
D is p la y O N /O F F c o n tr o l
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
C
B
D
1
1
X
0
0
0
0
w a it tim e > 1 0 0 u s
D is p la y c le a r
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
1
0
0
0
0
0
0
0
0
w a it t im e > 1 0 m s
E n te r m o d e s e t
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
0
0
I /D
S
0
0
0
1
0
In it ia liz a t io n e n d
Newhaven Display International, LLC
Page 14 of 22
NHD-12864EZ
4-bit Interface:
pow er on
w a it tim e > 4 0 m s
h ig h
x re s t lo w
fu n c tio n s e t
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
0
0
1
1
X
0
X
X
0
w a it tim e > 1 0 0 u s
fu n c tio n s e t
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
0
0
1
0
X
X
X
X
0
0
X
0
X
X
X
X
X
X
0
w a it tim e > 1 0 0 u s
D is p la y O N /O F F c o n tro l
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
X
X
X
X
0
0
0
0
0
0
X
X
X
X
0
1
D
C
B
0
w a it tim e > 1 0 0 u s
D is p la y c le a r
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
X
X
X
X
0
0
0
0
0
0
X
X
X
X
0
0
0
0
1
0
w a it tim e > 1 0 m s
D is p la y c le a r
R S R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
X
X
X
X
0
0
0
0
0
0
X
X
X
X
0
0
1
I/D S
0
In itia liz a tio n e n d
Newhaven Display International, LLC
Page 15 of 22
NHD-12864EZ
L C D
M
O D U L E
B IG -5
A140
A150
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Newhaven Display International, LLC
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NHD-12864EZ
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B1A0 V W X Y Z [ \ ] ^ _ ` a
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B3E0 O P Q R S T U V W X Y Z [ \ ] ^
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B540 K L M N O P Q R S T U V W X Y Z
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B670 X Y Z [ \ ] ^ _ ` a
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B6F0 V W X Y Z [ \ ] ^ _ ` a
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Page 17 of 22
NHD-12864EZ
B850 R S T U V W X Y Z [ \ ] ^ _ ` a
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BB60 Y Z [ \ ] ^ _ ` a
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BBE0 W X Y Z [ \ ] ^ _ ` a
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BEE0 N O P Q R S T U V W X Y Z [ \ ]
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C0D0 X Y Z [ \ ] ^ _ ` a
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C160 G H I J K L M N O P Q R S T U V
C170 W X Y Z [ \ ] ^ _ ` a
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C1F0 U V W X Y Z [ \ ] ^ _ ` a
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Page 18 of 22
NHD-12864EZ
C3D0 O P Q R S T U V W X Y Z [ \ ] ^
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C4F0 L M N O P Q R S T U V W X Y Z
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C650 H I J K L M N O P Q R S T U V W
C660 X Y Z [ \ ] ^ _ ` a
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CAC0 Q R S T U V W X Y Z [ \ ] ^ _ `
CAD0 a
CAE0
CAF0 ! " # $ % & ' ( ) * + , - . /
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CB60 P Q R S T U V W X Y Z [ \ ] ^ _
CB70 ` a
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CDD0 X Y Z [ \ ] ^ _ ` a
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CE70 W X Y Z [ \ ] ^ _ ` a
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CEE0 E F G H I J K L M N O P Q R S T
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CFA0 C D E F G H I J K L M N O P Q
CFB0 R S T U V W X Y Z [ \ ] ^ _ ` a
Page 19 of 22
NHD-12864EZ
CFC0
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D8D0 W X Y Z [ \ ] ^ _ ` a
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DB50 P Q R S T U V W X Y Z [ \ ] ^ _
Page 20 of 22
NHD-12864EZ
DB60 ` a
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E850 M N O P Q R S T U V W X Y Z [ \
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