NJU26040V-16A

NJU26040-16A Digital Signal Processor for 2ch Speaker System ■ General Description The NJU26040-16A is a high performance 24-bit digital signal processor. The NJU26040-16A provides 3D Surround function, Stereo Enhancement function, Equalizer function, Dynamic Bass Boost function, AGC/Limiter function. These kinds of sound functions are suitable for docking speaker, boom box, mini/micro-component, TV, and other speaker system. ■ Package NJU26040V-16A ■ FEATURES - Software • 3D Surround: eala (NJRC Original) • Stable center image and natural sound field • Stereo Enhancement: eala Stereo Expander (NJRC Original) • Reproduce the amazing stereo image even narrow distance between two speakers • Equalizer • 5band biquad filter • Band1, 2, 3 : HPF/Parametric Equalizer/is selectable. • Band4,5 : HPF/Parametric Equalizer/Bass/Treble is selectable. • Master Volume • Dynamic Bass Boost (NJRC Original) • Two-independent-channel processing for high channel separation • AGC/Limiter • Clock for Watch Dog Timer - Hardware • 24bit Fixed-point Digital Signal Processing • Maximum System Clock Frequency • Digital Audio Interface • Digital Audio Format • Master / Slave Mode • Power Supply • Input terminal • Package • Micro computer interface : 38MHz Max : 3 Input port / 2 Output ports 2 : I S 24bit, Left-justified, Right-justified, BCK : 32fs/64fs : Master Mode MCK : 1/2 fclk, 1/3 fclk ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs : 3.3V : 5V Input tolerant : SSOP32 (Pb-Free) 2 : I C bus (standard-mode/100kbps, Fast-mode/400kbps) : Serial interface (4 lines: clock, enable, input data, output data) The detail hardware specification is described in the “ NJU26040 Series Data Sheet (NJU26040_E_REL.pdf)”. Ver.2008-03-06 -1- ! NJU26040-16A ■ Function Block Diagram AD1/SDIN AD2/SSb SCL/SCK 24bit Fixed-point DSP Core SERIAL HOST INTERFACE PROGRAM CONTROL 24-BIT x 24-BIT MULTIPLIER ALU SERIAL AUDIO INTERFACE BCKI LRI BCKO LRO SDI0 SDI1 SDI2 SDA/SDOUT RESETb MCK CLKOUT CLK TIMING GENERATOR ADDRESS GENERATION UNIT SDO0 SDO1 DATA RAM FIRMWARE OTP/RAM WDC General I/O INTERFACE MUTEb PROC SEL Fig. 1 NJU26040-16A Block Diagram ■ DSP Block Diagram AGC Bypass Trim SDI0 AGC eala Master Volume SDI1 SDI1 Input Trim SDI2 SDI2 Input Trim eala Stereo Expander 5band EQ PEQ/HPF/Bass/Treble Dynamic Bass Boost Limiter SDO0 SDO1 either AGC or Limiter Fig. 2 NJU26040-16A Function Diagram -2- Ver.2008-03-06 NJU26040-16A ■ Pin Configuration VDD SDA/SDOUT SCL/SCK AD1/SDIN AD2/SSb RESETb VDD VDD VSS CLKOUT CLK SDI2 SDI1 SDI0 LRI BCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS TEST TEST SEL PROC MUTEb WDC VDD VSS TEST MCK TEST SDO1 SDO0 LRO BCKO Fig. 3 NJU26040-16A Pin Configuration Ver.2008-03-06 -3- ! NJU26040-16A ■ Pin Description Table 1 Pin Description Pin No. Symbol 1, 7, 8, 25 VDD 2 SDA / SDOUT I/O OD Description Power Supply +3.3V 2 I C I/O / 4-wire Serial Output This pin requires a pull-up. 2 I C Clock / Serial Clock 2 I C Address / Serial Input 2 I C Address / Serial Enable Reset (RESETb=’Low’: DSP Reset) GND OSC Output OSC Clock Input Audio Data Input 2 Audio Data Input 1 Audio Data Input 0 LR Clock Input Bit Clock Input Bit Clock Output LR Clock Output Audio Data Output 0 Audio Data Output 1 for Test (Do not connect) Master Clock Output for A/D, D/A for Test (connect to VSS) Watch Dog Clock Output (Open drain output) Master Volume level, After Reset DSP ,“1”:0dB, “0”: Mute After Reset DSP, “1”: Normal, “0”: Wait for start command 2 2 Select I C or Serial bus (“1”: Serial / “0”: I C-bus) 3 SCL / SCK I 4 AD1 / SDIN I 5 AD2 / SSb I 6 RESETb I 9, 24, 32 VSS 10 CLKOUT O 11 CLK I 12 SDI2 I 13 SDI1 I 14 SDI0 I 15 LRI I BCKI I 16 17 BCKO O 18 LRO O 19 SDO0 O 20 SDO1 O 21 TEST O 22 MCK O TEST I23, 30, 31 26 WDC I/O + 27 MUTEb I/O 28 PROC I/O 29 SEL I/O Note : I : Input I: Input (Pull-down) O : Output O + : Output (with Pull-up resistance) OD : Bi-directional (Open Drain) This pin requires a pull-up resistance. -4- Ver.2008-03-06 NJU26040-16A ■ Digital Audio Interface The NJU26040-16A audio interface provides industry standard serial data format of I S. The NJU26040-16A audio interface provides three audio data inputs, two audio data outputs as shown in table 2, table 3. Table 2 Pin No. 14 13 12 Table 3 Pin No. 19 20 Serial Audio Input Pin Symbol SDI0 SDI1 SDI2 Description Audio Data Input 0 L / R Audio Data Input 1 L / R Audio Data Input 2 L / R 2 Serial Audio Output Pin Symbol SDO0 SDO1 Description Audio Data Output 0 L / R Audio Data Output 1 L / R ■ Host Interface The NJU26040-14A can be controlled via Serial Host Interface (SHI) using either of two serial bus formats:I C bus or 4-Wire serial bus.(Table 4) Data transfers are in 8-bit packets (1 byte) when using either format. Table 4 Serial Host Interface Pin Description Pin No. 29 Symbol SEL Setting “Low” “High” Host Interface 2 I C bus 4-Wire serial bus 2 Table 5 Serial Host Interface Pin Description Symbol 2 Pin No. I C bus Format 2 (I C bus / Serial) Serial Data Input/Output 2 SDA / SDOUT * (Open Drain Input/Output) 3 SCL / SCK * Serial Clock 2 4 AD1 / SDIN * I C bus address Bit1 2 5 AD2 / SSb * I C bus address Bit2 4-Wire Serial bus Format Serial Data Output (Open-Drain Output) Serial Clock Serial Data Input Serial enable Note : SDA pin is a bi-directional open drain. 2 This pin requires a pull-up resistance in both I C bus and 4-Wire serial mode. When the power supply (VDD= +3.3V) is supplied to NJU26040-16A, these pins become +5.0V Input tolerant. Ver.2008-03-06 -5- ! NJU26040-16A ■ I2C bus I C bus interface transfers data to the SDA pin and clocks data to the SCL pin. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26040-16A. An address can be 2 arbitrarily set up by the AD1 and AD2 pins. The I C address of AD1/AD2 is decided by connection of AD1/AD2 pins. Table 6 I C bus SLAVE Address bit7 0 0 0 0 bit6 0 0 0 0 bit5 1 1 1 1 bit4 1 1 1 1 bit3 1 1 1 1 AD2 bit2 0 0 1 1 AD1 bit1 0 1 0 1 R/W bit0 R/W 2 2 Start bit Slave Address ( 7bit ) R/W bit ACK * SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”. 2 Note : The serial host interface supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I C bus data transfer. ■ 4-Wire Serial Interface SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low ( SSb=0 ). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb. SDOUT is Hi-Z in case of SSb = “High”. SDOUT is Open-drain output in case of SSb = “Low”. SDOUT needs a pull-up resistor when SDOUT is Hi-Z. SSb SCK SDIN SDOUT Hi-Z bit7 MSB bit6 bit6 bit5 bit5 bit1 bit1 bit0 LSB bit7 bit0 unstable Hi-Z Fig.4 4-Wire Serial Interface Timing Note: When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb=”High”. When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”. -6- Ver.2008-03-06 NJU26040-16A ■ Pin setting The NJU26040-16A operates default command setting after resetting the NJU26040-16A. In addition, the NJU26040-16A restricts operation at power on by setting PROC pin and MUTEb pin (Table 8). These pins are input pin. However, these pins operate as bi-directional pins. Connect with VDDIO or VSSIO through 3.3kΩ resistance. Table 7 Pin setting Pin No. Symbol Setting “High” 28 PROC “Low” 27 MUTEb “High” “Low” Function The NJU26040-16A operates default setting after reset. The NJU26040-16A does not operate after reset. Sending start command is required for starting operation. Master volume is set 0dB after reset. Master volume is set mute after reset. ■ Watch Dog Clock The NJU26040-16A outputs clock pulse through WDC (No.26) pin during normal operation. (Table 9) Table 8 Watch Dog Clock Output Cycle WDC Output Cycle (Low/High) Time 100ms The NJU26040-16A generates a clock pulse through the WDC terminal after resetting the NJU26040-16A. The WDC clock is useful to check the status of the NJU26040-16A operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26040-16A. When the WDC clock pulse is lost or not normal clock cycle, the NJU26040-16A does not operate correctly. Then reset the NJU26040-16A and set up the NJU26040-16A again. Note: If input and output of an audio signal stop and an audio interface stops, WDC can’t output. That is because it has controlled based on the signal of an audio interface. Ver.2008-03-06 -7- ! NJU26040-16A ■ NJU2604016A Command Table Table 9 NJU26040-16A Command No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Command System State Command Sample Rate Select Command Set Task Command Smooth Control Config Command Master Volume Control Command Master Volume Balance Setup Command AGC/Limiter Threshold Level Command AGC/Limiter Noise Compressor Level Command AGC/Limiter Ratio Command AGC/Limiter Attack Time / Release Time Command AGC/Limiter Output Boost Command AGC Bypass Trim Command SDI1 Input Trim Command SDI2 Input Trim Command eala Surround Gain Command No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Command eala Stereo Expander Effect mode Command EQ Mode Setup Command EQ f0 Command EQ Q Command EQ Gain Command DBB Start Level Command DBB Limit Level Command DBB Effect Command DBB Control Command DBB Attack Time / Release Time Command DBB LPF fc Command DBB Treble Boost Level Command Version No. Request Command Revision No. Request Command Start Command No Operation Command Notes : In respect to detail command information, request New Japan Radio Co., Ltd. Ver. 1.00 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -8- Ver.2008-03-06