NJU26120

NJU7384 Pulse Input Bipolar Stepper Motor Driver s PACKAGE OUTLINE s GENERAL DESCRIPTION NJU7384 is a bipolar drive stepping motor driver. The control method used is a simple pulse train input control (STEP & DIR) method of programming. Also, low power consumption was realized as a result of the adoption of a highly efficient CMOS. As the control functions, the external input RESET and ENABLE functions are used, and as the protective function, a thermal shutdown (TSD) is incorporated. The package uses the low thermal resistance SSOP32 which NJU7384V can withstand a high output current. s FEATURES • Operating Voltage 3.0 to 5.5V（Logic : VDD） 4.0 to 8.0V（H bridge : VMM） • Maximum Output Current 700mA/ch • Pulse Input (STEP＆DIR) Control • Half / Full Step Change Function • Thermal Shutdown Circuit • Thermal Shutdown Alarm Output • RESET Function • ENABLE Function • CMOS Technology • Package Outline SSOP32 s BLOCK DIAGLAM VDD VMM1 GATE DRIVE STEP OUTA1 OUTA2 DIR CONTROL LOGIC TRANSLATOR PGNG1 VMM2 GATE DRIVE HSM RESET OUTB1 OUTB2 ENABLE PGND2 GND TSD TSD ALARM Ver.2007-08-20 -1- NJU7384 s PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1. NC 2. NC 3. NC 4. VDD 5. NC 6. STEP 7. DIR 8. HSM 9. RESET 10. ENABLE 11. TSD ALARM 12. NC 13. GND 14. NC 15. NC 16. NC 32. VMM1 31. VMM1 30. OUTA1 29. OUTA1 28. OUTA2 27. OUTA2 26. PGND1 25. PGND1 24. PGND2 23. PGND2 22. OUTB2 21. OUTB2 20. OUTB1 19. OUTB1 18. VMM2 17. VMM2 s PIN DESCRIPTION PIN No. 1,2,3 4 5 6 7 8 9 10 11 12 13 14,15,16 17,18 19,20 21,22 23,24 25,26 27,28 29,30 31,32 SYMBOL NC VDD NC STEP DIR HSM RESET ENABLE TSD ALARM NC GND NC VMM2 OUTB1 OUTB2 PGND2 PGND1 OUTA2 OUTA1 VMM1 FUNCTION Non connection pins Logic Power-Supply input pin Non connection pin Pulse signal input pin for motor rotation control pin Forward / Reverse rotation control Full / Half step mode control pin Phase initialize signal input pin NOTE 1 pulse input ⇒ 1 clock motion “H”= Forward (CW), ”L”= Reverse (CCW) “H”= Full step, ”L”= Half step “H”= Normal operation, ”L”= Phase initialize Output signal all off control signal “H”= Normal operation, input pin ”L”= Output all off TSD alarm output pin TSD operating =”L” signal output Connect to motor power-supply Connect to motor power-supply Non connection pins Logic ground (GND) pin Non connection pins H bridge power-supply pins Output pin B1 Output pin B2 H bridge ground (GND) pin H bridge ground (GND) pin Output pin A2 Output pin A1 H bridge power-supply pins * Short all logic ground terminals and the H bridge ground terminal externally. * Short all H bridge power supply voltage terminals externally. * Fix the potential of unused logic input terminals externally. -2- Ver.2007-08-20 NJU7384 s ABSOLUTE MAXIMUM RATINGS PARAMETER Logic Power Supply Voltage H Bridge Power Supply Voltage Logic Input Voltage Motor Output Current (Max) Logic Input Current Operating Temperature Range Operating Junction Temperature Range Storage Temperature Rnage Power Dissipation *1) : VDD ≤ VMM *2) : EIAJ/JEDEC STD 2 Layer substrate (Ta=25°C) RATINGS +7.0 +9.0 -0.3 ~ VDD 700 10 -40 ~ +85 -40 ~ +150 -50 ~ +150 1175 SYMBOL(unit) VDD (V) VMM (V) VID (V) IOPEAK(mA/ch) IIPEAK (mA) Topr (°C) Tj(°C) Tstg(°C) PD (mW) NOTE *1) *2) s RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN. Logic Power Supply Voltage 3.0 VDD Range H Bridge Power Supply 4.0 VMM Voltage Range Logic H Input Voltage Logic L Input Voltage STEP-ON Time STEP-OFF Time Data Setup Time Hold Time Input Clock Frequency VIH VIL tONMIN tOFFMIN tDS tDH fCLK 3.5 0 10 10 1 1 - TYP. 5.0 6.0 - MAX. 5.5 8.0 VDD 1.2 50 UNIT V V V V µs µs µs µs kHz (Ta=25°C) NOTE VDD ≤ VMM - VDD=5.0V, No load Ver.2007-08-20 -3- NJU7384 s ELECTRICAL CHARACTERISTICS PARAMETER ■General I DD Operating Current I MM Thermal Shutdown Operating Temperature Thermal Shutdown Hysteresis TTSD THYS STEP, DIR, HSM, RESET, ENABLE=”5V”, No Load, VDD Meas. STEP, DIR, HSM, RESET, ENABLE=”5V”, No load, VMM Meas. 0.3 0.3 180 30 0.6 0.6 mA mA °C °C SYMBOL CONDITION MIN. (Ta=25°C, VDD=5V, VMM=6V) TYP. MAX. UNIT ■Input (STEP, DIR, HSM, ENABLE, RESET Terminals) Logic Input Current ■H Bridge (Output) H Output Voltage L Output Voltage Upper Side Output ON Resistance Under Side Output ON Resistance Output Leak Current ■Signal Output TSD Alarm L Output Voltage TSD Pull-up Resistance VTSD RTSD No external pull-up resistance IIH IIL STEP, DIR, HSM, ENABLE, RESET =”5V” STEP, DIR, HSM, ENABLE, RESET =”0V” -1 - 1 - µA µA VOH VOL ROH ROL IO LEAK Io=+400mA Io= -400mA Io=400mA Io=400mA - 5.5 - 5.7 0.2 0.75 0.50 1.0 0.4 1.25 1.00 - V V Ω Ω µA - 10 0.3 - V kΩ - -4- Ver.2007-08-20 NJU7384 s TIMING CONDITION t ONMIN t OFFMIN STEP 50% t DS DIR,HSM, RESET, ENABLE t DH s TRUTH TABLE LOGIC IN VDD DIR HSM RESET ENABLE H L H L H L H L H L MODE OPERATE Hi Z CW CCW FULL STEP HALF STEP OPERATE RESET OPERATE Hi Z *VMM : Motor voltage supply *OPERATE : Follow the input logic *Hi Z : Output all off (A1, A2, B1,B2) s EXCITATION SEQUENCE Condition: FULL STEP, HSM=ENABLE=RESET 0 1 2 3 Pulse OUTA1 L H H L OUTA2 H L L H OUTB1 L L H H OUTB2 H H L L IA + + IB + + DIR=HIGH CW DIR=LOW CCW Condition: HALF STEP, HSM=LOW, ENABLE=RESET=HIGH Pulse OUTA1 OUTA2 OUTB1 OUTB2 IA IB DIR=HIGH DIR=LOW 0 L H L H CW CCW 1 Hi Z Hi Z L H 0 2 H L L H + 3 H L Hi Z Hi Z + 0 4 H L H L + + 5 Hi Z Hi Z H L 0 + 6 L H H L + 7 L H Hi Z Hi Z 0 * Regarding the current flow direction, the direction A1→A2 and B1→B2 is indicated as +, and the direction A2→A1 and B2→B1 is indicated as –. Ver.2007-08-20 -5- NJU7384 s POWER SUPPLY ON/OFF TIMING Regarding the switch-on sequence of the logic power supply VDD and the motor power supply VMM, input VDD after VMM has risen. The recommended sequence is shown below. ON VDD ≤ VMM VDD ≤ VMM OFF VMM VDD The RESET signal is "L" level in the range of turning ON . And Phase logic is initialized. RESET The STEP terminal is a negative edge active. If STEP input terminal is no Signal. It signal level is fixed at “H “ level . STEP HSM/DIR ENABLE IA IB Excitation phase backup section Phase logic initialization section s RECOMMENDED STEP MODE CHANGEOVER (HSM) The current flowing through the stepping motor must be controlled continuously so that a mis-step does not occur. Also, the following precautions must be observed concerning changing of the setting of the HSM input. (1) A mis-step does not occur during changeover from a full step to a half step (2) Regarding changeover from a half step to a full step, (a) A mis-step does not occur during changeover from a half step (excitation sequence 0, 2, 4, 6) to a full step. (b) A mis-step occurs during changeover from a half step (excitation sequence 1, 3, 5, 7) to a full step. For the above reason, it is recommended that mode changeover from a half step to a full step be carried out during the period when the RESET input is “L” logic. -6Ver.2007-08-20 NJU7384 s TIMING CHART • Fixed mode (Full step / Forward direction) Condition : DIR=”H”, HSM=”H” VMM, VDD DIR HSM excitation sequence No. 0 STEP 1 2 3 4 RESET ENABLE IA IB Ver.2007-08-20 -7- NJU7384 • Direction change (Full step / Forward direction ⇒ Reverse direction) Condition : DIR=”H” ⇒ ”L”, HSM=”H” VMM, VDD DIR HSM excitation sequence No. 0 STEP 1 2 1 0 3 2 1 RESET ENABLE IA IB -8- Ver.2007-08-20 NJU7384 • Step mode change (Full step ⇒ Half step) Condition : DIR=”H”, HSM=”H” ⇒ ”L” VMM, VDD DIR HALF STEP sequence HSM excitation sequence No. 0 STEP 1 2 5 6 7 0 1 0 1 2 3 4 5 6 7 0 RESET ENABLE IA IB Ver.2007-08-20 -9- NJU7384 s APPLICATION CIRCUIT V MM(+6V) + V DD(+5V) µ-COM CMOS,TTL-LS Input/Output Device STEP STEP V DD + GND(V MM) V MM1 GATE DRIVE OUTA1 OUTA2 PGND1 STEPPER M CW/CCW FULL/HALF HSM TRANSLATOR DIR CONTROL LOGIC V MM2 GATE DRIVE RESET RESET OUTB1 OUTB2 PGND2 TSD ALARM NORMAL/INHIBIT ENABLE THERMAL SENSOR GND TSD GND(V DD) GND(V MM) [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 10 - Ver.2007-08-20