NJU26123V

NJU26123 ■ General Description Digital Signal Processor for TV ■Package The NJU26123 is a high performance 24-bit digital signal processor. The NJU26123 provides ‘NJRC Original Sound Enhancement’, ‘Lip sync Audio Delay’, 10band PEQ, HPF/LPF (FIR Filter), DRC, Tone Control, and Clipper. These kinds of sound functions are suitable for TV, mini-component, CD radio-cassette, speakers system and other audio products. ■ FEATURES - Software • NJRC Original Sound Enhancement (3D sound, Dialogue Boost, Bass Enhance) • Delay for Lip sync Audio Delay ( fs=48kHz : Max. 36msec, fs=44.1kHz : Max. 39msec, fs=32kHz : Max. 54msec ) • 10Band PEQ • HPF/LPF (FIR Filter) • DRC (Dynamic Range Compression) : 2-bands independent operation • Tone Control • Clipper • Master Volume • WatchDog Clock Output NJU26123V - Hardware • 24bit Fixed-point Digital Signal Processing • Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit • Digital Audio Interface : 3 Input ports / 3 Output ports • Digital Audio Format : I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs • Master / Slave Mode - Master Mode, MCK : 384fs @32kHz, 256fs @48kHz • Host Interface : I2C bus (Fast-mode/400kbps) • Power Supply : 3.3V • Input terminal : 5V Input tolerant • Package : SSOP24 (Pb-Free) Ver.2008-04-17 -1- NJU26123 ■ Function Block Diagram SCL I C INTERFACE SDA PROGRAM CONTROL 24Bit x 24Bit MULTIPLIER ALU TIMING GENERATOR / PLL ADDRESS GENERATION UNIT SERIAL AUDIO INTERFACE SDO0-2 BCK LR 2 24Bit Fixed-point DSP Core SDI0-2 RESETb MCK CLKOUT CLK SLAVEb Internal Pow er (1.8V) WDC FIRMWARE ROM GPIO INTERFACE PROC AD1 Built-in LDO VREGO External Low -ESR Capacitors Required DATA RAM 1.8V level terminal Fig. 1 NJU26123 Block Diagram -2- Ver.2008-04-17 NJU26123 ■ DSP Block Diagram SDI0 SDI1 SDI2 NJRC Original Sound Enhancement EXEC Volume & L/R Trimmer Input Trimmer Delay PEQ SW1 Tone Control SW2 SW4 (DRC enable / disable) HPF EXEC Output LPF SW DRC(HPF) SW SW HPF Output LPF Output DRC Mixer SW SW PROC Output DRC(LPF) SW SW3 (DRC XOVER enable / disable) C/SW Mixer C/SW Output EXEC Output HPF Output LPF Output PROC Output C/SW Output SDO0/1/2 Source Select SDO0 SDO0 Clipper (L/R) SDO0 SW5 SDO1 Master Volume & Channel Trimmer SDO1 Clipper (R) SDO1 SW6 SDO2 SDO2 SDO2 Fig. 2 NJU26123 Function Diagram Ver.2008-04-17 -3- NJU26123 ■ Pin Configuration RESETb LR BCK SDI2 SDI1 SDI0 MCK VDD VSS STBYb VSS VREGO 1 2 3 4 5 6 7 8 9 10 11 12 NJU26123 24 23 22 21 20 19 18 17 16 15 14 13 TEST SCL SDA SDO2 SDO1 SDO0 WDC PROC AD1 SLAVEb CLK CLKOUT SSOP24 Fig. 3 NJU26123 Pin Configuration ■ Pin Description Table 1 Pin Description No. Symbol I/O Description No. Symbol I/O Description 1 RESETb I RESET (active Low) 13 CLKOUT O OSC Output 2 LR I/O LR Clock 14 CLK I OSC Clock Input 3 BCK I/O Bit Clock 15 SLAVEb I Slave select 4 SDI2 I Audio Data Input 2 L/R 16 AD1 I I2C Address 5 SDI1 I Audio Data Input 1 L/R 17 PROC I Status select after Reset DSP 6 SDI0 I Audio Data Input 0 L/R 18 WDC OD Clock for Watch Dog Timer 7 MCK I/O Master Clock 19 SDO0 O Audio Data Output 0 L/R 8 VDD Power Supply +3.3V 20 SDO1 O Audio Data Output 1 L/R 9 VSS GND 21 SDO2 O Audio Data Output 2 L/R 10 STBYb I For TEST (Connected to VDD) 22 SDA OD I2C I/O 11 VSS GND 23 SCL I I2C Clock 12 VREGO PI Built-in Power Supply Bypass 24 TEST I For TEST(Connected to VSS) * I : Input, O : Output, I/O: Bi-directional, OD: Open-Drain I/O, PI: Power Supply Bypass AD1 (No.16) pin and PROC (No.17) pin are input pins. WDC (No.18) pin is open-drain pin with pull-up resistance. However, these pins operate as bi-directional pins. No.16pin and No.17pin connect with VDD or VSS through 3.3kΩ resistance. No.18pin do not connect or connect with VDD through 3.3kΩ resistance when unused. VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel between VSS (No.11) pin. A built-in power supply is used only for NJU26123 operation. Be not short-circuited of this pin. Do not take out the current, and connect other power supplies. -4- Ver.2008-04-17 NJU26123 ■ Absolute Maximum Ratings ( VSS=0V=GND, Ta=25°C ) Rating Units Table 2 Absolute Maximum Ratings Parameter Symbol Supply Voltage * Supply Voltage Bypass * In I/O, OD Pin Voltage * Out CLK CLKOUT Power Dissipation Operating Voltage Storage Temperature VDD VREGO Vx(IN) Vx(I/O) ,Vx(OD) Vx(OUT) Vx(CLK) Vx(CLKOUT) -0.3 to 4.2 -0.3 to 2.3 -0.3 to 5.5 (VDD ≥ 3.0V) -0.3 to 4.2 (VDD < 3.0V) V V V -0.3 to 4.2 565 mW PD -40 to 85 TOPR °C TSTR -40 to 125 °C * The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent damage to the LSI. * VDD : 8 pin * VREGO : 12 pin * Vx(IN) : 1, 4, 5, 6, 10, 15, 23, 24 pin * Vx(OD) : 22 pin * Vx(I/O) : 2, 3, 7, 16, 17, 18 pin * Vx(OUT) : 19, 20, 21 pin * Vx(CLK) : 14 pin * Vx(CLKOUT) : 13 pin VDD VDD(1.8V) VDD VDD(1.8V) ■ Terminal equivalent circuit diagram PAD RPD CLK CLKOUT SS Input, I/O (Input part) (1 to 7, 22, 23pin) (with RPU : 18pin , With RPD: 15, 16, 17, 24pin) V VSS CLK/CLKOUT (13, 14pin) VDD RPU PAD Output Disable PAD VDD Output, I/O (Output part) (2, 3, 7, 16, 17, 19, 20, 21pin ) ( Open Drain Output with RPU : 18pin) ( Open Drain Output: 22pin ) VSS VSS STBYb (10pin) Fig.4 NJU26123 Terminal equivalent circuit diagram Ver.2008-04-17 -5- NJU26123 ■ Electric Characteristics Table 3 Electric Characteristics Parameter Operating Voltage Operating Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage *3 *1 ( VDD=3.3V, fOSC=12.288MHz, Ta=25°C ) Symbol VDD IDD VIH VIL VOH VOL IIN (IOH= -1mA) (IOL= 1mA) Test Condition VDD pin At no load Min. 3.0 VDD x 0.7 0 VDD x 0.8 0 -10 VIN = VSS to VDD -120 -10 10 CLK, MCK *6 Typ. 3.3 20 12.288 50 Max. 3.6 35 VDD *2 Units V mA VDD x 0.3 VDD VDD x 0.2 10 10 120 13 3.0 55 V Leakage Current *4 IIN(PU) IIN(PD) µA Clock Frequency Clock Jitter *5 fOSC fJIT(CC) rEC MHz ns % 0 45 Clock Duty Cycle *1 *2 *3 *4 *5 *6 Input pin, Output pin and Open-Drain input/output pin are +5.0V tolerant except CLK input pin. Except No.18pin: WDC (Open-Drain output) and No.22: SDA (Open-Drain input/output). I IN(PU) : 18pin, I IN(PD) : 15, 16, 17, 24 pin Clock Jitter shows Cycle-to-cycle period jitter (JEDEC JESD65). Provide clock frequency for fOSC spec. NJU26123 needs clock frequency 12.288MHz when sampling rate is 48kHz. -6- Ver.2008-04-17 NJU26123 1. Power Supply, Input/Output terminal, Clock, Reset 1.1 Power Supply The NJU26123 has a power supply VDD. To setup good power supply condition, the decoupling capacitors should be implemented at the all power supply terminals. The NJU26123 include a built-in power supply (LDO) for internal logic. A built-in power supply generates 1.8V (-10% to +10%). VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel between VSS (No.11) pin. A built-in power supply is used only for NJU26123 operation. Be not short-circuited of this pin. Do not take out the current, and connect other power supplies. 1.2 Input/Output terminal It restricts, when the input terminals (AD1, PROC, RESETb, SDI0, SDI1, SDI2, STBYb, SLAVEb, SCL, TEST pins), the input/output terminals (LR, BCK, MCK pins) and the bi-directional Open-drain terminal (SDA pin) of NJU26123, and VDD are supplied on regular voltage (VDD=3.3V), and it becomes +5V Input tolerant. 1.3 Clock The NJU26123 CLK pin requires the system clock that should be related to the sample frequency 256 Fs. (For example : Fs=48kHz CLK=12.288MHz ) It is possible to be generated the system clock by connecting a crystal oscillator between CLK and CLKOUT. CLK/CLKOUT pins are not 5V tolerant, so check the voltage level of these pins. When SLAVEb pin is fixed on Low level, NJU26123 supplies the system clock from MCK pin. Fix the clock input pin not used to Low level because either the CLK pin or the MCK pin is supplied in NJU26123. The frequency divider for Master mode matched to the clock 256 times of Fs is installed in NJU26123. When clock except 256 times of Fs is used by Master mode, be careful to use because a dividing frequency of Master mode changes. Please check enough and decide parameter. Ver.2008-04-17 -7- NJU26123 1.4 Reset To initialize the NJU26123, RESETb pin should be set Low level during some period. After some period of Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26123. After the power supply and the oscillation of the NJU26123 becomes stable, RESETb pin must be kept Low-level more than tRESETb period. (Fig.5) After RESETb pin level goes to "High" (after reset release), a setup of the internal hardware of a Serial Host Interface completes NJU26123 within 10msec. Then, it will be in the state which can communicate. VDD tVREGO VREGO OSC unstable OSC stable CLK RESETb tRESETb Fig.5 Reset Timing Table 4 Reset Time Symbol Time tVREGO ≥ 10msec tRESETb ≥ 1.0msec Note : Don’t stop the supply of a clock while operating. NJU26123 installs PLL circuit internally. If the supply of a clock is stopped, PLL circuit cannot be sent a clock to the inside and NJU26123 does not operate normally. If supply of a clock is stopped or the NJU26123 is reset again, putting a normal clock into CLK terminal, the period RESETb terminal of tRESETb is kept “Low” level.(Table 4) Next, the NJU26123 is reset. Then redo from initial setting. -8- Ver.2008-04-17 NJU26123 2. Digital Audio Clock Digital audio data needs to synchronize and transmit between digital audio systems. The NJU26123 - master mode / slave mode - both of the modes are supported. - In Master mode; Use the clock of BCKO and a LRO pin output clock for digital audio data transfer. - In Slave mode; The clock output from a master device is needed for the input terminal of BCKI and LRI. A device in the system generates the transmitted clock become a standard. The other devices are set according to the transmitted clock. The device generating transmitted clock is called Master Device. The device according to the transmitted clock is called Slave Device. NJU26123 usually operates Slave Device. However, NJU26123 becomes Master Device in case of SLAVEb set the High level and NJU26123 is set Master mode by firmware command. In Slave mode, clock inputted to the BCK pin and the LR pin is used to digital audio signal transmission. In Master mode, clock outputted to the BCK pin and the LR pin is used to digital audio signal transmission. 2.1 Audio Clock Three kinds of clocks are needed for digital audio data transfer. (1) LR clock (LR) is needed by serial-data transmission. It is the same as the sampling frequency of a digital audio signal. (2) Bit clock (BCK) is needed by serial-data transmission. It becomes the multiple of LR clock. (3) Master clock (MCK) is needed by A/D, D/A converter, etc. It becomes the multiple of LR clock. It is not related to serial audio data transmission. In SLAVEb is High level, the MCK pin becomes buffer output pin for input clock to the CLK pin after NJU26123 resets. The MCK output is able to be stopped by firmware command. In SLAVEb is Low level, MCK pin becomes system clock input pin. It is not insure to change the logical switch of SLAVEb pin during operating. If it is necessary to change SLAVEb pin setting, reset NJU26123 every time. Table 5 SLAVEb, BCK, LR, MCK SLAVEb and firmware LR pin setting SLAVEb=”Low” LR clock input Firmware: each DSP slave operating SLAVEb=”H” Firmware: Slave SLAVEb=”H” Firmware: Master LR clock output DSP Master operating BCK pin Bit clock input DSP slave operating Bit clock output DSP Master operating MCK pin NJU26123 operating clock input (MCK or CLK) Master clock output (Buffer of CLK) In NJU26123 is used by 256 times of Maximum sampling frequency, NJU26123 is able to output LR clock of same sampling rate and two-third times of sampling rate, and output BCK clock of 32 times sampling rate and 64 times sampling rate in Master mode. Ver.2008-04-17 -9- NJU26123 Table 6 Input clock (In Slave mode) Mode Clock Signal Multiple Frequency 32kHz 44.1kHz 48kHz LR 1fs 32kHz 44.1kHz 48kHz BCK (32fs) 32fs 1.024MHz 1.4112MHz 1.536MHz BCK (64fs) 64fs 2.048MHz 2.822MHz 3.072MHz DSP MCK Slave Input terminal: Clock is generated by MCK or CLK (SLAVEb=”L”) MCK Buffer output of CLK 12.288MHz (SLAVEb=”H”) Table 7 Output clock (In Master mode) Mode DSP Master Clock Signal LR BCK (32fs) BCK (64fs) MCK Multiple Frequency 1fs 32fs 64fs Buffer output of CLK 32kHz 32kHz 1.024MHz 2.048MHz CLK pin frequency 44.1kHz 48kHz 48kHz 1.536MHz 3.072MHz 12.288MHz - 10 - Ver.2008-04-17 NJU26123 3. Digital Audio Interface 3.1 Digital Audio Data Format The NJU26123 can use three kinds of formats hereafter as industry-standard digital audio data format. : MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing) (1) I2S (2) Left-justified : LR clock -- MSB is placed for changing. (3) Right-justified : LSB is placed just before LR clock change rate. The main differences among three kinds of formats are in the position relation between LR clock (LR) and an audio data (SDI, SDO). - In every format: : a left channel is transmitted previously. - In Right/Left-justified : LR clock ='High' shows a left channel. - I2S : LR clock=”Low” shows a left channel. - The Bit clock BCK is used as a shift clock of transmission data. The number of clocks more than the number of sum total transmission bits of a L/R channel is needed at least. - One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes equal to a sample rate (Fs). - The NJU26123 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks. This serial data format is applied to both MASTER and SLAVE mode. 3.2 Serial Audio Data Input/output The NJU26123 audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output lines: SDO0, SDO1 and SDO2. (Table 9). Table 8 Serial Audio Input Pin Description Pin No. Symbol Description 6 SDI0 Audio Data Input 0 L/R 5 SDI1 Audio Data Input 1 L/R 4 SDI2 Audio Data Input 2 L/R Table 9 Serial Audio Output Pin Description Pin No. Symbol Description 19 SDO0 Audio Data Output 0 L/R 20 SDO1 Audio Data Output 1 L/R 21 SDO2 Audio Data Output 2 L/R Ver.2008-04-17 - 11 - NJU26123 The NJU26123 can use three kinds of formats hereafter as industry-standard digital audio data format; (1) I2S (2) Left-Justified (3) Right-justified and 16 / 18 / 20 / 24bits data length. (Fig.6-1 to Fig6-12) An audio interface input and output data format become the same data format. LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-1 I2S Data Format 64fs, 24bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB 23 Left Channel Right Channel SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-2 Left-Justified Data Format 64fs, 24bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-3 Right-Justified Data Format 64fs, 24bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-4 I2S Data Format 64fs, 20bit Data LRI, LRO BC BCKO KI, M SB LSB 32 Clocks M SB 32 Clocks LSB 19 Left Channel Right Channel SDI, SDO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-5 Left-Justified Data Format 64fs, 20bit Data LRI, LRO BC BC KI, KO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SD 2 1 0 O 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-6 Right-Justified Data Format 64fs, 20bit Data - 12 - Ver.2008-04-17 NJU26123 LRI, LRO BC BC KI, KO M SB Left Channel Right Chann el LSB 32 Clocks M SB 32 Clock s LSB SD SD I, O 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-7 I2S Data Format 64fs, 18bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB 17 Left Channel Right Channel SDI, SDO 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-8 Left-Justified Data Format 64fs, 18bit Data LRI, LRO BC BC KI, KO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SD SD 2 1 0 I, O 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-9 Right-Justified Data Format 64fs, 18bit Data LRI, LRO BCKI, BCKO M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-10 I2S Data Format 32fs, 16bit Data LRI, LRO BCKI, BCKO M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-11 Left-Justified Data Format 32fs, 16bit Data LRI, LRO BCKI, BCKO M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6-12 Right-Justified Data Format 32fs, 16bit Data Ver.2008-04-17 - 13 - NJU26123 3.3 Serial Audio Input Timing Table 10 Serial Audio Input Timing Parameters Parameter Symbol Test Condition BCK Frequency * BCK Period * Low Pulse Width High Pulse Width BCK to LR Time ** LR to BCK Time ** Data Setup Time Data Hold Time fBCKI tSIL tSIH tSLI tLSI tDS tDH Min 75 75 40 40 15 15 ( VDD=3.3V, Ta=25°C ) Typ. Max Units 6.5 MHz ns ns ns ns ns * It is the regulation of absolute maximum ratings. Maximum frequency of BCK is limited. ** It is the regulation in slave mode. LR tSIH tSIL tSLI tLSI BCK tDS tDH SDI Fig.7 Serial Audio Input Timing Table 11 Serial Audio Output Timing Parameters Parameter Symbol Test Condition BCK to LR Time * Data Output Delay tSLO tDOD CL=25pF ( VDD=3.3V, Ta=25°C ) Typ. Max Units Min -15 - - 15 15 ns ns * It is the regulation in Master mode. LR tSLO BCK tDOD SDO Fig.8 Serial Audio Input Timing - 14 - Ver.2008-04-17 NJU26123 ■ Host Interface The NJU26123 can be controlled via Serial Host Interface (SHI) using I2C bus. Data transfers are in 8 bit packets (1 byte) when using either format. Refer to serial Host Interface Pin Description.(Table 12) Table 12 Serial Host Interface Pin Description Symbol Pin No. I2C bus Format (I2C bus) 16 AD1 I2C bus address Bit Serial Data Input/Output 22 SDA (Open Drain Input/Output) 23 SCL Serial Clock Note : SDA pin (No.22) is a bi-directional open drain terminal. This pin requires a pull-up resister. AD1 (No.16) pin is input pin with pull-down. AD1 (No.16) pin is connected with VDD or VSS through 3.3kΩ resistance. When NJU26123 is stopped by power supply VDD, SDA pin and SCL pin become Hi-Z. But these pins are not 5V tolerant when VDD stops. ■ I2C bus I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. SDA pin is a bi-directional open drain and requires a pull-up resister. AD1 pin is used to configure the seven-bit SLAVE address of the serial host interface. (Table 13) This offers additional flexibility to a system design by two different SLAVE addresses of the NJU26123. An address can be arbitrarily set up by the AD1 pin. The I2C address of AD1 is decided by connection of AD1 pin. Table 13 I2C bus SLAVE Address bit7 0 0 bit6 0 0 bit5 1 1 bit4 1 1 bit3 1 1 bit2 0 0 AD1 bit1 0 1 R/W bit0 R/W Start bit Slave Address ( 7bit ) R/W bit ACK * SLAVE address is 0 when AD1 is “Low”. SLAVE address is 1 when AD1 is “High”. * SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”. Note : The serial host interface supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I2C bus data transfer. Ver.2008-04-17 - 15 - NJU26123 Table 14 I2C bus Interface Timing Parameters Parameter SCL Clock Frequency Start Condition Hold Time SCL “Low” Duration SCL “High” Duration Start Condition Setup Time Data Hole Time *1 Data Setup Time Rising Time Falling Time Stop Condition Setup Time Bus Release Time *2 Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF ( VDD=3.3V, fOSC=12.288MHz, Ta=25°C ) Min 0 0.6 1.3 0.6 0.6 0 250 0.6 1.3 Max 400 0.9 1000 300 - Units kHz µs µs µs µs µs ns ns ns µs µs SDA tBUF tR tF tHD:STA SCL tHD:STA t LOW P S tHD:DAT tHIGH 2 tSU:DAT Sr tSU:STA tSU:STO P Fig.9 I C bus Timing Note : *1 tHD:DAT: Keep data 100ns hold time to avoid indefinite state by SCL falling edge. *2 This item shows the interface specification. The interval of a continuous command is specified separately. - 16 - Ver.2008-04-17 NJU26123 ■ Pin setting The NJU26123 operates default command setting after resetting the NJU26123. In addition, the NJU26123 restricts operation at power on by setting PROC pin (No.17) (Table 15). This pin is input pin. However, this pin operates as bi-directional pin. Connect with VDD or VSS through 3.3kΩ resistance. Table 15 Pin setting Pin No. Symbol Setting “High” 17 PROC “Low” Function The NJU26123 does not operate after reset. Sending start command is required for starting operation. The NJU26123 operates default setting after reset. The default value of Master Volume is Mute. ■ WatchDog Clock The NJU26123 outputs clock pulse through WDC (No.18) pin during normal operation. The NJU26123 generates a clock pulse through the WDC terminal after resetting the NJU26123. The WDC clock is useful to check the status of the NJU26123 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26123. When the WDC clock pulse is lost or not normal clock cycle, the NJU26123 does not operate correctly. Then reset the NJU26123 and set up the NJU26123 again. Watchdog clock output cycle is about 170msec. Note: If input and output of an audio signal stop and an audio interface stops, WDC can’t output. That is because it has controlled based on the signal of an audio interface. Ver.2008-04-17 - 17 - NJU26123 ■ NJU26123 Command Table Table 16 NJU26123 Command No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Set Task Fs Select Smooth Control Input Select SDO0 Output Source Select SDO1 Output Source Select SDO2 Output Source Select DRC Mode Select DRC Xover Frequency Select Delay Setup System Status Tone Control (Bass@100Hz) Tone Control (Treble@10kHz) Clipper (SDO0_L/R) Limit Level Setup Clipper (SDO0_L/R) Boost Level Setup Clipper (SDO1_R) Limit Level Setup Command No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Trimmer Setup DRC (HPF) Ratio & Attack/Release Time Setup DRC (LPF) Ratio & Attack/Release Time Setup DRC (HPF) Level Setup DRC (LPF) Level Setup PEQ Setup Sound Enhancement Setup User Define Xover Filter Coefficient Setup Firmware Version Number Request Firmware Revision Number Request Software Reset Boot with Mute Boot with Unmute No Operation (Nop) Command Clipper (SDO1_R) Boost Level Setup . - 18 - Ver.2008-04-17 NJU26123 ■ Package SSOP24, Pb-Free [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2008-04-17 - 19 -